PRELIMINARY Integrated Circuit Systems, Inc. ICS8343I-01 LOW SKEW, 1-TO-16 LVCMOS / LVTTL FANOUT BUFFER GENERAL DESCRIPTION FEATURES The ICS8343I-01 is a low skew, 1-to-16 LVCMOS/LVTTL Fanout Buffer and a member of HiPerClockS™ the HiPerClockS™ family of High Performance Clock Solutions from ICS. The ICS8343I-01 single ended clock input accepts LVCMOS or LVTTL input levels. The ICS8343I-01 operates at 3.3V, 2.5V and mixed 3.3V input and 2.5V supply modes over the commercial temperature range. Guaranteed output and partto-part skew characteristics make the ICS8343I-01 ideal for those clock distribution applications demanding well defined performance and repeatability. • 16 LVCMOS/LVTTL outputs ICS • 1 LVCMOS/LVTTL clock input • CLK can accept the following input levels: LVCMOS, LVTTL • Maximum output frequency: 200MHz • Dual output enable inputs facilitates 1-to-16 or 1-to-8 input to output modes • All inputs are 5V tolerant • Output skew: 250ps (typical) • Part-to-part skew: 700ps (typical) • Full 3.3V and 2.5V or mixed 3.3V core/2.5V operating supply • -40°C to 85°C ambient operating temperature BLOCK DIAGRAM Q13 Q14 Q15 DD2 OE2 VDD2 V OE1 DD Q0 VDD V Q1 DD1 Q2 VDD1 V PIN ASSIGNMENT 32 31 30 29 28 27 26 25 CLK CLK VDD1 1 24 VDD2 VDD1 2 23 VDD2 VDD1 3 22 VDD2 Q3 4 21 Q12 20 Q11 Q0 Q0 Q15 Q15 Q1 Q1 Q14 Q14 Q2 Q2 Q13 Q13 Q4 5 Q3 Q3 Q12 Q12 GND 6 19 GND Q4 Q4 Q11 Q11 GND 7 18 GND Q5 Q5 Q10 Q10 GND 8 17 GND Q6 Q6 Q9 Q9 Q7 Q7 Q8 Q8 Q10 Q9 Q8 VDD CLK Q7 Q6 GND GND 9 10 11 12 13 14 15 16 Q5 OE1 OE1 ICS8343I-01 32-Lead LQFP 7mm x 7mm x 1.4mm body package Y Package (Top View) OE2 OE2 The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice. 8343AYI-01 www.icst.com/products/hiperclocks.html 1 REV. A JUNE 22, 2004 PRELIMINARY Integrated Circuit Systems, Inc. ICS8343I-01 LOW SKEW, 1-TO-16 LVCMOS / LVTTL FANOUT BUFFER TABLE 1. PIN DESCRIPTIONS Description Number Name 1, 2, 3 VDD1 Power Type 4, 5 6, 7, 8, 17, 18, 19 9, 10, 11 Q3, Q4 Output GND Power Q5, Q6, Q7 Output LVCMOS/LVTTL clock outputs. 7Ω typical output impedance. 12 13 14, 15, 16 CLK VDD Q8, Q9, Q10 Input Power Output Pulldown LVCMOS/LVTTL clock input / 5V tolerant. Core supply pin. LVCMOS/LVTTL clock outputs. 7Ω typical output impedance. 20, 21 Q11, Q12 Output LVCMOS/LVTTL clock outputs. 7Ω typical output impedance. Q0 thru Q7 output supply pins. LVCMOS/LVTTL clock outputs. 7Ω typical output impedance. Power supply ground. Q8 thru Q15 output supply pins. LVCMOS/LVTTL clock outputs. 7Ω typical output impedance. Output enable. When low forces outputs Q8 thru Q15 to HiZ state. 28 OE2 Input Pullup 5V tolerant. LVCMOS/LVTTL interface levels. Output enable. When low forces outputs Q0 thru Q7 to HiZ state. 29 OE1 Input Pullup 5V tolerant. LVCMOS/LVTTL interface levels. 30, 31, 32 Q0, Q1, Q2 Output LVCMOS/LVTTL clock outputs. 7Ω typical output impedance. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin characteristics, for typical values. 22, 23, 24 25, 26, 27 Power Output VDD2 Q13, Q14, Q15 TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions CIN Input Capacitance C PD Power Dissipation Capacitance (per output) Minimum Typical Maximum Units 4 pF VDD, VDD1, VDD2 = 3.465V 11 pF VDD1, VDD2 = 2.63V 9 pF RPULLUP Input Pullup Resistor 51 KΩ RPULLDOWN Input Pulldown Resistor 51 KΩ ROUT Output Impedance VDD, VDD1, VDD2 = 3.3V 5 7 12 Ω TABLE 3. FUNCTION TABLE Inputs Outputs OE1 OE2 Q0:Q7 Q8:Q15 0 0 HiZ HiZ 1 0 Active HiZ 0 1 HiZ Active 1 1 Active Active NOTE: OE1 and OE2 are 5V tolerant. 8343AYI-01 www.icst.com/products/hiperclocks.html 2 REV. A JUNE 22, 2004 PRELIMINARY Integrated Circuit Systems, Inc. ICS8343I-01 LOW SKEW, 1-TO-16 LVCMOS / LVTTL FANOUT BUFFER ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5 V Outputs, VO -0.5V to VDDx + 0.5V Package Thermal Impedance, θJA 47.9°C/W (0 lfpm) Storage Temperature, TSTG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDD1 = VDD2 = 3.3V±5%, TA = -40° TO 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VDD Core Supply Voltage 3.135 3.3 3.465 V VDDx Output Supply Voltage; NOTE 1 3.135 3.3 3.465 V IDD Power Supply Current 35 mA 14 mA Maximum Units V IDDx Output Supply Current; NOTE 2 NOTE 1: VDDx denotes VDD1 and VDD2. NOTE 2: IDDx denotes the sum of IDD1 and IDD2. TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = VDD1 = VDD2 = 3.3V±5%, TA = -40° TO 85°C Symbol Parameter VIH Input High Voltage VIL Input Low Voltage IIH Input High Current Test Conditions Minimum Typical OE1, OE2 2 VDD + 0.3 CLK 2 VDD + 0.3 V OE1, OE2 -0.3 0.8 V CLK -0.3 1.3 V 5 µA 150 µA OE1, OE2 CLK VDD = VIN = 3.465V VDD = VIN = 3.465V OE1, OE2 VDD = 3.465V, VIN = 0V CLK VDD = 3.465V, VIN = 0V IIL Input Low Current VOH Output High Voltage; NOTE 1 -150 µA -5 µA 2.6 V VOL Output Low Voltage; NOTE 1 0.5 V IOZL Output Tristate Current Low 5 µA IOZH Output Tristate Current High 5 µA NOTE 1: Outputs terminated with 50Ω to VDDx/2. See Parameter Measurement Information, 3.3V Output Load Test Circuit. 8343AYI-01 www.icst.com/products/hiperclocks.html 3 REV. A JUNE 22, 2004 PRELIMINARY Integrated Circuit Systems, Inc. ICS8343I-01 LOW SKEW, 1-TO-16 LVCMOS / LVTTL FANOUT BUFFER TABLE 4C. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V±5%, VDD1 = VDD2 = 2.5V±5%, TA = -40° TO 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VDD Core Supply Voltage 3.135 3.3 3.465 V VDDx Output Supply Voltage; NOTE 1 2.375 2.5 2.625 V IDD Power Supply Current 35 mA 14 mA IDDx Output Supply Current; NOTE 2 NOTE 1: VDDx denotes VDD1 and VDD2. NOTE 2: IDDx denotes the sum of IDD1 and IDD2. TABLE 4D. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = 3.3V±5%, VDD1 = VDD2 = 2.5V±5%, TA = -40° TO 85°C Symbol Parameter VIH Input High Voltage VIL Input Low Voltage IIH Input High Current IIL Input Low Current Test Conditions Minimum OE1, OE2 CLK Maximum Units 2 Typical VDD + 0.3 V 2 VDD + 0.3 V OE1, OE2 -0.3 0.8 V CLK -0.3 1.3 V OE1, OE2 VDD = VIN = 3.465V 5 µA CLK VDD = VIN = 3.465V 150 µA OE1, OE2 VDD = 3.465V, VIN = 0V -150 µA CLK VDD = 3.465V, VIN = 0V -5 µA VOH Output High Voltage; NOTE 1 VOL Output Low Voltage; NOTE 1 0.5 V IOZL Output Tristate Current Low 5 µA 5 µA 1.8 Output Tristate Current High IOZH NOTE 1: Outputs terminated with 50Ω to VDDx/2. See Parameter Measurement Information, 3.3V/2.5 Output Load Test Circuit. 8343AYI-01 www.icst.com/products/hiperclocks.html 4 V REV. A JUNE 22, 2004 PRELIMINARY Integrated Circuit Systems, Inc. ICS8343I-01 LOW SKEW, 1-TO-16 LVCMOS / LVTTL FANOUT BUFFER TABLE 4E. POWER SUPPLY DC CHARACTERISTICS, VDD = VDD1 = VDD2 = 2.5V±5%, TA = -40° TO 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VDD Core Supply Voltage 2.375 2.5 2.625 V VDDx Output Supply Voltage; NOTE 1 2.375 2.5 2.625 V IDD Power Supply Current 34 mA 13 mA Maximum Units IDDx Output Supply Current; NOTE 2 NOTE 1: VDDx denotes VDD1 and VDD2. NOTE 2: IDDx denotes the sum of IDD1 and IDD2. TABLE 4F. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = VDD1 = VDD2 = 2.5V±5%, TA = -40° TO 85°C Symbol Parameter VIH Input High Voltage VIL Input Low Voltage IIH Input High Current Test Conditions Minimum Typical OE1, OE2 2 VDD + 0.3 V CLK 2 VDD + 0.3 V -0.3 0.8 V -0.3 1.3 V 5 µA OE1, OE2 CLK OE1, OE2 CLK VDD = VIN = 2.625V VDD = VIN = 2.625V OE1, OE2 VDD = 2.625V, VIN = 0V CLK VDD = 2.625V, VIN = 0V IIL Input Low Current VOH Output High Voltage; NOTE 1 VOL Output Low Voltage; NOTE 1 150 µA -150 µA -5 µA 1.8 V 0.5 V IOZL Output Tristate Current Low 5 µA IOZH Output Tristate Current High 5 µA NOTE 1: Outputs terminated with 50Ω to VDDx/2. See Parameter Measurement Information, 2.5V Output Load Test Circuit. 8343AYI-01 www.icst.com/products/hiperclocks.html 5 REV. A JUNE 22, 2004 PRELIMINARY Integrated Circuit Systems, Inc. ICS8343I-01 LOW SKEW, 1-TO-16 LVCMOS / LVTTL FANOUT BUFFER TABLE 5A. AC CHARACTERISTICS, VDD = VDD1 = VDD2 = 3.3V±5%, TA = -40° TO 85°C Symbol Parameter fMAX tR / tF Onput Frequency Propagation Delay; NOTE 1 Output Skew; NOTE 2, 4 Par t-to-Par t Skew; NOTE 3, 4 Output Rise/Fall Time odc Output Duty Cycle ƒ≤ 133MHz 50 % tPW Output Pulse Width ƒ > 133MHz tPERIOD/2 ns tpLH t sk(o) t sk(pp) Test Conditions Minimum Typical Maximum Units 200 MHz ƒ≤ 200MHz 3 ns Measured on rising edge @VDDx/2 250 ps Measured on rising edge @VDDx/2 700 ps 20% to 80% 0.4 1.5 ns All parameters measured at fMAX unless noted otherwise. NOTE 1: Measured from VDD/2 of the input to VDDx/2 of the output. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDx/2. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDx/2. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. TABLE 5B. AC CHARACTERISTICS, VDD = 3.3V±5%, VDD1 = VDD2 = 2.5V±5%, TA = -40° TO 85°C Symbol fMAX Parameter Onput Frequency Test Conditions Minimum Typical Maximum 200 Units MHz tpLH Propagation Delay; NOTE 1 ƒ≤ 200MHz 3.25 ns t sk(o) Output Skew; NOTE 2, 4 Measured on rising edge @VDDx/2 250 ps t sk(pp) Par t-to-Par t Skew; NOTE 3, 4 Measured on rising edge @VDDx/2 700 ps Output Rise/Fall Time 20% to 80% 0.4 1.0 ns tR / tF odc Output Duty Cycle ƒ≤ 133MHz 50 % All parameters measured at fMAX unless noted otherwise. NOTE 1: Measured from VDD/2 of the input to VDDx/2 of the output. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDx/2. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDx/2. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. TABLE 5C. AC CHARACTERISTICS, VDD = VDD1 = VDD2 = 2.5V±5%, TA = -40° TO 85°C Symbol fMAX Parameter Onput Frequency tpLH Propagation Delay; NOTE 1 Test Conditions ƒ≤ 200MHz Minimum Typical 3 Maximum 133 Units MHz ns t sk(o) Output Skew; NOTE 2, 4 Measured on rising edge @VDDx/2 250 ps t sk(pp) Par t-to-Par t Skew; NOTE 3, 4 Measured on rising edge @VDDx/2 1 ns Output Rise/Fall Time 20% to 80% 0.4 1.0 ns tR / tF odc Output Duty Cycle ƒ≤ 133MHz 50 % All parameters measured at fMAX unless noted otherwise. NOTE 1: Measured from VDD/2 of the input to VDDx/2 of the output. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDx/2. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDx/2. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. 8343AYI-01 www.icst.com/products/hiperclocks.html 6 REV. A JUNE 22, 2004 PRELIMINARY Integrated Circuit Systems, Inc. ICS8343I-01 LOW SKEW, 1-TO-16 LVCMOS / LVTTL FANOUT BUFFER PARAMETER MEASUREMENT INFORMATION 2.05V±5% 1.25V±5% 1.65V±5% SCOPE VDD, V DDx SCOPE VDD V DDx Qx LVCMOS Qx LVCMOS GND GND -1.65V±5% -1.25V±5% 3.3V CORE/ 3.3V OUTPUT LOAD AC TEST CIRCUIT 3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT 1.25V±5% V SCOPE VDD, V DDx DDx Qx 2 Qx LVCMOS V DDx Qy GND 2 t sk(o) -1.25V±5% 2.5V CORE/ 2.5V OUTPUT LOAD AC TEST CIRCUIT Part 1 Qx Part 2 Qy OUTPUT SKEW V 80% DDx Clock Outputs V DDx 20% 20% tR tF 2 t sk(pp) OUTPUT RISE/FALL TIME PART-TO-PART SKEW 8343AYI-01 80% 2 www.icst.com/products/hiperclocks.html 7 REV. A JUNE 22, 2004 PRELIMINARY Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-16 LVCMOS / LVTTL FANOUT BUFFER V DDx VDDx 2 CLK ICS8343I-01 2 Q0:Q15 Pulse Width t VDDx 2 Q0:Q15 t PD odc = PERIOD t PW t PERIOD OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD PROPAGATION DELAY 8343AYI-01 www.icst.com/products/hiperclocks.html 8 REV. A JUNE 22, 2004 PRELIMINARY Integrated Circuit Systems, Inc. ICS8343I-01 LOW SKEW, 1-TO-16 LVCMOS / LVTTL FANOUT BUFFER RELIABILITY INFORMATION TABLE 6. θJAVS. AIR FLOW TABLE FOR 32 LEAD LQFP θJA by Velocity (Linear Feet per Minute) 0 Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 67.8°C/W 47.9°C/W 200 500 55.9°C/W 42.1°C/W 50.1°C/W 39.4°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS8343I-01 is: 985 8343AYI-01 www.icst.com/products/hiperclocks.html 9 REV. A JUNE 22, 2004 PRELIMINARY Integrated Circuit Systems, Inc. PACKAGE OUTLINE - Y SUFFIX ICS8343I-01 LOW SKEW, 1-TO-16 LVCMOS / LVTTL FANOUT BUFFER FOR 32 LEAD LQFP TABLE 7. PACKAGE DIMENSIONS JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS BBA SYMBOL MINIMUM NOMINAL MAXIMUM 32 N A -- -- 1.60 A1 0.05 -- 0.15 A2 1.35 1.40 1.45 b 0.30 0.37 0.45 c 0.09 -- 0.20 D 9.00 BASIC D1 7.00 BASIC D2 5.60 Ref. E 9.00 BASIC E1 7.00 BASIC E2 5.60 Ref. 0.80 BASIC e L 0.45 0.60 0.75 θ 0° -- 7° ccc -- -- 0.10 Reference Document: JEDEC Publication 95, MS-026 8343AYI-01 www.icst.com/products/hiperclocks.html 10 REV. A JUNE 22, 2004 PRELIMINARY Integrated Circuit Systems, Inc. ICS8343I-01 LOW SKEW, 1-TO-16 LVCMOS / LVTTL FANOUT BUFFER TABLE 8. ORDERING INFORMATION Part/Order Number ICS8343AYI-01 ICS8343AYI-01T Marking ICS8343AYI-01 ICS8343AYI-01 Package 32 Lead LQFP 32 Lead LQFP on Tape and Reel Count 250 per tray 1000 Temperature -40°C to 85°C -40°C to 85°C The aforementioned trademark, HiPerClockS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 8343AYI-01 www.icst.com/products/hiperclocks.html 11 REV. A JUNE 22, 2004