ICS83905I Integrated Circuit Systems, Inc. LOW SKEW, 1:6 CRYSTAL INTERFACE-TOLVCMOS / LVTTL FANOUT BUFFER GENERAL DESCRIPTION FEATURES The ICS83905I is a low skew, 1-to-6 LVCMOS / LVTTL Fanout Buffer and a member of the HiPerClockS™ HiPerClockS™ family of High Performance Clock Solutions from ICS. The low impedance LVCMOS/LVTTL outputs are designed to drive 50W series or parallel terminated transmission lines. The effective fanout can be increased from 6 to 12 by utilizing the ability of the outputs to drive two series terminated lines. • 6 LVCMOS / LVTTL outputs ICS • Outputs able to drive 12 series terminated lines • Crystal oscillator interface • Crystal input frequency range: 10MHz to 40MHz • Output skew: 80ps (maximum) • RMS phase jitter @ 25MHz, (100Hz - 1MHz): 0.26ps (typical) (VDD = VDDO = 2.5V) The ICS83905I is characterized at full 3.3V, 2.5V, and 1.8V, mixed 3.3V/2.5V, 3.3V/1.8V and 2.5V/1.8V output operating supply mode. Guaranteed output and part-to-part skew characteristics along with the 1.8V output capabilities makes the ICS83905I ideal for high performance, single ended applications that also require a limited output voltage. Phase noise: Offset Noise Power 100Hz .............. -129.7 dBc/Hz 1kHz .............. -144.4 dBc/Hz 10kHz .............. -147.3 dBc/Hz 100kHz .............. -157.3 dBc/Hz • 5V tolerant enable inputs • Synchronous output enables • Operating power supply modes: Full 3.3V, 2.5V and 1.8V, mixed 3.3V core/2.5V output operating supply, mixed 3.3V core/1.8V output operating supply, mixed 2.5V core/1.8V output operating supply • -40°C to 85°C ambient operating temperature • Lead-Free package fully RoHS compliant BLOCK DIAGRAM PIN ASSIGNMENT BCLK0 BCLK1 XTAL_IN BCLK2 XTAL_OUT XTAL_OUT ENABLE 2 GND BCLK0 VDD o BCLK1 GND BCLK2 1 2 3 4 5 6 7 8 XTAL_IN ENABLE 1 BCLK5 VDDO BCLK4 GND BCLK3 VDD 16 15 14 13 12 11 10 9 ICS83905I BCLK3 16-Lead TSSOP 4.4mm x 5.0mm x 0.92mm body package G Pacakge Top View BCLK4 ENABLE 1 SYNCHRONIZE BCLK5 ENABLE 2 83905AGI SYNCHRONIZE http://www.icst.com/products/hiperclocks.html 1 REV. B MAY 16, 2005 ICS83905I Integrated Circuit Systems, Inc. LOW SKEW, 1:6 CRYSTAL INTERFACE-TOLVCMOS / LVTTL FANOUT BUFFER TABLE 1. PIN DESCRIPTIONS Number Name 1 XTAL_OUT Type Description Output Crystal oscillator interface. XTAL_OUT is the output. 2, 15 ENABLE 2, ENABLE 1 Input Clock enable. LVCMOS / LVTTL interface levels. See Table 3. 3, 7 , 1 1 4, 6, 8, 10, 12, 14 5, 13 GND BCLK0, BCLK1, BCLK2, BCLK3, BCLK4, BCLK5 VDDO Power Power supply ground. Output Clock outputs. LVCMOS / LVTTL interface levels. Power Output supply pin. 9 VDD Power Core supply pin. 16 XTAL_IN Input Crystal oscillator interface. XTAL_IN is the input. TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN Input Capacitance Test Conditions CPD Power Dissipation Capacitance (per output) TABLE 3. OUTPUT ENABLE AND VDDO = 3.465V ENABLE 2 Maximum Units pF 19 pF VDDO = 2.625V 18 pF VDDO = 2V 16 pF VDDO = 3.3V ± 5% 7 Ω VDDO = 2.5V ± 5% 7 Ω VDDO = 1.8V ± 0.2V 10 Ω CLOCK ENABLE FUNCTION TABLE Control Inputs ENABLE 1 Typical 4 Output Impedance ROUT Minimum Outputs BCLK0:BCLK4 BCLK5 0 0 LOW LOW 0 1 LOW Toggling 1 0 Toggling LOW 1 1 Toggling Toggling BCLK5 BCLK0:4 ENABLE2 ENABLE1 FIGURE 1. ENABLE TIMING DIAGRAM 83905AGI http://www.icst.com/products/hiperclocks.html 2 REV. B MAY 16, 2005 ICS83905I Integrated Circuit Systems, Inc. LOW SKEW, 1:6 CRYSTAL INTERFACE-TOLVCMOS / LVTTL FANOUT BUFFER ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD 4.6V NOTE: Stresses beyond those listed under Absolute Inputs, VI -0.5V to VDD + 0.5 V Maximum Ratings may cause permanent damage to the Outputs, VO -0.5V to VDDO + 0.5V device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions be- Package Thermal Impedance, θJA 16 Lead TSSOP package 89°C/W (0 lfpm) Storage Temperature, TSTG -65°C to 150°C yond those listed in the DC Characteristics or AC Character- istics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter VDD Core Supply Voltage Test Conditions Minimum Typical Maximum Units 3.135 3.3 3.465 V 3.135 3.3 VDDO Output Supply Voltage 3.465 V IDD Power Supply Current ENABLE 1:2 = 00 10 mA IDDO Output Supply Current ENABLE 1:2 = 00 5 mA TABLE 4B. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 2.5V±5%, TA = -40°C TO 85°C Symbol Parameter VDD Core Supply Voltage Test Conditions Minimum Typical Maximum Units 2.375 2. 5 2.625 V 2.375 2.5 VDDO Output Supply Voltage 2.625 V IDD Power Supply Current ENABLE 1:2 = 00 8 mA IDDO Output Supply Current ENABLE 1:2 = 00 4 mA TABLE 4C. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 1.8V±0.2V, TA = -40°C TO 85°C Symbol Parameter VDD Core Supply Voltage Test Conditions Minimum Typical Maximum Units 1.6 1.8 2.0 V 1.6 1.8 VDDO Output Supply Voltage 2.0 V IDD Power Supply Current ENABLE 1:2 = 00 5 mA IDDO Output Supply Current ENABLE 1:2 = 00 3 mA TABLE 4D. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 2.5V±5%, TA = -40°C TO 85°C Symbol Parameter VDD Core Supply Voltage Test Conditions Minimum Typical Maximum Units 3.135 3.3 3.465 V 2.375 2.5 VDDO Output Supply Voltage 2.625 V IDD Power Supply Current ENABLE 1:2 = 00 10 mA IDDO Output Supply Current ENABLE 1:2 = 00 4 mA 83905AGI http://www.icst.com/products/hiperclocks.html 3 REV. B MAY 16, 2005 ICS83905I Integrated Circuit Systems, Inc. LOW SKEW, 1:6 CRYSTAL INTERFACE-TOLVCMOS / LVTTL FANOUT BUFFER TABLE 4E. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 1.8V±0.2V, TA = -40°C TO 85°C Symbol Parameter VDD Core Supply Voltage Test Conditions Minimum Typical Maximum Units 3.135 3.3 3.465 V 1.6 1.8 VDDO Output Supply Voltage 2.0 V IDD Power Supply Current ENABLE 1:2 = 00 10 mA IDDO Output Supply Current ENABLE 1:2 = 00 3 mA TABLE 4F. POWER SUPPLY DC CHARACTERISTICS, VDD = 2.5V±5%, VDDO = 1.8V±0.2V, TA = -40°C TO 85°C Symbol Parameter VDD Core Supply Voltage Test Conditions Minimum Typical Maximum Units 2.375 2.5 2.625 V 1.6 1.8 VDDO Output Supply Voltage 2.0 V IDD Power Supply Current ENABLE 1:2 = 00 8 mA IDDO Output Supply Current ENABLE 1:2 = 00 3 mA Maximum Units VDD + 0.3 V TABLE 4G. LVCMOS/LVTTL DC CHARACTERISTICS, TA = -40°C TO 85°C Symbol VIH VIL Parameter Input High Voltage Input Low Voltage VOH ENABLE 1, ENABLE 2 ENABLE 1, ENABLE 2 Output High Voltage Test Conditions Minimum VDD = 3.3V ± 5% 2 Typical VDD = 2.5V ± 5% 1.7 VDD + 0.3 V VDD = 1.8V ± 0.2V 0.65*VDD VDD + 0.3 V VDD = 3.3V ± 5% -0.3 0. 8 V VDD = 2.5V ± 5% -0.3 0. 7 V VDD = 1.8V ± 0.2V -0.3 0.35*VDD V VDDO = 3.3V ± 5%; NOTE 1 2.6 V VDDO = 2.5V ± 5%; IOH = -1mA 2 V VDDO = 2.5V ± 5%; NOTE 1 1.8 V VDDO = 1.8V ± 0.2V; NOTE 1 VDDO - 0.3 V VDDO = 3.3V ± 5%; NOTE 1 VOL Output Low Voltage 0.5 V VDDO = 2.5V ± 5%; IOL = 1mA 0.4 V VDDO = 2.5V ± 5%; NOTE 1 0.45 V VDDO = 1.8V ± 0.2V; NOTE 1 0.35 V NOTE 1: Outputs terminated with 50Ω to VDDO/2. See Parameter Measurement section, "Load Test Circuit" diagrams. TABLE 5. CRYSTAL CHARACTERISTICS Parameter Test Conditions Minimum Mode of Oscillation Typical Maximum Units Fundamental 40 MHz Equivalent Series Resistance (ESR) Frequency 50 Ω Shunt Capacitance 7 pF Drive Level 1 mW 83905AGI 10 http://www.icst.com/products/hiperclocks.html 4 REV. B MAY 16, 2005 ICS83905I Integrated Circuit Systems, Inc. LOW SKEW, 1:6 CRYSTAL INTERFACE-TOLVCMOS / LVTTL FANOUT BUFFER TABLE 6A. AC CHARACTERISTICS, VDD = VDDO = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units Using External Crystal 10 40 MH z Using External Clock Source; NOTE 1 DC 100 MH z 48 52 % 80 ps fMAX Output Frequency odc Output Duty Cycle tsk(o) Output Skew; NOTE 2, 4 tjit(Ø) RMS Phase Jitter (Random) tR/tF Output Rise/Fall Time tEN Output Enable Time; NOTE 3 tDIS 25MHz @ (Integration Range: 100Hz-1MHz) 20% to 80% 0.13 200 ps 800 ps ENABLE 1 4 cycles ENABLE 2 4 cycles Output Disable Time; ENABLE 1 NOTE 3 ENABLE 2 4 cycles 4 cycles All parameters measured at ƒ ≤ fMAX using a crystal input unless noted otherwise. Terminated at 50Ω to VDDO/2. NOTE 1: XTAL_IN can be overdriven relative to a signal a crystal would provide. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: These parameters are guaranteed by characterization. Not tested in production. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. TABLE 6B. AC CHARACTERISTICS, VDD = VDDO = 2.5V±5%, TA = -40°C TO 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units Using External Crystal 10 40 MH z Using External Clock Source; NOTE 1 DC 100 MH z 47 53 % 80 ps fMAX Output Frequency odc Output Duty Cycle tsk(o) Output Skew; NOTE 2, 5 tjit(Ø) RMS Phase Jitter (Random); NOTE 3 tR/tF Output Rise/Fall Time 25MHz @ (Integration Range: 100Hz-1MHz) 20% to 80% 0.26 200 ps 800 ps ENABLE 1 4 cycles tEN Output Enable Time; NOTE 4 ENABLE 2 4 cycles tDIS Output Disable Time; ENABLE 1 NOTE 4 ENABLE 2 4 cycles 4 cycles All parameters measured at ƒ ≤ fMAX using a crystal input unless noted otherwise. Terminated at 50Ω to VDDO/2. NOTE 1: XTAL_IN can be overdriven relative to a signal a crystal would provide. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: Please refer to phase noise plot. NOTE 4: These parameters are guaranteed by characterization. Not tested in production. NOTE 5: This parameter is defined in accordance with JEDEC Standard 65. 83905AGI http://www.icst.com/products/hiperclocks.html 5 REV. B MAY 16, 2005 ICS83905I Integrated Circuit Systems, Inc. LOW SKEW, 1:6 CRYSTAL INTERFACE-TOLVCMOS / LVTTL FANOUT BUFFER TABLE 6C. AC CHARACTERISTICS, VDD = VDDO = 1.8V±0.2V, TA = -40°C TO 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units Using External Crystal 10 40 MH z Using External Clock Source; NOTE 1 DC 100 MH z 47 53 % 80 ps fMAX Output Frequency odc Output Duty Cycle tsk(o) Output Skew; NOTE 2, 4 tjit(Ø) RMS Phase Jitter (Random) tR/tF Output Rise/Fall Time tEN Output Enable Time; NOTE 3 tDIS 25MHz @ (Integration Range: 100Hz-1MHz) 0.27 20% to 80% 200 ps 900 ps ENABLE 1 4 cycles ENABLE 2 4 cycles Output Disable Time; ENABLE 1 NOTE 3 ENABLE 2 4 cycles 4 cycles All parameters measured at ƒ ≤ fMAX using a crystal input unless noted otherwise. Terminated at 50Ω to VDDO/2. NOTE 1: XTAL_IN can be overdriven relative to a signal a crystal would provide. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: These parameters are guaranteed by characterization. Not tested in production. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. TABLE 6D. AC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 2.5V±5%, TA = -40°C TO 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units Using External Crystal 10 40 MH z Using External Clock Source; NOTE 1 DC 100 MH z 48 52 % 80 ps fMAX Output Frequency odc Output Duty Cycle tsk(o) Output Skew; NOTE 2, 4 tjit(Ø) RMS Phase Jitter (Random) tR/tF Output Rise/Fall Time tEN Output Enable Time; NOTE 3 tDIS 25MHz @ (Integration Range: 100Hz-1MHz) 20% to 80% 0.14 200 ps 800 ps ENABLE 1 4 cycles ENABLE 2 4 cycles Output Disable Time; ENABLE 1 NOTE 3 ENABLE 2 4 cycles 4 cycles All parameters measured at ƒ ≤ fMAX using a crystal input unless noted otherwise. Terminated at 50Ω to VDDO/2. NOTE 1: XTAL_IN can be overdriven relative to a signal a crystal would provide. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: These parameters are guaranteed by characterization. Not tested in production. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. 83905AGI http://www.icst.com/products/hiperclocks.html 6 REV. B MAY 16, 2005 ICS83905I Integrated Circuit Systems, Inc. LOW SKEW, 1:6 CRYSTAL INTERFACE-TOLVCMOS / LVTTL FANOUT BUFFER TABLE 6E. AC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 1.8V±0.2V, TA = -40°C TO 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units Using External Crystal 10 40 MHz Using External Clock Source; NOTE 1 DC 100 MHz 48 52 % 80 ps fMAX Output Frequency odc Output Duty Cycle tsk(o) Output Skew; NOTE 2, 4 tjit(Ø) RMS Phase Jitter (Random) tR/tF Output Rise/Fall Time tEN Output Enable Time; NOTE 3 tDIS Output Disable Time; ENABLE 1 NOTE 3 ENABLE 2 25MHz @ (Integration Range: 100Hz-1MHz) 0.18 20% to 80% 200 ps 900 ps ENABLE 1 4 cycles ENABLE 2 4 cycles 4 cycles 4 cycles All parameters measured at ƒ ≤ fMAX using a crystal input unless noted otherwise. Terminated at 50Ω to VDDO/2. NOTE 1: XTAL_IN can be overdriven relative to a signal a crystal would provide. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: These parameters are guaranteed by characterization. Not tested in production. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. TABLE 6F. AC CHARACTERISTICS, VDD = 2.5V±5%, VDDO = 1.8V±0.2V, TA = -40°C TO 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units Using External Crystal 10 40 MH z Using External Clock Source; NOTE 1 DC 100 MH z 47 53 % 80 ps fMAX Output Frequency odc Output Duty Cycle tsk(o) Output Skew; NOTE 2, 4 tjit(Ø) RMS Phase Jitter (Random) tR/tF Output Rise/Fall Time 25MHz @ (Integration Range: 100Hz-1MHz) 20% to 80% 0.19 200 ps 900 ps ENABLE 1 4 cycles tEN Output Enable Time; NOTE 3 ENABLE 2 4 cycles tDIS Output Disable Time; ENABLE 1 NOTE 3 ENABLE 2 4 cycles 4 cycles All parameters measured at ƒ ≤ fMAX using a crystal input unless noted otherwise. Terminated at 50Ω to VDDO/2. NOTE 1: XTAL_IN can be overdriven relative to a signal a crystal would provide. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: These parameters are guaranteed by characterization. Not tested in production. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. 83905AGI http://www.icst.com/products/hiperclocks.html 7 REV. B MAY 16, 2005 ICS83905I Integrated Circuit Systems, Inc. LOW SKEW, 1:6 CRYSTAL INTERFACE-TOLVCMOS / LVTTL FANOUT BUFFER TYPICAL PHASE NOISE AT 25MHZ (2.5V CORE/ 2.5V OUTPUT) 0 -10 25MHz -20 RMS Phase Jitter (Random) 100Hz to 1MHz = 0.26ps (typical) -30 -40 NOISE POWER dBc Hz -50 -60 -70 -80 -90 -100 Raw Phase Noise Data -110 ➤ -120 -130 -140 -150 -160 -170 -180 -190 10 100 1k 10k 100k 1M OFFSET FREQUENCY (HZ) TYPICAL PHASE NOISE AT 25MHZ (3.3V CORE/ 3.3V OUTPUT) 0 -10 25MHz -20 RMS Phase Jitter (Random) 100Hz to 1MHz = 0.13ps (typical) -30 -40 NOISE POWER dBc Hz -50 -60 -70 -80 -90 -100 Raw Phase Noise Data -110 ➤ -120 -130 -140 -150 -160 -170 -180 -190 10 100 1k 10k 100k 1M OFFSET FREQUENCY (HZ) 83905AGI http://www.icst.com/products/hiperclocks.html 8 REV. B MAY 16, 2005 ICS83905I Integrated Circuit Systems, Inc. LOW SKEW, 1:6 CRYSTAL INTERFACE-TOLVCMOS / LVTTL FANOUT BUFFER PARAMETER MEASUREMENT INFORMATION 1.25V±5% 1.65V±5% SCOPE VDD, VDDO Qx LVCMOS LVCMOS GND Qx GND -1.165V±5% 3.3V SCOPE VDD, VDDO CORE/3.3V -1.25V±5% OUTPUT LOAD AC TEST CIRCUIT 2.5V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT 2.05V±5% 0.9V±0.1V SCOPE VDD , VDDO 1.25V±5% SCOPE V DD VDDO LVCMOS Qx LVCMOS Qx GND GND -0.9V ± 0.1V -1.25V±5% 1.8V CORE/1.8V OUTPUT LOAD AC TEST CIRCUIT 2.4±0.9V 3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT 1.6V±0.025% 0.9V±0.1V 0.9V±0.1V SCOPE VDD VDDO LVCMOS VDDO Qx LVCMOS Qx GND GND -0.9V±0.1V -0.9V±0.1V 3.3V CORE/1.8V OUTPUT LOAD AC TEST CIRCUIT 83905AGI SCOPE V DD 2.5 CORE/1.8V OUTPUT LOAD AC TEST CIRCUIT http://www.icst.com/products/hiperclocks.html 9 REV. B MAY 16, 2005 ICS83905I Integrated Circuit Systems, Inc. LOW SKEW, 1:6 CRYSTAL INTERFACE-TOLVCMOS / LVTTL FANOUT BUFFER V DD V DDO Qx 2 BCLKx 2 t PW t V PERIOD DDO Qy 2 tsk(o) odc = t PW x 100% t PERIOD OUTPUT SKEW Clock Outputs OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD 80% 80% tR tF 20% 20% OUTPUT RISE/FALL TIME 83905AGI http://www.icst.com/products/hiperclocks.html 10 REV. B MAY 16, 2005 ICS83905I Integrated Circuit Systems, Inc. LOW SKEW, 1:6 CRYSTAL INTERFACE-TOLVCMOS / LVTTL FANOUT BUFFER APPLICATION INFORMATION CRYSTAL INPUT INTERFACE outs. Slightly increasing the C1 and C2 values will slightly reduce the frequency. Slightly decreasing the C1 and C2 values will slightly increase the frequency. For the oscillator circuit below, R1 can be used, but is not required. For new designs, it is recommended that R1 not be used. Figure 1A shows an example of ICS83905I crystal interface with a parallel resonant crystal. The frequency accuracy can be fine tuned by adjusting the C1 and C2 values. For a parallel crystal with loading capacitance CL = 18pF, we suggest C1 = 15pF and C2 = 15pF to start with. These values may be slightly fine tuned further to optimize the frequency accuracy for different board lay- XTAL_IN C1 15p X1 18pF Parallel Cry stal 0 XTAL_OUT C2 15p R1 (optional) FIGURE 1. CRYSTAL OSCILLATOR INTERFACE 83905AGI http://www.icst.com/products/hiperclocks.html 11 REV. B MAY 16, 2005 ICS83905I Integrated Circuit Systems, Inc. LOW SKEW, 1:6 CRYSTAL INTERFACE-TOLVCMOS / LVTTL FANOUT BUFFER LAYOUT GUIDELINE Figure 2 shows an example of ICS83905I application schematic. In this example, the device is operated at VDD = 3.3V and VDDO = 3.3V. The decoupling capacitors should be located as close as possible to the power pins. The input is driven by an 18pF load resonant quartz crystal. The tuning capacitors (C1, C2) are fairly accurate, but minor adjustments might be required. For the LVCMOS output drivers, two termination examples are shown in the schematic. For additional termination, examples are shown in the LVCMOS Termination Application Note. VDDO = 3.3V VDD = 3.3V R2 31 Zo = 50 Ohm CL = 18 pf C2 15pf C1 15pF LVCMOS U1 ENABLE 2 VDDO 1 2 3 4 5 6 7 8 XTAL_OUT ENABLE 2 GND BCLK0 VDDO BCLK1 GND BCLK2 XTAL_IN ENABLE 1 BCLK5 VDDO BCLK4 GND BCLK3 VDD 16 15 14 13 12 11 10 9 ENABLE 1 VDD R3 100 Zo = 50 Ohm R4 100 ICS83905I LVCMOS VDD C3 10uF VDDO C4 .1uF C5 .1uF Optional Termination C6 .1uF Unused outputs can be left floating. There should be no trace attached to unused outputs. Device characterized and specification limits set with all outputs terminated. FIGURE 2. Schematic of Recommended Layout 83905AGI http://www.icst.com/products/hiperclocks.html 12 REV. B MAY 16, 2005 ICS83905I Integrated Circuit Systems, Inc. LOW SKEW, 1:6 CRYSTAL INTERFACE-TOLVCMOS / LVTTL FANOUT BUFFER RELIABILITY INFORMATION TABLE 7. θJAVS. AIR FLOW TABLE FOR 16 LEAD TSSOP θ JA by Velocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 137.1°C/W 89.0°C/W 118.2°C/W 81.8°C/W 106.8°C/W 78.1°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS83905I is: 339 Pin compatible to MPC905 83905AGI http://www.icst.com/products/hiperclocks.html 13 REV. B MAY 16, 2005 ICS83905I Integrated Circuit Systems, Inc. PACKAGE OUTLINE - G SUFFIX FOR LOW SKEW, 1:6 CRYSTAL INTERFACE-TOLVCMOS / LVTTL FANOUT BUFFER 16 LEAD TSSOP TABLE 8. PACKAGE DIMENSIONS SYMBOL TSSOP Minimum N A FOR Millimeters Maximum 16 -- 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 4.90 5.10 E E1 6.40 BASIC 4.30 e 4.50 0.65 BASIC L 0.45 0.75 α 0° 8° aaa -- 0.10 Reference Document: JEDEC Publication 95, MO-153 83905AGI http://www.icst.com/products/hiperclocks.html 14 REV. B MAY 16, 2005 ICS83905I Integrated Circuit Systems, Inc. LOW SKEW, 1:6 CRYSTAL INTERFACE-TOLVCMOS / LVTTL FANOUT BUFFER TABLE 9. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature ICS83905AGI TBD 16 Lead TSSOP tube -40°C to 85°C ICS83905AGIT TBD 16 Lead TSSOP 2500 tape & reel -40°C to 85°C ICS83905AGILF 83905AIL 16 Lead "Lead-Free" TSSOP tube -40°C to 85°C ICS83905AGILFT 83905AIL 16 Lead "Lead-Free" TSSOP 2500 tape & reel -40°C to 85°C NOTE: Parts that are ordered with an “LF” suffix to the part number are the Pb-Free configuration and are RoHS compliant. The aforementioned trademark, HiPerClockS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 83905AGI http://www.icst.com/products/hiperclocks.html 15 REV. B MAY 16, 2005 ICS83905I Integrated Circuit Systems, Inc. LOW SKEW, 1:6 CRYSTAL INTERFACE-TOLVCMOS / LVTTL FANOUT BUFFER REVISION HISTORY SHEET Rev Table Page 6A - 6F 2 1 5-7 A B B 83905AGI 8 11 12 Description of Change Added Enable Timing Diagram. Features Section - added RMS Phase Jitter bullet. AC Characteristics Tables - added RMS Phase Jitter spec. Corrected ambient operating temperature. Added Phase Noise Plot. Added Crystal Input Interface in Application Section. Added schematic layout. http://www.icst.com/products/hiperclocks.html 16 Date 3/28/05 4/8/05 5/16/05 REV. B MAY 16, 2005