PRELIMINARY Integrated Circuit Systems, Inc. ICS84025 CRYSTAL-TO-LVCMOS / LVTTL FREQUENCY SYNTHESIZER WITH FANOUT BUFFER GENERAL DESCRIPTION FEATURES The ICS84025 is a Crystal-to-LVCMOS/LVTTL Frequency Synthesizer with Fanout Buffer and HiPerClockS™ a member of the HiPerClockS™ family of High Performance Clock Solutions from ICS. The VCO frequency is programmed in steps equal to the value of the crystal frequency. The VCO and output frequency can be programmed using the feedback and output frequency select pins. The low phase noise characteristics of the ICS84025 make it an ideal clock source for Fibre Channel 1 and Gigabit Ethernet applications. • 6 LVCMOS/LVTTL outputs ,&6 • Crystal oscillator interface • Output frequency range: 53.125MHz to 125MHz • Crystal input frequency: 25MHz and 25.5MHz • RMS phase jitter at 106.25, using a 25.5MHz crystal (637KHz to 10MHz): 3.25ps • Phase noise: Offset Noise Power 100Hz ................. -100 dBc/Hz 1KHz ................. -115 dBc/Hz 10KHz ................. -125 dBc/Hz 100KHz ................. -127 dBc/Hz FUNCTION TABLE Inputs XTAL Output Frequency MR F_SEL1 F_SEL0 F_OUT 1 X X LOW 0 0 0 25.5MHz 53.125MHz • 0°C to 70°C ambient operating temperature 0 0 1 25.5MHz 106.25MHz • Industrial temperature information available upon request 0 1 0 25MHz 62.5MHz 0 1 1 25MHz 125MHz • 3.3V core, outputs may either be 3.3V, 2.5V or 1.8V BLOCK DIAGRAM PIN ASSIGNMENT VDDO Q0 GND Q1 VDDO Q2 GND Q3 VDDO Q4 GND Q5 XTAL1 0 OSC Output Divider XTAL2 1 6 / Q0:Q5 PLL Feedback Divider 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 F_SEL0 F_SEL1 MR XTAL1 XTAL2 GND VDDA VDD PLL_SEL GND nc VDDO ICS84025 24-Lead, 300-MIL SOIC 7.5mm x 15.33mm x 2.3mm body package M Package Top View F_SEL1 PLL_SEL MR F_SEL0 The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice. 84025EM www.icst.com/products/hiperclocks.html 1 REV. A APRIL 16, 2003 PRELIMINARY Integrated Circuit Systems, Inc. ICS84025 CRYSTAL-TO-LVCMOS / LVTTL FREQUENCY SYNTHESIZER WITH FANOUT BUFFER TABLE 1. PIN DESCRIPTIONS Number Name 1, 5, 9, 13 VDDO Power Type Description Output supply pins. 2 Q0 Output Clock output. LVCMOS/LVTTL interface levels. 3, 7, 11, 15, 19 GND Power Power supply ground. 4 Q1 Output Clock output. LVCMOS/LVTTL interface levels. 6 Q2 Output Clock output. LVCMOS/LVTTL interface levels. 8 Q3 Output Clock output. LVCMOS/LVTTL interface levels. 10 Q4 Output Clock output. LVCMOS/LVTTL interface levels. 12 Q5 Output Clock output. LVCMOS/LVTTL interface levels. 14 nc Unused 16 PLL_SEL Input 17 VDD Power No connect. Selects between the PLL and cr ystal inputs as the input to the dividers. When HIGH, selects PLL. When LOW, selects XTAL1, XTAL2. LVCMOS / LVTTL interface levels. Core supply pin. 18 VDDA Power Analog supply pin. 20, 21 XTAL2, XTAL1 Input 22 MR Input 23 F_SEL1 Input 24 F_SEL0 Input Pullup Cr ystal oscillator interface. XTAL1 is the input. XTAL2 is the output. Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the outputs to go low. When logic LOW, the Pulldown internal dividers and the outputs are enabled. LVCMOS / LVTTL interface levels. Pulldown Feedback frequency select pin. LVCMOS/LVTTL interface levels. Pullup Output frequency select pin. LVCMOS / LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN Input Capacitance RPULLUP Input Pullup Resistor RPULLDOWN Input Pulldown Resistor CPD 84025EM Test Conditions Power Dissipation Capacitance (per output) Minimum Typical Maximum Units 4 pF 51 KΩ 51 KΩ VDD, VDDO = 3.465V TBD pF VDD = 3.465V, VDDO = 2.625V TBD pF VDD = 3.465V, VDDO = 1.95V TBD pF www.icst.com/products/hiperclocks.html 2 REV. A APRIL 16, 2003 PRELIMINARY Integrated Circuit Systems, Inc. ICS84025 CRYSTAL-TO-LVCMOS / LVTTL FREQUENCY SYNTHESIZER WITH FANOUT BUFFER ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5 V Outputs, VO -0.5V to VDDO + 0.5V Package Thermal Impedance, θJA 46.2°C/W (0 lfpm) Storage Temperature, TSTG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 3.3V ± 5%, TA = 0°C TO 70°C Symbol Parameter Minimum Typical Maximum Units VDD Core Supply Voltage Test Conditions 3.135 3.3 3.465 V VDDA Analog Supply Voltage 3.135 3.3 3.465 V 3.135 3.3 3.465 V 2.375 2.5 2.625 V 1.65 1.8 1.95 V Output Supply Voltage VDDO Power Supply Current IDD 71 mA IDDA Analog Supply Current 15 mA IDDO Output Supply Current 70 mA TABLE 3B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = VDDA = 3.3V ± 5%, TA = 0°C TO 70°C Symbol Parameter VIH Input High Voltage VIL Input Low Voltage IIH Input High Current IIL Input Low Current VOH Test Conditions PLL_SEL, MR, F_SEL0, F_SEL1 PLL_SEL, MR, F_SEL0, F_SEL1 MR, F_SEL1 PLL_SEL, F_SEL0 Minimum Typical Maximum Units 2 VDD + 0.3 V -0.3 0.8 V 150 µA 5 µA VDD = VIN = 3.465V VDD = VIN = 3.465V MR, F_SEL1 VDD = 3.465V, VIN = 0V -5 µA PLL_SEL, F_SEL0 VDD = 3.465V, VIN = 0V -150 µA VDDO = 3.3V ± 5% 2.6 V VDDO = 2.5V ± 5% 1.8 V VDDO = 1.8V ± 0.15V VDDO- 0.45 Output High Voltage; NOTE 1 V VDDO = 3.3V ± 5% VOL Output Low Voltage; NOTE 1 0.5 VDDO = 2.5V ± 5% VDDO = 1.8V ± 0.15V NOTE 1: Outputs terminated with 50Ω to VDDO/2. See Parameter Measurement Information Section, "Output Load Test Circuit" diagrams. V 0.5 V 0.45 V TABLE 4. CRYSTAL CHARACTERISTICS Parameter Test Conditions Minimum Mode of Oscillation Typical Maximum Units Fundamental Frequency 25 25.5 MHz Equivalent Series Resistance (ESR) 70 Ω Shunt Capacitance 7 pF 84025EM www.icst.com/products/hiperclocks.html 3 REV. A APRIL 16, 2003 PRELIMINARY Integrated Circuit Systems, Inc. ICS84025 CRYSTAL-TO-LVCMOS / LVTTL FREQUENCY SYNTHESIZER WITH FANOUT BUFFER TABLE 5A. AC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V ± 5%, TA = 0°C TO 70°C Symbol Parameter FOUT Output Frequency tjit(cc) Cycle-to-Cycle Jitter; NOTE 2 tsk(o) Output Skew; NOTE 1, 2 tR / tF Output Rise/Fall Time odc Output Duty Cycle tPW Output Pulse Width Test Conditions Minimum Typical 53.125 20% to 80% Maximum Units 125 MHz 50 ps TBD ps 300 700 ps tPERIOD/2 + TBD ps 50 tPERIOD/2 - TBD % PLL Lock Time 1 ms tLOCK See Parameter Measurement Information section. NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. TABLE 5B. AC CHARACTERISTICS, VDD = VDDA = 3.3V ± 5%, VDDO = 2.5V ± 5%, TA = 0°C TO 70°C Symbol Parameter FOUT Output Frequency tjit(cc) Cycle-to-Cycle Jitter ; NOTE 2 tsk(o) Output Skew; NOTE 1, 2 tR / tF Output Rise/Fall Time odc Output Duty Cycle tPW Output Pulse Width Test Conditions Minimum Typical 53.125 20% to 80% Maximum Units 125 MHz 30 ps TBD ps 300 700 50 tPERIOD/2 - TBD ps % tPERIOD/2 + TBD ps PLL Lock Time 1 ms tLOCK See Parameter Measurement Information section. NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. TABLE 5C. AC CHARACTERISTICS, VDD = VDDA = 3.3V ± 5%, VDDO = 1.8V ± 0.15V, TA = 0°C TO 70°C Symbol Parameter FOUT Output Frequency tjit(cc) Cycle-to-Cycle Jitter; NOTE 2 tsk(o) Output Skew; NOTE 1, 2 tR / tF Output Rise/Fall Time odc Output Duty Cycle tPW Output Pulse Width Test Conditions Minimum Typical 53.125 Maximum Units 125 MHz 30 ps TBD 20% to 80% 300 ps 700 50 tPERIOD/2 - TBD ps % tPERIOD/2 + TBD ps PLL Lock Time 1 ms tLOCK See Parameter Measurement Information section. NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. 84025EM www.icst.com/products/hiperclocks.html 4 REV. A APRIL 16, 2003 PRELIMINARY Integrated Circuit Systems, Inc. ICS84025 CRYSTAL-TO-LVCMOS / LVTTL FREQUENCY SYNTHESIZER WITH FANOUT BUFFER TYPICAL PHASE NOISE 0 -10 25MHz Input -20 RMS Phase Noise Jitter 12K to 20MHz = 3.5ps (typical) -30 -40 -60 Z (dBc H ) PHASE NOISE -50 125MHz 62.5MHz -70 -80 -90 -100 -110 -120 -130 -140 -150 10 100 1k 10k 100k 1M 10M OFFSET FREQUENCY (HZ) 0 -10 25.5MHz Input -20 RMS Phase Noise Jitter 12K to 20MHz = 3.5ps (typical) -30 -40 ( ) -60 dBc HZ PHASE NOISE -50 106.25MHz 53.125MHz -70 -80 -90 -100 -110 -120 -130 -140 -150 10 100 1k 10k 100k 1M 10M OFFSET FREQUENCY (HZ) 84025EM www.icst.com/products/hiperclocks.html 5 REV. A APRIL 16, 2003 PRELIMINARY Integrated Circuit Systems, Inc. ICS84025 CRYSTAL-TO-LVCMOS / LVTTL FREQUENCY SYNTHESIZER WITH FANOUT BUFFER PARAMETER MEASUREMENT INFORMATION VDD, VDDA, VDDO = 1.65V±5% 2.05V±5% 1.25V±5% SCOPE VDDO Qx LVCMOS Qx LVCMOS GND = -1.65V±5% GND = -1.25V±5% 3.3V OUTPUT LOAD AC TEST CIRCUIT 2.4± 0.9V SCOPE VDD 3.3V/2.5V OUTPUT LOAD AC TEST CIRCUIT 0.9V±0.075V V DDO SCOPE VDD VDDO Qx 2 Qx LVCMOS V DDO Qy 2 tsk(o) GND = -0.9V±0.075V 3.3V/1.8V OUTPUT LOAD AC TEST CIRCUIT OUTPUT SKEW VOH V V DDO DDO 2 DDO 2 tcycle ➤ n VREF 2 tcycle ➤ Q0:Q5 V n+1 ➤ VOL 1σ contains 68.26% of all measurements 2σ contains 95.4% of all measurements 3σ contains 99.73% of all measurements 4σ contains 99.99366% of all measurements 6σ contains (100-1.973x10-7)% of all measurements ➤ t jit(cc) = tcycle n –tcycle n+1 1000 Cycles Histogram Reference Point Mean Period (Trigger Edge) (First edge after trigger) Cycle-to-Cycle Jitter Period Jitter V DDO 2 Q0:Q5 80% 80% Pulse Width t 20% 20% PERIOD Clock Outputs t odc = t PW R t F t PERIOD odc, tPW & tPERIOD 84025EM OUTPUT RISE/FALL TIME www.icst.com/products/hiperclocks.html 6 REV. A APRIL 16, 2003 PRELIMINARY Integrated Circuit Systems, Inc. ICS84025 CRYSTAL-TO-LVCMOS / LVTTL FREQUENCY SYNTHESIZER WITH FANOUT BUFFER APPLICATION INFORMATION POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS84025 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, VDDA, and VDDO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 2 illustrates how a 24Ω resistor along with a 10µF and a .01µF bypass capacitor should be connected to each VDDA pin. 3.3V VDD .01µF 24 Ω VDDA .01µF 10 µF FIGURE 2. POWER SUPPLY FILTERING CRYSTAL INPUT INTERFACE A crystal can be characterized for either series or parallel mode operation. The ICS84025 has a built-in crystal oscillator circuit. This interface can accept either a series or parallel crystal without additional components and generate frequencies with accuracy suitable for most applications. Additional accuracy can be achieved by adding two small capacitors C1 and C2 as shown in Figure 3. 20 XTAL2 C1 18pF 25MHz X1 21 XTAL1 C2 22pF ICS84025 Figure 3. CRYSTAL INPUt INTERFACE 84025EM www.icst.com/products/hiperclocks.html 7 REV. A APRIL 16, 2003 PRELIMINARY Integrated Circuit Systems, Inc. ICS84025 CRYSTAL-TO-LVCMOS / LVTTL FREQUENCY SYNTHESIZER WITH FANOUT BUFFER SCHEMATIC EXAMPLE recommended to have one decouple capacitor per power pin. Each decoupling capacitor should be located as close as possible to the power pin. The low pass filter R7, C11 and C16 for clean analog supply should also be located as close to the VDDA pin as possible. Figure 4A shows a schematic example of using an ICS84025. In this example, the input is a 25MHz parallel resonant crystal with load capacitor CL=18pF. The frequency fine tuning capacitors C1 and C2 is 22pF and 18pF respectively. This example also shows logic control input handling. The configuration is set at F_SEL[1:0]=11 therefore the output frequency is 125MHz. It is VDD VDD U1 Zo = 50 R6 R7 10 PLL_SEL VDDA 22p C11 0.1u C16 10u C1 X1 25MHz,18pF F_SEL1 F_SEL0 13 14 15 16 17 18 19 20 21 22 23 24 VDDO NC GND PLL_SEL VDD VDDA GND XTAL2 XTAL1 MR F_SEL1 F_SEL0 Q5 GND Q4 VDDO Q3 GND Q2 VDDO Q1 GND Q0 VDDO 12 11 10 9 8 7 6 5 4 3 2 1 43 Zo = 50 R1 C2 43 18p ICS84025 VDD RU2 1K RU3 1K RU4 1K PLL_SEL F_SEL1 F_SEL0 RD2 SP RD3 SP SP = Spare, Not Installed VDD=3.3V VDD (U1,1) C6 0.1u RD4 SP (U1,5) (U1,9) C5 0.1u (U1,13) C3 0.1u (U1,17) C4 0.1u C7 0.1u FIGURE 4A. ICS84025 SCHEMATIC EXAMPLE 84025EM www.icst.com/products/hiperclocks.html 8 REV. A APRIL 16, 2003 PRELIMINARY Integrated Circuit Systems, Inc. ICS84025 CRYSTAL-TO-LVCMOS / LVTTL FREQUENCY SYNTHESIZER WITH FANOUT BUFFER The following component footprints are used in this layout example: • The differential 50Ω output traces should have the same length. All the resistors and capacitors are size 0603. • Avoid sharp angles on the clock trace. Sharp angle turns cause the characteristic impedance to change on the transmission lines. POWER AND GROUNDING Place the decoupling capacitors as close as possible to the power pins. If space allows, placement of the decoupling capacitor on the component side is preferred. This can reduce unwanted inductance between the decoupling capacitor and the power pin caused by the via. • Keep the clock traces on the same layer. Whenever possible, avoid placing vias on the clock traces. Placement of vias on the traces can affect the trace characteristic impedance and hence degrade signal integrity. Maximize the power and ground pad sizes and number of vias capacitors. This can reduce the inductance between the power and ground planes and the component power and ground pins. • To prevent cross talk, avoid routing other signal traces in parallel with the clock traces. If running parallel traces is unavoidable, allow a separation of at least three trace widths between the differential clock trace and the other signal trace. The RC filter consisting of R7, C11, and C16 should be placed as close to the VDDA pin as possible. • Make sure no other signal traces are routed between the clock trace pair. CLOCK TRACES • The matching termination resistors should be located as close to the receiver input pins as possible. AND TERMINATION Poor signal integrity can degrade the system performance or cause system failure. In synchronous high-speed digital systems, the clock signal is less tolerant to poor signal integrity than other signals. Any ringing on the rising or falling edge or excessive ring back can cause system failure. The shape of the trace and the trace delay might be restricted by the available space on the board and the component location. While routing the traces, the clock signal traces should be routed first and should be locked prior to routing other signal traces. CRYSTAL The crystal X1 should be located as close as possible to the pins 21 (XTAL1) and 20 (XTAL2). The trace length between the X1 and U1 should be kept to a minimum to avoid unwanted parasitic inductance and capacitance. Other signal traces should not be routed near the crystal traces. C4 R6 GND VDD R5 VIA 50 Ohm traces 50 Ohm traces R7 C3 50 Ohm traces C1 C16 C11 R4 C7 R3 VDDA 50 Ohm traces C5 X1 50 Ohm traces R2 R1 50 Ohm traces C2 PIN1 U1 C6 FIGURE 4B. PCB BOARD LAYOUT FOR ICS84025 84025EM www.icst.com/products/hiperclocks.html 9 REV. A APRIL 16, 2003 PRELIMINARY Integrated Circuit Systems, Inc. ICS84025 CRYSTAL-TO-LVCMOS / LVTTL FREQUENCY SYNTHESIZER WITH FANOUT BUFFER RELIABILITY INFORMATION TABLE 6. θJAVS. AIR FLOW TABLE qJA by Velocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 83.2°C/W 46.2°C/W 65.7°C/W 39.7°C/W 57.5°C/W 36.8°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS84025 is: 2949 84025EM www.icst.com/products/hiperclocks.html 10 REV. A APRIL 16, 2003 PRELIMINARY Integrated Circuit Systems, Inc. ICS84025 CRYSTAL-TO-LVCMOS / LVTTL FREQUENCY SYNTHESIZER WITH FANOUT BUFFER PACKAGE OUTLINE - M SUFFIX TABLE 7. PACKAGE DIMENSIONS Millimeters SYMBOL Minimum N Maximum 24 A -- 2.65 A1 0.10 -- A2 2.05 2.55 B 0.33 0.51 C 0.18 0.32 D 15.20 15.85 E 7.40 7.60 e H 1.27 BASIC 10.00 10.65 h 0.25 0.75 L 0.40 1.27 α 0° 8° Reference Document: JEDEC Publication 95, MS-013, MO-119 84025EM www.icst.com/products/hiperclocks.html 11 REV. A APRIL 16, 2003 PRELIMINARY Integrated Circuit Systems, Inc. ICS84025 CRYSTAL-TO-LVCMOS / LVTTL FREQUENCY SYNTHESIZER WITH FANOUT BUFFER TABLE 8. ORDERING INFORMATION Part/Order Number Marking Package Count Temperature ICS84025EM ICS84025EM 24 Lead SOIC 30 per tube 0°C to 70°C ICS84025EMT ICS84025EM 24 Lead SOIC on Tape and Reel 1000 0°C to 70°C While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 84025EM www.icst.com/products/hiperclocks.html 12 REV. A APRIL 16, 2003