PRELIMINARY Integrated Circuit Systems, Inc. ICS843204I FEMTOCLOCKS™ CRYSTAL-TO3.3V LVPECL FREQUENCY SYNTHESIZER GENERAL DESCRIPTION FEATURES The ICS843204I is a 4 output LVPECL Synthesizer optimized to generate Gigabit HiPerClockS™ Ethernet and SONET reference clock frequencies and is a member of the HiPerClocksTM family of high performance clock solutions from ICS. Using a 19.44MHz and 25MHz, 18pF parallel resonant crystal, 155.52MHz and 156.25MHz frequencies can be generated. The ICS843204I uses ICS’ FemtoClock TM low phase noise VCO technology and can achieve 1ps or lower typical RMS phase jitter. The ICS843204I is packaged in a 48-pin TSSOP package. • Four 3.3V LVPECL outputs ICS • Selectable crystal oscillator interface or LVCMOS/LVTTL single-ended input • Supports the following output frequencies: 155.52MHz and 156.25MHz • VCO range: 560MHz - 680MHz • RMS phase jitter @ 155.52MHz, using a 19.44MHz crystal (12kHz - 13MHz): 0.86ps (typical) • RMS phase jitter @ 156.25MHz, using a 19.44MHz crystal (1.875MHz - 20MHz): 0.52ps (typical) • Full 3.3V supply mode • -40°C to 85°C ambient operating temperature • Available in both standard and lead-free RoHS compliant packages BLOCK DIAGRAM PIN ASSIGNMENT PLL_BYPASS_A IN_SELA CLK0 SELA0 OEA0 XTAL_IN0 25MHz OSC PLL ÷4 QA0 0 XTAL_OUT0 nQA0 1 156.25MHz SELA1 625MHz OEA1 0 QA1 1 nQA1 PLL_BYPASS_B IN_SELB SELB0 CLK1 OEB0 19.44MHz XTAL_IN1 OSC PLL ÷4 XTAL_OUT1 155.52MHz 0 QB0 1 nQB0 SELB1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 IN_SEL_A CLK0 XTAL_IN0 XTAL_OUT0 nc V EE OEA0 OEA1 VCC V CCA nc nc SELB0 V EE OEB0 OEB1 VCC SELB1 V CCA nc nc nc nc nc ICS843204I OEB1 622.08MHz nQA1 QA1 nQA0 QA0 nc VCCO _A SELA1 SELA0 PLL_BYPASS_A nc nc nc nc XTAL_IN1 XTAL_OUT1 CLK1 IN_SEL_B PLL_BYPASS_B VCCO _B nc QB0 nQB0 QB1 nQB1 0 QB1 1 nQB1 48 Lead TSSOP 6.1mm x 12.5mm x 0.93mm package body G Package Top View The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice. 843204AGI www.icst.com/products/hiperclocks.html REV. A JANUARY 6, 2006 1 PRELIMINARY Integrated Circuit Systems, Inc. ICS843204I FEMTOCLOCKS™ CRYSTAL-TO3.3V LVPECL FREQUENCY SYNTHESIZER TABLE 1. PIN DESCRIPTIONS Number Name Type Description 1, 2 nQA1, QA1 Output Differential output pair. LVPECL interface levels. 3, 4 5, 10, 11, 12, 13, 20, 25, 26, 27, 28, 29, 37, 38, 44 6 nQA0, QA0 Output Differential output pair. LVPECL interface levels. nc Unused VCCO_A Power 7 SELA1 Input 8 SELA0 Input 9 Input Input 16, 47 PLL_BYPASS_A XTAL_IN1, XTAL_OUT1 CLK1, CLK0 21, 22 QB0, nQB0 Ouput 17 IN_SEL_B Input Pullup 18 PLL_BYPASS_B Input Pullup 14, 15 Input No connect. Output supply pin for Bank A outputs. Select pin. When HIGH, selects QA1/nQA1 at 155.52MHz. Pulldown When LOW, selects QA1/nQA1 at 156.25MHz. LVCMOS/LVTTL interface levels. Select pin. When HIGH, selects QA0/nQA0 at 155.52MHz. Pulldown When LOW, selects QA1/nQA1 at 156.25MHz. LVCMOS/LVTTL interface levels. Pullup When LOW, PLL is bypassed. When HIGH, PLL output is active. Parallel resonant crystal interface. XTAL_OUT1 is the output, XTAL_IN1 is the input. Pulldown LVCMOS/LVTTL clock inputs. Differential output pair. LVPECL interface levels. Select pin. When HIGH, selects XTAL1 inputs. When LOW, selects CLK1 input. LVCMOS/LVTTL interface levels. When LOW, PLL is bypassed. When HIGH, PLL output is active. 19 VCCO_B Power Output supply pin for Bank B outputs. 23, 24 QB1, nQB1 Ouput 31 SELB1 Input 30, 39 VCCA Power Differential output pair. LVPECL interface levels. Select pin. When HIGH, selects QB1/nQB1 at 155.52MHz. When LOW, selects QB1/nQB1 at 156.25MHz. LVCMOS/LVTTL interface levels. Analog supply pins. 32, 40 VCC Power Pullup Core supply pins. Output enable pin. QB1/nQB1 outputs are enable. 33 OEB1 Input Pullup LVCMOS/LVTTL interface levels. Output enable pin. QB0/nQB0 outputs are enabled. 34 OEB0 Input Pullup LVCMOS/LVTTL interface levels. Power Negative supply pins. 35, 43 VEE Select pin. When HIGH, selects QB0/nQB0 at 155.52MHz. When LOW, selects QB0/nQB0 at 156.25MHz. 36 SELB0 Input Pullup LVCMOS/LVTTL interface levels. Output enable pin. QA1/nQA1 outpus are enabled. 41 OEA1 Input Pullup LVCMOS/LVTTL interface levels. Output enable pin. QA0/nQA0 outputs are enabled. 42 OEA0 Input Pullup LVCMOS/LVTTL interface levels. XTAL_OUT0, Parallel resonant crystal interface. XTAL_OUT0 is the output, 45, 46 Input XTAL_IN0 is the input. XTAL_IN0 Select pin. When HIGH, selects XTAL0 inputs. When LOW, 48 IN_SEL_A Input Pullup selects CLK0 input. LVCMOS/LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN Input Capacitance 4 pF RPULLDOWN Input Pulldown Resistor 51 kΩ RPULLUP Input Pullup Resistor 843204AGI Test Conditions Minimum Typical 51 www.icst.com/products/hiperclocks.html 2 Maximum Units kΩ REV. A JANUARY 6, 2006 PRELIMINARY Integrated Circuit Systems, Inc. ICS843204I FEMTOCLOCKS™ CRYSTAL-TO3.3V LVPECL FREQUENCY SYNTHESIZER ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCC 4.6V Inputs, VI -0.5V to VCC + 0.5V Outputs, IO Continuous Current Surge Current 50mA 100mA NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Package Thermal Impedance, θJA 58.3°C/W (0 lfpm) Storage Temperature, TSTG -65°C to 150°C TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO_A = VCCO_B = 3.3V±10%, TA = -40°C TO 85°C Symbol Parameter Minimum Typical Maximum Units VCC Core Supply Voltage Test Conditions 2.97 3.3 3.63 V VCCA Analog Supply Voltage 2.97 3.3 3.63 V VCCO_A, VCCO_B Output Supply Voltage 2.97 3.3 3.63 V IEE Power Supply Current 125 mA ICC Core Supply Current 92 mA ICCA Analog Supply Current 14 mA ICCO_A, ICCO_B Output Supply Current 16 mA TABLE 3B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCA = VCCO_A = VCCO_B = 3.3V±10%, TA = -40°C TO 85°C Symbol VIH VIL IIH IIL 843204AGI Parameter Input High Voltage Input Low Voltage Input High Current Input Low Current Test Conditions Minimum Typical 2 -0.3 Maximum VCC + 0.3 Units V 0.8 V CLK0, CLK1, SELA0, SELA1 VCC = VIN = 3.63V 150 µA PLL_BYPASS_A, PLL_BYPASS_B, IN_SEL_A, IN_SEL_B, SELB1, SELB0, OEB0, OEB1, OEA0, OEA1 VCC = VIN = 3.63V 5 µA CLK0, CLK1, SELA0, SELA1 VCC = 3.63V, VIN = 0V -5 µA PLL_BYPASS_A, PLL_BYPASS_B, IN_SEL_A, IN_SEL_B, SELB1, SELB0, OEB0, OEB1, OEA0, OEA1 VCC = 3.63V, VIN = 0V -150 µA www.icst.com/products/hiperclocks.html 3 REV. A JANUARY 6, 2006 PRELIMINARY Integrated Circuit Systems, Inc. ICS843204I FEMTOCLOCKS™ CRYSTAL-TO3.3V LVPECL FREQUENCY SYNTHESIZER TABLE 3C. LVPECL DC CHARACTERISTICS, VCC = VCCA = VCCO_A = VCCO_B = 3.3V±10%, TA = -40°C TO 85°C Symbol Parameter Test Conditions VOH Output High Voltage; NOTE 1 VOL Output Low Voltage; NOTE 1 VSWING Peak-to-Peak Output Voltage Swing Minimum Typical Maximum Units VCCO - 1.4 VCCO - 0.9 V VCCO - 2.0 VCCO - 1.7 V 0.6 1.0 V Maximum Units NOTE 1: Outputs terminated with 50Ω to VCCO - 2V. TABLE 4. CRYSTAL CHARACTERISTICS Parameter Test Conditions Minimum Mode of Oscillation Typical Fundamental 25 MHz Equivalent Series Resistance (ESR) Frequency 19.44 50 Ω Shunt Capacitance 7 pF Drive Level 1 mW Maximum Units NOTE: Characterized using an 18pF parallel resonant cr ystal. TABLE 5. AC CHARACTERISTICS, VCC = VCCA = VCCO_A = VCCO_B = 3.3V±10%, TA = -40°C TO 85°C Symbol Parameter fOUT Output Frequency t sk(o) Output Skew; NOTE 1, 2 t jit(Ø) RMS Phase Jitter (Random); NOTE 3 t R / tF Output Rise/Fall Time Test Conditions Minimum Typical SELB0 = 1; OEB0 = 1 155.52 MHz SELA0 = 0; OEA0 = 1 156.25 MHz TBD ps 155.52MHz, (12kHz - 1.3MHz) 0.86 ps 156.25MHz, (1.875MHz - 20MHz) 0.52 ps 20% to 80% 475 ps odc Output Duty Cycle 50 NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at VCCO/2. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: See Phase Noise plot. 843204AGI www.icst.com/products/hiperclocks.html 4 % REV. A JANUARY 6, 2006 PRELIMINARY Integrated Circuit Systems, Inc. ICS843204I FEMTOCLOCKS™ CRYSTAL-TO3.3V LVPECL FREQUENCY SYNTHESIZER PARAMETER MEASUREMENT INFORMATION 2V Qx V CC , VCCA, VCCO_X nQx SCOPE Qx nQy LVPECL Qy nQx VEE tsk(o) -1.3V ± 0.33V 3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT OUTPUT SKEW Noise Power Phase Noise Plot Phase Noise Mask 80% 80% VSW I N G f1 Offset Frequency Clock Outputs 20% 20% f2 tR tF RMS Jitter = Area Under the Masked Phase Noise Plot RMS PHASE JITTER OUTPUT RISE/FALL TIME nQA0, nQA1 nQB0, nQB1 QA0, QA1 QB0, QB1 t PW t odc = PERIOD t PW x 100% t PERIOD OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD 843204AGI www.icst.com/products/hiperclocks.html 5 REV. A JANUARY 6, 2006 PRELIMINARY Integrated Circuit Systems, Inc. ICS843204I FEMTOCLOCKS™ CRYSTAL-TO3.3V LVPECL FREQUENCY SYNTHESIZER APPLICATION INFORMATION POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS843204I provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VCC, VCCA, and VCCO_x should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10Ω resistor along with a 10µF and a .01μF bypass capacitor should be connected to each VCCA. 3.3V VCC .01μF 10Ω VCCA .01μF 10μF FIGURE 1. POWER SUPPLY FILTERING CRYSTAL INPUT INTERFACE The ICS843204I has been characterized with 18pF parallel resonant crystals. The capacitor values shown in Figure 2 below were determined using an 18pF parallel resonant crystal and were chosen to minimize the ppm error. XTAL_OUT C1 33p X1 18pF Parallel Crystal XTAL_IN C2 27p ICS843204I Figure 2. CRYSTAL INPUt INTERFACE 843204AGI www.icst.com/products/hiperclocks.html 6 REV. A JANUARY 6, 2006 PRELIMINARY Integrated Circuit Systems, Inc. ICS843204I FEMTOCLOCKS™ CRYSTAL-TO3.3V LVPECL FREQUENCY SYNTHESIZER RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS: OUTPUTS: CRYSTAL INPUT: For applications not requiring the use of the crystal oscillator input, both XTAL_IN and XTAL_OUT can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from XTAL_IN to ground. LVPECL OUTPUT All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. CLK INPUT: For applications not requiring the use of a clock input, it can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from the CLK input to ground. LVCMOS CONTROL PINS: All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. TERMINATION FOR 3.3V LVPECL OUTPUT The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. outputs are designed to drive 50Ω transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 3A and 3B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These 3.3V Zo = 50Ω 125Ω FOUT 125Ω FIN Zo = 50Ω Zo = 50Ω FOUT 50Ω RTT = 1 Z ((VOH + VOL) / (VCC – 2)) – 2 o Zo = 50Ω VCC - 2V RTT 84Ω FIGURE 3A. LVPECL OUTPUT TERMINATION 843204AGI FIN 50Ω 84Ω FIGURE 3B. LVPECL OUTPUT TERMINATION www.icst.com/products/hiperclocks.html 7 REV. A JANUARY 6, 2006 PRELIMINARY Integrated Circuit Systems, Inc. ICS843204I FEMTOCLOCKS™ CRYSTAL-TO3.3V LVPECL FREQUENCY SYNTHESIZER POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS843002. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS843002 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 10% = 3.63V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • • Power (core)MAX = VCC_MAX * IEE_MAX = 3.63V * 125mA = 453.75mW Power (outputs)MAX = 30mW/Loaded Output pair If all outputs are loaded, the total power is 4 * 30mW = 120mW Total Power_MAX (3.63V, with all outputs switching) = 453.75mW + 120mW = 573.75mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 52.3°C/W per Table 7 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.574W * 52.3°C/W = 115°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). TABLE 7. THERMAL RESISTANCE θJA FOR 48-PIN TSSOP, FORCED CONVECTION θJA by Velocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 82.6°C/W 58.3°C/W 200 70.3°C/W 52.3°C/W 500 63.7°C/W 49.9°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. 843204AGI www.icst.com/products/hiperclocks.html 8 REV. A JANUARY 6, 2006 PRELIMINARY Integrated Circuit Systems, Inc. ICS843204I FEMTOCLOCKS™ CRYSTAL-TO3.3V LVPECL FREQUENCY SYNTHESIZER 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 4. VCCO Q1 VOUT RL 50 VCCO - 2V FIGURE 4. LVPECL DRIVER CIRCUIT AND TERMINATION To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage of V - 2V. CCO • For logic high, VOUT = V OH_MAX (V CCO_MAX • -V OH_MAX OL_MAX CCO_MAX -V CCO_MAX – 0.9V ) = 0.9V For logic low, VOUT = V (V =V =V CCO_MAX – 1.7V ) = 1.7V OL_MAX Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(V OH_MAX – (V CCO_MAX - 2V))/R ] * (V CCO_MAX L -V OH_MAX ) = [(2V - (V CCO_MAX -V OH_MAX ))/R ] * (V CCO_MAX L -V )= OH_MAX [(2V - 0.9V)/50Ω] * 0.9V = 19.8mW Pd_L = [(V OL_MAX – (V CCO_MAX - 2V))/R ] * (V L CCO_MAX -V OL_MAX ) = [(2V - (V CCO_MAX -V OL_MAX ))/R ] * (V L CCO_MAX -V )= OL_MAX [(2V - 1.7V)/50Ω] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW 843204AGI www.icst.com/products/hiperclocks.html 9 REV. A JANUARY 6, 2006 PRELIMINARY Integrated Circuit Systems, Inc. ICS843204I FEMTOCLOCKS™ CRYSTAL-TO3.3V LVPECL FREQUENCY SYNTHESIZER RELIABILITY INFORMATION TABLE 8. θJAVS. AIR FLOW TABLE FOR 48 LEAD TSSOP θJA by Velocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 82.6°C/W 58.3°C/W 200 70.3°C/W 52.3°C/W 500 63.7°C/W 49.9°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS843204I is: 4090 843204AGI www.icst.com/products/hiperclocks.html 10 REV. A JANUARY 6, 2006 PRELIMINARY Integrated Circuit Systems, Inc. ICS843204I FEMTOCLOCKS™ CRYSTAL-TO3.3V LVPECL FREQUENCY SYNTHESIZER PACKAGE OUTLINE - G SUFFIX FOR 48 LEAD TSSOP TABLE 9. PACKAGE DIMENSIONS SYMBOL Millimeters Minimum N A Maximum 48 -- 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.17 0.27 c 0.09 0.20 D 12.40 12.60 E E1 8.10 BASIC 6.00 6.20 0.50 BASIC e L 0.45 0.75 α 0° 8° aaa -- 0.10 Reference Document: JEDEC Publication 95, MO-153 843204AGI www.icst.com/products/hiperclocks.html 11 REV. A JANUARY 6, 2006 PRELIMINARY Integrated Circuit Systems, Inc. ICS843204I FEMTOCLOCKS™ CRYSTAL-TO3.3V LVPECL FREQUENCY SYNTHESIZER TABLE 10. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature ICS843204AGI ICS843204AGI 48 Lead TSSOP tube -40°C to 85°C ICS843204AGIT ICS843204AGI 48 Lead TSSOP 1000 tape & reel -40°C to 85°C ICS843204AGILF TBD 48 Lead "Lead-Free" TSSOP tube -40°C to 85°C ICS843204AGILFT TBD 48 Lead "Lead-Free" TSSOP 1000 tape & reel -40°C to 85°C NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant. The aforementioned trademarks, HiPerClockS and FEMTOCLOCKS are trademarks of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 843204AGI www.icst.com/products/hiperclocks.html 12 REV. A JANUARY 6, 2006