ICS854054 Integrated Circuit Systems, Inc. 4:1 DIFFERENTIAL-TO-LVDS CLOCK MULTIPLEXER GENERAL DESCRIPTION FEATURES The ICS854054 is a 4:1 Differential-to-LVDS Clock Multiplexer which can operate up to 2.8GHz and HiPerClockS™ is a member of the HiPerClockS™ family of High Performance Clock Solutions from ICS. The ICS854054 has 4 selectable differential clock inputs. The PCLK, nPCLK input pairs can accept LVPECL, LVDS, CML or SSTL levels. The fully differential architecture and low propagation delay make it ideal for use in clock distribution circuits. The select pins have internal pulldown resistors. The SEL1 pin is the most significant bit and the binary number applied to the select pins will select the same numbered data input (i.e., 00 selects PCLK0, nPCLK0). • High speed 4:1 differential multiplexer ICS • One differential LVDS output • Four selectable differential clock inputs • PCLKx, nPCLKx pairs can accept the following differential input levels: LVPECL, LVDS, CML, SSTL • Maximum output frequency: 2.8GHz • Translates any single ended input signal to LVDS levels with resistor bias on nPCLKx input • Part-to-part skew: 375ps (maximum) • Propagation delay: 700ps (maximum) • Supply voltage range: 3.135V to 3.465V • -40°C to 85°C ambient operating temperature • Available in both standard and lead-free RoHS compliant packages BLOCK DIAGRAM PIN ASSIGNMENT PCLK0 nPCLK0 00(default) PCLK1 nPCLK1 01 PCLK2 nPCLK2 PCLK3 nPCLK3 Q nQ 10 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VDD Q nQ GND nPCLK3 PCLK3 nPCLK2 PCLK2 ICS854054 16-Lead TSSOP 4.4mm x 5.0mm x 0.92mm package body G Package Top View 11 SEL1 854054AG PCLK0 nPCLK0 PCLK1 nPCLK1 VDD SEL0 SEL1 GND SEL0 www.icst.com/products/hiperclocks.html 1 REV. A MARCH 29, 2006 ICS854054 Integrated Circuit Systems, Inc. 4:1 DIFFERENTIAL-TO-LVDS CLOCK MULTIPLEXER TABLE 1. PIN DESCRIPTIONS Number Name 1 PCLK0 Input Type Pulldown Description 2 nPCLK0 Input Pullup/Pulldown 3 PCLK1 Input Pulldown 4 nPCLK1 Input Pullup/Pulldown 5, 16 VDD Power 6, 7 SEL0, SEL1 Input 8, 13 GND Power 9 PCLK2 Input Non-inver ting differential clock input. Inver ting differential clock input. VDD/2 default when left floating. Non-inver ting differential clock input. Inver ting differential clock input. VDD/2 default when left floating. Positive supply pins. Pulldown Clock select input pins. LVCMOS/LVTTL interface levels. Power supply ground. Pulldown Non-inver ting differential clock input. Inver ting differential clock input. Pullup/Pulldown VDD/2 default when left floating. 10 nPCLK2 Input 11 PCLK3 Input Pulldown 12 nPCLK3 Input Pullup/Pulldown 14, 15 nQ0, Q0 Output Non-inver ting differential clock input. Inver ting differential clock input. VDD/2 default when left floating. Differential output pair. LVDS interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions Minimum Typical Maximum Units RPULLDOWN Pulldown Resistor 75 kΩ RVDD/2 Pullup/Pulldown Resistors 50 kΩ TABLE 3. CLOCK INPUT FUNCTION TABLE Inputs Outputs SEL1 SEL0 Q nQ 0 0 PCLK0 nPCLK0 0 1 PCLK1 nPCLK1 1 0 PCLK2 nPCLK2 1 1 PCLK3 nPCLK3 854054AG www.icst.com/products/hiperclocks.html 2 REV. A MARCH 29, 2006 ICS854054 Integrated Circuit Systems, Inc. 4:1 DIFFERENTIAL-TO-LVDS CLOCK MULTIPLEXER ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD 5.5V Inputs, VI -0.5V to VDD + 0.5 V Outputs, IO Continuous Current 10mA Surge Current NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. 15mA Package Thermal Impedance, θJA 89°C/W (0 lfpm) Storage Temperature, TSTG -65°C to 150°C TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V ± 5%, TA = -40°C TO 85°C Symbol Parameter Test Conditions VDD Positive Supply Voltage IDD Power Supply Current Minimum Typical Maximum Units 3.135 3.3 3.465 V 90 mA TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter VIH Input High Voltage Test Conditions Minimum Typical 2 VIL Input Low Voltage IIH Input High Current VDD = VIN = 3.465V -0.3 IIL Input Low Current VDD = 3.465V, VIN = 0V Maximum Units VDD + 0.3 V 0.8 V 150 µA -10 µA TABLE 4C. LVPECL DC CHARACTERISTICS, VDD = 3.3V ± 5%, TA = -40°C TO 85°C Symbol Parameter Maximum Units PCLK0:PCLK3 VDD = VIN = 3.465V Test Conditions 150 µA nPCLK0:nPCLK3 VDD = VIN = 3.465V 150 µA IIH Input High Current IIL Input Low Current VPP Peak-to-Peak Input Voltage Minimum PCLK0:PCLK3 VDD = 3.465V, VIN = 0V -10 nPCLK0:nPCLK3 VDD = 3.465V, VIN = 0V -150 Typical 0.15 VCMR Common Mode Input Voltage; NOTE 1, 2 1.2 NOTE 1: Common mode voltage is defined as VIH. NOTE 2: For single ended applications, the maximum input voltage for PCLKx or nPCLKx is VDD + 0.3V. 854054AG www.icst.com/products/hiperclocks.html 3 µA µA 1.2 V VDD V REV. A MARCH 29, 2006 ICS854054 Integrated Circuit Systems, Inc. 4:1 DIFFERENTIAL-TO-LVDS CLOCK MULTIPLEXER TABLE 4D. LVDS DC CHARACTERISTICS, VDD = 3.3V ± 5%, TA = -40°C TO 85°C Symbol Parameter VOD Differential Output Voltage Δ VOD VOD Magnitude Change VOS Offset Voltage Δ VOS VOS Magnitude Change Test Conditions Minimum Typical Maximum Units 250 450 525 mV 50 mV 1.125 1.25 1.375 V 50 mV Maximum Units 2.8 GHz 700 ps TABLE 5. AC CHARACTERISTICS, VDD = 3.135V TO 3.465V, TA = -40°C TO 85°C Symbol Parameter Test Conditions fMAX Output Frequency tPD t sk(pp) Propagation Delay; NOTE 1 Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section Par t-to-Par t Skew; NOTE 2, 3 t sk(i) t R / tF t jit Minimum Typical 325 155.52 MHz, (12kHz - 20MHz) 0.195 375 ps Input Skew 90 ps Output Rise/Fall Time 250 ps 20% to 80% 50 155.52MHz, MUXISOLATION MUX Isolation -50 Input Peak-to-Peak = 800mV All parameters measured up to 1.5MHz unless noted otherwise. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 3: This parameter is defined according with JEDEC Standard 65. 854054AG ps www.icst.com/products/hiperclocks.html 4 dB REV. A MARCH 29, 2006 ICS854054 Integrated Circuit Systems, Inc. 4:1 DIFFERENTIAL-TO-LVDS CLOCK MULTIPLEXER ADDITIVE PHASE JITTER the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot. The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in 0 -10 Additive Phase Jitter, RMS -20 @ 155.52MHz (12kHz - 20MHz) = <0.195ps typical -30 -40 -50 SSB PHASE NOISE dBc/HZ -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 1k 10k 100k 1M 10M 100M OFFSET FROM CARRIER FREQUENCY (HZ) As with most timing specifications, phase noise measurements have issues. The primary issue relates to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the device. This is illustrated above. The de- 854054AG vice meets the noise floor of what is shown, but can actually be lower. The phase noise is dependant on the input source and measurement equipment. www.icst.com/products/hiperclocks.html 5 REV. A MARCH 29, 2006 ICS854054 Integrated Circuit Systems, Inc. 4:1 DIFFERENTIAL-TO-LVDS CLOCK MULTIPLEXER PARAMETER MEASUREMENT INFORMATION V DD SCOPE Qx nPCLK0:3 3.3V±5% Power Supply Float GND + - LVDS V V Cross Points PP CMR PCLK0:3 nQx GND 3.3V OUTPUT LOAD AC TEST CIRCUIT DIFFERENTIAL INPUT LEVEL nPCLK0:3 nQx PART 1 Qx PCLK0:3 nQ0 nQy PART 2 Qy Q0 tPD tsk(pp) PROPAGATION DELAY PART-TO-PART SKEW nPCLK0 PCLK0 80% nPCLK1 80% VOD Clock Outputs PCLK1 20% 20% tR nQ tF Q tPD2 tPD1 tsk(i) tsk(i) = |tPD1 - tPD2| INPUT SKEW OUTPUT RISE/FALL TIME VDD out VDD DC Input LVDS ➤ ➤ out ➤ 100 ➤ VOD/Δ VOD out out ➤ LVDS DIFFERENTIAL OUTPUT VOLTAGE 854054AG VOS/Δ VOS ➤ DC Input OFFSET VOLTAGE www.icst.com/products/hiperclocks.html 6 REV. A MARCH 29, 2006 ICS854054 Integrated Circuit Systems, Inc. 4:1 DIFFERENTIAL-TO-LVDS CLOCK MULTIPLEXER APPLICATION INFORMATION WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD= 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. VDD R1 1K Single Ended Clock Input PCLK V_REF nPCLK C1 0.1u R2 1K FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT RECOMMENDATIONS FOR UNUSED INPUT PINS INPUTS: PCLK/nPCLK INPUT: For applications not requiring the use of a differential input, both the PCLK and nPCLK pins can be left floating. Though not required, but for additional protection, a 1kΩ resister can be tied from PCLK to ground. SELECT PINS: All select pins have internal pull-ups and pull-downs; additional resistance is not required but can be added for additional protection. A 1kΩ resister can be used. 854054AG www.icst.com/products/hiperclocks.html 7 REV. A MARCH 29, 2006 ICS854054 Integrated Circuit Systems, Inc. 4:1 DIFFERENTIAL-TO-LVDS CLOCK MULTIPLEXER LVPECL CLOCK INPUT INTERFACE gested here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements. The PCLK /nPCLK accepts LVPECL, CML, SSTL and other differential signals. Both VSWING and V OH must meet the VPP and VCMR input requirements. Figures 2A to 2E show interface examples for the HiPerClockS PCLK/nPCLK input driven by the most common driver types. The input interfaces sug- 2.5V 3.3V 3.3V 3.3V 2.5V 3.3V R1 50 CML R3 120 R2 50 SSTL Zo = 50 Ohm R4 120 Zo = 60 Ohm PCLK PCLK Zo = 60 Ohm Zo = 50 Ohm nPCLK nPCLK HiPerClockS PCLK/nPCLK R1 120 FIGURE 2A. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A CML DRIVER HiPerClockS PCLK/nPCLK R2 120 FIGURE 2B. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY AN SSTL IN DRIVER 3.3V 3.3V 3.3V 3.3V 3.3V R3 125 R4 125 Zo = 50 Ohm LVDS_Driv er Zo = 50 Ohm CLK CLK R1 100 Zo = 50 Ohm nCLK LVPECL R1 84 nCLK Receiv er Zo = 50 Ohm HiPerClockS Input R2 84 FIGURE 2C. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER FIGURE 2D. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVDS DRIVER 3.3V 3.3V 3.3V 3.3V LVPECL Zo = 50 Ohm C1 Zo = 50 Ohm C2 R3 84 R4 84 PCLK nPCLK R5 100 - 200 R6 100 - 200 R1 125 HiPerClockS PCLK/nPCLK R2 125 FIGURE 2E. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER WITH AC COUPLE 854054AG www.icst.com/products/hiperclocks.html 8 REV. A MARCH 29, 2006 ICS854054 Integrated Circuit Systems, Inc. 4:1 DIFFERENTIAL-TO-LVDS CLOCK MULTIPLEXER LVDS DRIVER TERMINATION A general LVDS interface is shown in Figure 3. In a 100Ω differential transmission line environment, LVDS drivers require a matched load termination of 100Ω across near the receiver input. For a multiple LVDS outputs buffer, if only partial outputs are used, it is recommended to terminate the unused outputs. 3.3V 3.3V LVDS_Driv er + R1 100 - 100 Ohm Differiential Transmission Line FIGURE 3. TYPICAL LVDS DRIVER TERMINATION 854054AG www.icst.com/products/hiperclocks.html 9 REV. A MARCH 29, 2006 ICS854054 Integrated Circuit Systems, Inc. 4:1 DIFFERENTIAL-TO-LVDS CLOCK MULTIPLEXER POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS854054. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS854054 is the sum of the core power. The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. • Power (core)MAX = VDD_MAX * IDD_MAX = 3.465V * 90mA = 311.85mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature qJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 81.8°C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.312W * 81.8°C/W = 110.5°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). TABLE 6. THERMAL RESISTANCE θJA FOR 16-LEAD TSSOP, FORCED CONVECTION θJA by Velocity (Linear Feet per Minute) 0 Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 137.1°C/W 89.0°C/W 200 118.2°C/W 81.8°C/W 500 106.8°C/W 78.1°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. 854054AG www.icst.com/products/hiperclocks.html 10 REV. A MARCH 29, 2006 ICS854054 Integrated Circuit Systems, Inc. 4:1 DIFFERENTIAL-TO-LVDS CLOCK MULTIPLEXER RELIABILITY INFORMATION TABLE 7. θJAVS. AIR FLOW TABLE FOR 16 LEAD TSSOP θJA by Velocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 137.1°C/W 89.0°C/W 118.2°C/W 81.8°C/W 106.8°C/W 78.1°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS854054 is: 361 854054AG www.icst.com/products/hiperclocks.html 11 REV. A MARCH 29, 2006 ICS854054 Integrated Circuit Systems, Inc. PACKAGE OUTLINE - G SUFFIX FOR 4:1 DIFFERENTIAL-TO-LVDS CLOCK MULTIPLEXER 16 LEAD TSSOP TABLE 8. PACKAGE DIMENSIONS Millimeters SYMBOL Minimum N A Maximum 16 -- 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 4.90 5.10 E E1 6.40 BASIC 4.30 e 4.50 0.65 BASIC L 0.45 0.75 α 0° 8° aaa -- 0.10 Reference Document: JEDEC Publication 95, MO-153 854054AG www.icst.com/products/hiperclocks.html 12 REV. A MARCH 29, 2006 Integrated Circuit Systems, Inc. ICS854054 4:1 DIFFERENTIAL-TO-LVDS CLOCK MULTIPLEXER TABLE 9. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature ICS854054AG 854054AG 16 Lead TSSOP tube -40°C to 85°C ICS854054AGT 854054AG 16 Lead TSSOP 2500 tape & reel -40°C to 85°C ICS854054AGLF TBD 16 Lead TSSOP tube -40°C to 85°C ICS854054AGLFT TBD 16 Lead TSSOP 2500 tape & reel -40°C to 85°C NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant. The aforementioned trademark, HiPerClockS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 854054AG www.icst.com/products/hiperclocks.html 13 REV. A MARCH 29, 2006