ICS ICS853006AGT

Integrated
Circuit
Systems, Inc.
ICS853006
LOW SKEW, 1-TO-6
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
GENERAL DESCRIPTION
FEATURES
The ICS853006 is a low skew, high performance
1-to-6 Differential-to-2.5V/3.3V LVPECL/ECL
HiPerClockS™
Fanout Buffer and a member of the HiPerClockS™
family of High Performance Clock Solutions from
ICS. The ICS853006 is characterized to operate
from a 2.5V or a 3.3V power supply. Guaranteed output and
part-to-part skew characteristics make the ICS853006 ideal
for those applications demanding well defined performance
and repeatability.
• 6 differential LVPECL outputs
ICS
• 1 differential PCLK, nPCLK input pair
• PCLK, nPCLK pair can accept the following
differential input levels: LVPECL, LVDS, CML, SSTL
• Maximum output frequency: > 2GHz
• Output skew: 30ps (maximum)
• Part-to-part skew: 150ps (maximum)
• Propagation delay: 510ps (maximum)
• LVPECL mode operating voltage supply range:
VCC = 2.375V to 3.465V, VEE = 0V
• ECL mode operating voltage supply range:
VCC = 0V, VEE = -2.375V to -3.465V
• -40°C to 85°C ambient operating temperature
BLOCK DIAGRAM
PCLK
nPCLK
V BB
PIN ASSIGNMENT
VCC
nQ0
Q0
nQ1
Q1
nQ2
Q2
VCC
PCLK
nPCLK
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
20
19
18
17
16
15
14
13
12
11
VCC
Q5
nQ5
Q4
nQ4
Q3
nQ3
VCC
VEE
VBB
ICS853006
20-Lead TSSOP
6.5mm x 4.4mm x 0.92mm package body
G Package
Top View
Q5
nQ5
853006AG
1
2
3
4
5
6
7
8
9
10
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1
REV. A AUGUST 18, 2004
ICS853006
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-6
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
TABLE 1. PIN DESCRIPTIONS
Number
Name
1, 8, 13, 20
VCC
2, 3
4, 5
Type
Description
Power
Positive supply pins.
nQ0, Q0
Output
Differential output pair. LVPECL interface levels.
nQ1, Q1
Output
Differential output pair. LVPECL interface levels.
6, 7
nQ2, Q2
Output
Differential output pair. LVPECL interface levels.
9
PCLK
Input
10
nPCLK
Input
11
VBB
Output
12
VEE
Power
Negative supply pin.
Pulldown Non-inver ting differential LVPECL clock input.
Pullup/
Inver ting differential LVPECL clock input. VCC/2 default when left floating.
Pulldown
Bias voltage.
14, 15
nQ3, Q3
Output
Differential output pair. LVPECL interface levels.
16, 17
nQ4, Q4
Output
Differential output pair. LVPECL interface levels.
18, 19
nQ5, Q5
Output
Differential output pair. LVPECL interface levels.
NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
RPULLDOWN
Input Pulldown Resistor
Test Conditions
Minimum
Typical
75
Maximum
Units
KΩ
RVCC/2
Input Pullup/Pulldown Resistor
50
KΩ
TABLE 3. CLOCK INPUT FUNCTION TABLE
Input
PCLK
Outputs
nPCLK
Q0:Q5
nQ0:nQ5
Input to Output Mode
Polarity
0
1
LOW
HIGH
Differential to Differential
Non Inver ting
1
0
HIGH
LOW
Differential to Differential
Non Inver ting
0
Biased; NOTE 1
LOW
HIGH
Single Ended to Differential
Non Inver ting
1
Biased; NOTE 1
HIGH
LOW
Single Ended to Differential
Non Inver ting
Biased; NOTE 1
0
HIGH
LOW
Single Ended to Differential
Inver ting
Biased; NOTE 1
1
LOW
HIGH
Single Ended to Differential
Inver ting
NOTE 1: Please refer to the Application Information section, "Wiring the Differential Input to Accept Single Ended Levels".
853006AG
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2
REV. A AUGUST 18, 2004
Integrated
Circuit
Systems, Inc.
ICS853006
LOW SKEW, 1-TO-6
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
ABSOLUTE MAXIMUM RATINGS
Inputs, VI (LVPECL mode)
4.6V (LVPECL mode, VEE = 0) NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage
-4.6V (ECL mode, VCC = 0)
to the device. These ratings are stress specifi-0.5V to V + 0.5 V
Inputs, VI (ECL mode)
0.5V to VEE - 0.5V
Supply Voltage, VCC
Negative Supply Voltage, VEE
Outputs, IO
Continuous Current
Surge Current
VBB Sink/Source, IBB
CC
cations only. Functional operation of product at
these conditions or any conditions beyond those
50mA
100mA
listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maxi-
± 0.5mA
mum rating conditions for extended periods may
affect product reliability.
Operating Temperature Range, TA -40°C to +85°C
Storage Temperature, TSTG
-65°C to 150°C
Package Thermal Impedance, θJA
73.2°C/W (0 lfpm)
(Junction-to-Ambient)
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = 2.375V TO 3.465V; VEE = 0V
Symbol
Parameter
VCC
Positive Supply Voltage
I EE
Power Supply Current
Test Conditions
Minimum
Typical
Maximum
Units
2.375
3.3
3.465
V
115
mA
TABLE 4B. LVPECL DC CHARACTERISTICS, VCC = 3.3V; VEE = 0V
Symbol
Parameter
Min
-40°C
Typ
Max
Min
25°C
Typ
Max
Min
85°C
Typ
Max
Units
VOH
Output High Voltage; NOTE 1
2.175
2.275
2.38
2.225
2.295
2.37
2.295
2.33
2.365
V
VOL
Output Low Voltage; NOTE 1
1.405
1.545
1.68
1.425
1.52
1.615
1.44
1.535
1.63
V
VIH
Input High Voltage(Single-Ended)
2.075
2.36
2.075
2.36
2.075
2.36
V
VIL
Input Low Voltage(Single-Ended)
1.43
1.765
1.43
1.765
1.43
1.765
V
VBB
Output Voltage Reference; NOTE 2
1.86
1.98
1.86
1.98
1.86
1.98
V
VPP
Peak-to-Peak Input Voltage
Input High Voltage
Common Mode Range; NOTE 3, 4
Input
PCLK, nPCLK
High Current
PCLK
Input
Low Current nPCLK
150
1200
150
1200
150
1200
mV
3.3
1.2
3.3
1.2
3.3
V
150
µA
VCMR
IIH
IIL
800
1.2
800
150
150
800
-10
-10
-10
µA
-150
-150
-150
µA
Input and output parameters vary 1:1 with VCC. VEE can vary +0.925V to -0.5V.
NOTE 1: Outputs terminated with 50Ω to VCC - 2V.
NOTE 2: Single-ended input operation is limited. VCC ≥ 3V in LVPECL mode.
NOTE 3: Common mode voltage is defined as VIH.
NOTE 4: For single-ended applications, the maximum input voltage for PCLK, nPCLK is VCC + 0.3V.
853006AG
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3
REV. A AUGUST 18, 2004
Integrated
Circuit
Systems, Inc.
ICS853006
LOW SKEW, 1-TO-6
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = 2.5V; VEE = 0V
Symbol
Parameter
VOH
VOL
-40°C
25°C
85°C
Units
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Output High Voltage; NOTE 1
1.375
1.475
1.58
1.425
1.495
1.57
1.495
1.53
1.565
V
Output Low Voltage; NOTE 1
0.605
0.745
0.88
0.625
0.72
0.815
0.64
0.735
0.83
V
VIH
Input High Voltage(Single-Ended)
1.275
1.56
1.275
1.56
1.275
-0.83
V
VIL
Input Low Voltage(Single-Ended)
0.63
0.965
0.63
0.965
0.63
0.965
V
VPP
150
1200
150
1200
150
1200
mV
2.5
1.2
2.5
1.2
2.5
V
IIH
Peak-to-Peak Input Voltage
Input High Voltage
Common Mode Range; NOTE 3, 4
Input
PCLK0, nPCLK
High Current
150
µA
IIL
Input
Low Current
VCMR
PCLK
800
1.2
800
150
-10
800
150
-10
µA
-150
-150
-150
nPCLK
Input and output parameters var y 1:1 with VCC. VEE can var y +0.925V to -0.5V.
NOTE 1: Outputs terminated with 50Ω to VCC - 2V.
NOTE 2: Single-ended input operation is limited. VCC ≥ 3V in LVPECL mode.
NOTE 3: Common mode voltage is defined as VIH.
NOTE 4: For single-ended applications, the maximum input voltage for PCLK, nPCLK is VCC + 0.3V.
-10
µA
TABLE 4D. ECL DC CHARACTERISTICS, VCC = 0V; VEE = -3.465V TO -2.375V
Symbol
Parameter
VOH
-40°C
25°C
85°C
Units
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Output High Voltage; NOTE 1
-1.125
-1.025
-0.92
-1.075
-1.005
-0.93
-1.005
-0.97
-0.935
VOL
Output Low Voltage; NOTE 1
-1.895
-1.755
-1.62
-1.875
-1.78
-1.685
-1.86
-1.765
-1.67
V
VIH
Input High Voltage(Single-Ended)
-1.225
-0.94
-1.225
-0.94
-1.225
-0.94
V
VIL
Input Low Voltage(Single-Ended)
-1.87
-1.535
-1.87
-1.535
-1.87
-1.535
V
VBB
Output Voltage Reference; NOTE 2
-1.44
-1.32
-1.44
-1.32
-1.44
VPP
150
1200
150
1200
150
0
VEE+1.2V
0
VEE+1.2V
IIH
Peak-to-Peak Input Voltage
Input High Voltage
Common Mode Range; NOTE 3, 4
Input
PCLK, nPCLK
High Current
IIL
Input
Low Current
VCMR
P CLK
800
VEE+1.2V
150
150
-10
800
-1.32
V
1200
mV
0
V
150
µA
-10
µA
-150
-150
-150
nPCLK
Input and output parameters vary 1:1 with VCC. VEE can vary +0.925V to -0.5V.
NOTE 1: Outputs terminated with 50Ω to VCC - 2V.
NOTE 2: Single-ended input operation is limited. VCC ≥ 3V in LVPECL mode.
NOTE 3: Common mode voltage is defined as VIH.
NOTE 4: For single-ended applications, the maximum input voltage for PCLK, nPCLK is VCC + 0.3V.
µA
853006AG
-10
800
V
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4
REV. A AUGUST 18, 2004
ICS853006
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-6
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
TABLE 5. AC CHARACTERISTICS, VCC = 0V; VEE = -2.375V TO -3.465V OR VCC = 2.375 TO 3.465V; VEE = 0V
-40°C
Symbol
Parameter
fMAX
Output Frequency
t PD
Propagation Delay; NOTE 1
tsk(o)
Output Skew; NOTE 2, 4
tsk(pp)
Par t-to-Par t Skew; NOTE 3, 4
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter section
tjit
tR/tF
Output Rise/Fall Time
Min
Typ
25°C
Max
Min
>2
340
20% to 80%
Typ
400
460
15
27
350
95
410
470
15
27
150
Max
>2
390
0.03
205
Typ
GHz
510
ps
17
30
ps
150
ps
0.03
205
95
Units
450
150
0.03
150
Min
>2
150
95
85°C
Max
150
ps
205
ps
All parameters are measured ≤ 1GHz unless otherwise noted.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
853006AG
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5
REV. A AUGUST 18, 2004
ICS853006
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-6
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
ADDITIVE PHASE JITTER
the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value,
which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a
better understanding of its effects on the desired application over
the entire time record of the signal. It is mathematically possible
to calculate an expected bit error rate given a phase noise plot.
The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the
dBc Phase Noise. This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise
power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This
ratio is expressed in decibels (dBm) or a ratio of the power in
0
-10
-20
Input/Output Additive
Phase Jitter at 155.52MHz
-30
= 0.03ps (typical)
-40
SSB PHASE NOISE dBc/HZ
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
1k
10k
100k
1M
10M
100M
OFFSET FROM CARRIER FREQUENCY (HZ)
As with most timing specifications, phase noise measurements
have issues. The primary issue relates to the limitations of the
equipment. Often the noise floor of the equipment is higher than
the noise floor of the device. This is illustrated above. The de-
853006AG
vice meets the noise floor of what is shown, but can actually be
lower. The phase noise is dependant on the input source and
measurement equipment.
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6
REV. A AUGUST 18, 2004
Integrated
Circuit
Systems, Inc.
ICS853006
LOW SKEW, 1-TO-6
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
PARAMETER MEASUREMENT INFORMATION
2V
VCC
Qx
VCC
SCOPE
nPCLK
LVPECL
V
Cross Points
PP
V
CMR
PCLK
nQx
VEE
V EE
-0.375V to -1.465V
OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
nQx
nQx
PART 1
Qx
Qx
nQy
nQy
PART 2
Qy
Qy
t sk(pp)
t sk(o)
PART-TO-PART SKEW
OUTPUT SKEW
nPCLK
80%
80%
PCLK
VSW I N G
Clock
Outputs
20%
20%
tR
nQ0:nQ5
tF
Q0:Q5
tPD
OUTPUT RISE/FALL TIME
853006AG
PROPAGATION DELAY
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7
REV. A AUGUST 18, 2004
ICS853006
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-6
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 1 shows an example of the differential input that can be
wired to accept single ended levels. The reference voltage level
VBB generated from the device is connected to the negative input.
The C1 capacitor should be located as close as possible to the
input pin.
VCC
C1
0.1u
CLK_IN
PCLK
VBB
nPCLK
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
TERMINATION
FOR
LVPECL OUTPUTS
50Ω transmission lines. Matched impedance techniques should
be used to maximize operating frequency and minimize signal
distortion. Figures 2A and 2B show two different layouts which
are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned
are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must
be used for functionality. These outputs are designed to drive
3.3V
Zo = 50Ω
125Ω
FOUT
125Ω
FIN
Zo = 50Ω
Zo = 50Ω
FOUT
50Ω
RTT =
1
Z
((VOH + VOL) / (VCC – 2)) – 2 o
VCC - 2V
Zo = 50Ω
RTT
84Ω
FIGURE 2A. LVPECL OUTPUT TERMINATION
853006AG
FIN
50Ω
84Ω
FIGURE 2B. LVPECL OUTPUT TERMINATION
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8
REV. A AUGUST 18, 2004
ICS853006
Integrated
Circuit
Systems, Inc.
TERMINATION
FOR
LOW SKEW, 1-TO-6
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
2.5V LVPECL OUTPUT
Figure 3A and Figure 3B show examples of termination for 2.5V
LVPECL driver. These terminations are equivalent to terminating 50Ω to VCC - 2V. For VCC = 2.5V, the VCC - 2V is very close to
ground level. The R3 in Figure 3B can be eliminated and the
termination is shown in Figure 3C.
2.5V
VCC=2.5V
2.5V
2.5V
VCC=2.5V
R1
250
Zo = 50 Ohm
R3
250
+
Zo = 50 Ohm
+
Zo = 50 Ohm
-
Zo = 50 Ohm
2,5V LVPECL
Driv er
-
R1
50
2,5V LVPECL
Driv er
R2
62.5
R2
50
R4
62.5
R3
18
FIGURE 3A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
FIGURE 3B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
2.5V
VCC=2.5V
Zo = 50 Ohm
+
Zo = 50 Ohm
2,5V LVPECL
Driv er
R1
50
R2
50
FIGURE 3C. 2.5V LVPECL TERMINATION EXAMPLE
853006AG
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9
REV. A AUGUST 18, 2004
ICS853006
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-6
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
LVPECL CLOCK INPUT INTERFACE
The PCLK /nPCLK accepts LVPECL, CML, SSTL and other
differential signals. Both VSWING and VOH must meet the VPP
and VCMR input requirements. Figures 4A to 4F show interface
examples for the HiPerClockS PCLK/nPCLK input driven by
the most common driver types. The input interfaces suggested
here are examples only. If the driver is from another vendor,
use their termination recommendation. Please consult with
the vendor of the driver component to confirm the driver termination requirements.
3.3V
3.3V
3.3V
3.3V
3.3V
R1
50
CML
Zo = 50 Ohm
R2
50
Zo = 50 Ohm
PCLK
R1
100
Zo = 50 Ohm
nPCLK
nPCLK
Zo = 50 Ohm
HiPerClockS
PCLK/nPCLK
HiPerClockS
PCLK/nPCLK
CML Built-In Pullup
FIGURE 4A. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY AN OPEN COLLECTOR CML DRIVER
PCLK
FIGURE 4B. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A BUILT-IN PULLUP CML DRIVER
3.3V
3.3V
3.3V
3.3V
R3
125
3.3V
R4
125
Zo = 50 Ohm
3.3V LVPECL
Zo = 50 Ohm
C1
Zo = 50 Ohm
C2
PCLK
PCLK
Zo = 50 Ohm
nPCLK
LVPECL
R1
84
VBB
nPCLK
HiPerClockS
Input
PC L K/n PC LK
R5
100 - 200
R2
84
FIGURE 4C. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A 3.3V LVPECL DRIVER
R2
50
R1
50
R6
100 - 200
FIGURE 4D. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A 3.3V LVPECL DRIVER WITH AC COUPLE
2.5V
3.3V
3.3V
3.3V
2.5V
R3
120
SSTL
Zo = 50 Ohm
R4
120
C1
LVDS
Zo = 60 Ohm
PCLK
PCLK
R5
100
Zo = 60 Ohm
nPCLK
R1
120
nPCLK
Zo = 50 Ohm
HiPerClockS
PCLK/nPCLK
PC L K /n PC L K
R1
1K
R2
120
FIGURE 4E. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY AN SSTL DRIVER
853006AG
VBB
C2
R2
1K
FIGURE 4F. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A 3.3V LVDS DRIVER
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10
REV. A AUGUST 18, 2004
ICS853006
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-6
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
SCHEMATIC EXAMPLE
Additional LVPECL driver termination approaches are shown in
the LVPECL Termination Application Note. It is recommended
at least one decoupling capacitor per power pin. The decoupling
capacitors should be physically located near the power pins.
For ICS853006, the unused output can be left floating.
Figure 5 shows a schematic example of ICS853006. The
ICS853006 input can accept various types of differential input
signal. In this example, the inputs are driven by an LVPECL drivers. For the ICS853006 LVPECL output driver, an example of
LVPECL driver termination approach is shown in this schematic.
Zo = 50
+
Zo = 50
-
R2
50
R1
50
3.3V
U1
ICS853006
R3
50
3.3V
1
2
3
4
5
6
7
8
9
10
3.3V
Zo = 50
VCC
nQ0
Q0
nQ1
Q1
nQ2
Q2
VCC
PCLK
nPCLK
VCC
Q5
nQ5
Q4
nQ4
Q3
nQ3
VCC
VEE
VBB
20
19
18
17
16
15
14
13
12
11
C5 (Optional)
0.1u
Zo = 50
+
Zo = 50
-
Zo = 50
R5
50
3.3V LVPECL
R9
50
R10
50
(U1, 1)
(U1, 13)
(U1, 8)
(U1, 20)
3.3V
C7(Optional)
0.1u
R11
50
R6
50
C2
0.1u
C1
0.1u
R4
50
C3
0.1u
C6 (Optional)
0.1u
C4
0.1u
FIGURE 5. ICS853006 LVPECL CLOCK OUTPUT BUFFER SCHEMATIC EXAMPLE
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ICS853006
LOW SKEW, 1-TO-6
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS853006.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS853006 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 115mA = 398.48mW
Power (outputs)MAX = 30.94mW/Loaded Output pair
If all outputs are loaded, the total power is 6 * 30.94mW = 185.64mW
Total Power_MAX (3.465V, with all outputs switching) = 398.48mW + 185.64mW = 584.12mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used . Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.584W * 66.6°C/W = 123.9°C. This is below the limit of 125°C
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE θJA
FOR
20-PIN TSSOP, FORCED CONVECTION
θJA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
114.5°C/W
73.2°C/W
200
500
98.0°C/W
66.6°C/W
88.0°C/W
63.5°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
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ICS853006
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LOW SKEW, 1-TO-6
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
3. Calculations and Equations.
LVPECL output driver circuit and termination are shown in Figure 6.
VCC
Q1
VOUT
RL
50
VCC - 2V
FIGURE 6. LVPECL DRIVER CIRCUIT
AND
TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage of V - 2V.
CC
•
For logic high, VOUT = V
OH_MAX
(V
CC_MAX
•
– 0.935V
OH_MAX
OL_MAX
CC_MAX
CC_MAX
) = 0.935V
-V
For logic low, VOUT = V
(V
=V
=V
CC_MAX
– 1.67V
) = 1.67V
-V
OL_MAX
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(V
OH_MAX
– (V
CC_MAX
- 2V))/R ] * (V
CC_MAX
L
-V
OH_MAX
) = [(2V - (V
CC_MAX
-V
OH_MAX
))/R ] * (V
CC_MAX
L
-V
OH_MAX
)=
[(2V - 0.935V)/50Ω] * 0.935V = 19.92mW
Pd_L = [(V
OL_MAX
– (V
CC_MAX
- 2V))/R ] * (V
L
CC_MAX
-V
OL_MAX
) = [(2V - (V
CC_MAX
-V
OL_MAX
))/R ] * (V
L
CC_MAX
-V
OL_MAX
)=
[(2V - 1.67V)/50Ω] * 1.67V = 11.02mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30.94mW
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ICS853006
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Systems, Inc.
LOW SKEW, 1-TO-6
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
RELIABILITY INFORMATION
TABLE 7. θJAVS. AIR FLOW TABLE
FOR
20 LEAD TSSOP
θ by Velocity (Linear Feet per Minute)
JA
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
0
200
500
114.5°C/W
73.2°C/W
98.0°C/W
66.6°C/W
88.0°C/W
63.5°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS853006 is: 1340
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PACKAGE OUTLINE - G SUFFIX
FOR
ICS853006
LOW SKEW, 1-TO-6
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
20 LEAD TSSOP
TABLE 8. PACKAGE DIMENSIONS
Millimeters
SYMBOL
Minimum
N
A
Maximum
20
--
1.20
A1
0.05
0.15
A2
0.80
1.05
b
0.19
0.30
c
0.09
0.20
D
6.40
6.60
E
E1
6.40 BASIC
4.30
e
4.50
0.65 BASIC
L
0.45
0.75
α
0°
8°
aaa
--
0.10
Reference Document: JEDEC Publication 95, MO-153
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ICS853006
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Systems, Inc.
LOW SKEW, 1-TO-6
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
TABLE 8. ORDERING INFORMATION
Part/Order Number
Marking
Package
Count
Temperature
ICS853006AG
ICS853006AG
20 lead TSSOP
72 per tube
-40°C to 85°C
ICS853006AGT
ICS853006AG
20 lead TSSOP on Tape and Reel
2500
-40°C to 85°C
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
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REV. A AUGUST 18, 2004