PRELIMINARY ICS854S013 LOW SKEW, DUAL, 1-TO-3 DIFFERENTIAL-TO-LVDS FANOUT BUFFER General Description Features The ICS854S013 is a low skew, high performance Dual 1-to-3 Differential-to-LVDS Fanout Buffer and HiPerClockS™ a member of the HiPerClockS™ family of High Performance Clock Solutions from IDT. The PCLKx, nPCLKx pairs can accept most standard differential input levels. The ICS854S013 is characterized to operate from a 3.3V power supply. Guaranteed output and bank skew characteristics make the ICS854S013 ideal for those clock distribution applications demanding well defined performance and repeatability. • • • Two differential LVDS output banks • • Maximum output frequency: >3GHz • • • • • • • Output skew: <25ps (typical) ICS Block Diagram Translates any single ended input signal to LVDS levels with resistor bias on nPCLKx input Bank skew: <50ps (typical) Propagation delay: TBD Additive phase jitter, RMS: 0.15ps (typical) Full 3.3V power supply 0°C to 70°C ambient operating temperature Available in both standard (RoHS 5) and lead-free (RoHS 6) packages nQA0 QA0 VDD PCLKA nPCLKA PCLKB nPCLKB VDD nQB0 QB0 QA1 nQA1 QA2 nQA2 QB0 nQB0 PCLKB Pulldown nPCLKB Pullup PCLKx, nPCLKx pairs can accept the following differential input levels: LVPECL, LVDS, CML, SSTL Pin Assignment QA0 nQA0 PCLKA Pulldown nPCLKA Pullup Two differential clock input pairs QB1 nQB1 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 QA1 nQA1 QA2 nQA2 VDD QB2 nQB2 QB1 nQB1 GND ICS854S013 QB2 nQB2 20-Lead TSSOP 6.5mm x 4.4mm x 0.925mm package body G Package Top View The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization and/or qualification. Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice. IDT™ / ICS™ LVDS FANOUT BUFFER 1 ICS854S013BG REV. A FEBRUARY 26, 2008 ICS854S013 LOW SKEW, DUAL, 1-TO-3 DIFFERENTIAL-TO-LVDS FANOUT BUFFER PRELIMINARY Table 1. Pin Descriptions Number Name Type Description 1, 2 nQA0, QA0 Output 3, 8, 16 VDD Power 4 PCLKA Input Pulldown 5 nPCLKA Input Pullup 6 PCLKB Input Pulldown Pullup Differential output pair. LVDS interface levels. Power supply pins. Non-inverting differential clock input. Inverting differential clock input. VDD/2 default when left floating. Non-inverting differential clock input. Inverting differential clock input. VDD/2 default when left floating. 7 nPCLKB Input 9, 10 nQB0, QB0 Output Differential output pair. LVDS interface levels. 11 GND Power Power supply ground. 12, 13 nQB1, QB1 Output Differential output pair. LVDS interface levels. 14, 15 nQB2, QB2 Output Differential output pair. LVDS interface levels. 17, 18 nQA2, QA2 Output Differential output pair. LVDS interface levels. 19, 20 nQA1, QA1 Output Differential output pair. LVDS interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units CIN Input Capacitance 4 pF RPULLUP Input Pullup Resistor 51 kΩ RPULLDOWN Input Pulldown Resistor 51 kΩ Table 3. Clock Input Function Table Inputs Outputs PCLKA, PCLKB nPCLKA, nPCLKB QA[0:2], QB[0:2] nQA[0:2], nQB[0:2] Input to Output Mode Polarity 0 1 LOW HIGH Differential to Differential Non-Inverting 1 0 HIGH LOW Differential to Differential Non-Inverting 0 Biased; NOTE 1 LOW HIGH Single-ended to Differential Non-Inverting 1 Biased; NOTE 1 HIGH LOW Single-ended to Differential Non-Inverting Biased; NOTE 1 0 HIGH LOW Single-ended to Differential Inverting Biased; NOTE 1 1 LOW HIGH Single-ended to Differential Inverting NOTE 1: Please refer to the Application Information Section, Wiring the Differential Input to Accept Single-ended Levels. IDT™ / ICS™ LVDS FANOUT BUFFER 2 ICS854S013BG REV. A FEBRUARY 26, 2008 ICS854S013 LOW SKEW, DUAL, 1-TO-3 DIFFERENTIAL-TO-LVDS FANOUT BUFFER PRELIMINARY Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Rating Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, IO Continuos Current Surge Current 10mA 15mA Package Thermal Impedance, θJA 87.2°C/W (0 mps) Storage Temperature, TSTG -65°C to 150°C DC Electrical Characteristics Table 4A. LVDS Power Supply DC Characteristics, VDD = 3.3V ± 5%, TA = 0°C to 70°C Symbol Parameter Test Conditions VDD Positive Supply Voltage IDD Power Supply Current Minimum Typical Maximum Units 3.135 3.3 3.465 V 135 mA Table 4B. LVPECL Differential DC Characteristics, VDD = 3.3V ± 5%, TA = 0°C to 70°C Symbol Parameter IIH Input High Current IIL Test Conditions Minimum Typical Maximum Units PCLKA, PCLKB VDD = VIN = 3.465V 150 µA nPCLKA, nPCLKB VDD = VIN = 3.465V 5 µA PCLKA, PCLKB VDD = 3.465V, VIN = 0V -5 µA nPCLKA, nPCLKB VDD = 3.465V, VIN = 0V -150 µA Input Low Current VPP Peak-to-Peak Voltage; NOTE 1 VCMR Common Mode Input Voltage; NOTE 1, 2 0.15 1.3 V GND + 0.5 VDD – 0.85 V NOTE 1: VIL should not be less than -0.3V. NOTE 2: Common mode input voltage is defined as VIH. IDT™ / ICS™ LVDS FANOUT BUFFER 3 ICS854S013BG REV. A FEBRUARY 26, 2008 ICS854S013 LOW SKEW, DUAL, 1-TO-3 DIFFERENTIAL-TO-LVDS FANOUT BUFFER PRELIMINARY Table 4C. LVDS DC Characteristics, VDD = 3.3V ± 5%, TA = 0°C to 70°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VOD Differential Output Voltage 360 mV ∆VOD VOD Magnitude Change 50 mV VOS Offset Voltage 1.35 V ∆VOS VOS Magnitude Change 50 mV Table 5. AC Characteristics, VDD = 3.3V ± 5%, TA = 0°C to 70°C Parameter Symbol fMAX Output Frequency tPD Propagation Delay; NOTE 1 TBD ps tsk(o) Output Skew; NOTE 2, 4 <25 ps tsk(b) Bank Skew; NOTE 3, 4 <50 ps tjit Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section tR / tF Output Rise/Fall Time odc Output Duty Cycle Test Conditions Minimum Typical Maximum Units >3 GHz 100MHz, Integration Range: 12kHz – 20MHz 0.15 20% to 80% 200 ps 50 % All parameters measured at 500MHz unless noted otherwise. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured from the output differential cross points. NOTE 3: Defined as skew within a bank of outputs at the same voltage and with equal load conditions. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. IDT™ / ICS™ LVDS FANOUT BUFFER 4 ICS854S013BG REV. A FEBRUARY 26, 2008 ICS854S013 LOW SKEW, DUAL, 1-TO-3 DIFFERENTIAL-TO-LVDS FANOUT BUFFER PRELIMINARY Additive Phase Jitter The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot. 0 Additive Phase Jitter @ 100MHz 12kHz to 20MHz = 0.15ps (typical) -10 -20 -30 -40 SSB Phase Noise dBc/Hz -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 1k 10k 100k 1M 10M 100M Offset from Carrier Frequency (Hz) As with most timing specifications, phase noise measurements has issues relating to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the IDT™ / ICS™ LVDS FANOUT BUFFER device. This is illustrated above. The device meets the noise floor of what is shown, but can actually be lower. The phase noise is dependent on the input source and measurement equipment. 5 ICS854S013BG REV. A FEBRUARY 26, 2008 ICS854S013 LOW SKEW, DUAL, 1-TO-3 DIFFERENTIAL-TO-LVDS FANOUT BUFFER PRELIMINARY Parameter Measurement Information VDD SCOPE VDD 3.3V±5% POWER SUPPLY + Float GND – nPCLKA, nPCLKB Qx V V Cross Points PP LVDS CMR PCLKA, PCLKB nQx GND 3.3V LVDS Output Load AC Test Circuit Differential Input Level nQXx nQx QXx Qx nQXx nQy QXx Qy tsk(o) tsk(b) Where X = A or B Bank Skew Output Skew nQAx, nQBx nPCLKA, nPCLKB QAx, QBx PCLKA, PCLKB t PW t nQAx, nQBx odc = QAx, QBx t PW x 100% t PERIOD tPD Output Duty Cycle/Pulse Width/Period Propagation Delay IDT™ / ICS™ LVDS FANOUT BUFFER PERIOD 6 ICS854S013BG REV. A FEBRUARY 26, 2008 ICS854S013 LOW SKEW, DUAL, 1-TO-3 DIFFERENTIAL-TO-LVDS FANOUT BUFFER PRELIMINARY Parameter Measurement Information, continued VDD out 80% VOD Clock Outputs DC Input 20% 20% tR LVDS tF ➤ 80% out ➤ VOS/∆ VOS ➤ Output Rise/Fall Time Offset Voltage Setup VDD LVDS 100 ➤ VOD/∆ VOD out ➤ DC Input ➤ out Differential Output Voltage Setup IDT™ / ICS™ LVDS FANOUT BUFFER 7 ICS854S013BG REV. A FEBRUARY 26, 2008 ICS854S013 LOW SKEW, DUAL, 1-TO-3 DIFFERENTIAL-TO-LVDS FANOUT BUFFER PRELIMINARY Application Information Recommendations for Unused Input and Output Pins Inputs: Outputs: PCLK/nPCLK Inputs LVDS Outputs For applications not requiring the use of a differential input, both the PCLK and nPCLK pins can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from PCLK to ground. All unused LVDS output pairs can be either left floating or terminated with 100Ω across. If they are left floating, there should be no trace attached. Wiring the Differential Input to Accept Single-Ended Levels Figure 1 shows how the differential input can be wired to accept single-ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. VDD R1 1K CLK_IN PCLKx V_REF nPCLKx C1 0.1uF R2 1K Figure 1. Single-Ended Signal Driving Differential Input IDT™ / ICS™ LVDS FANOUT BUFFER 8 ICS854S013BG REV. A FEBRUARY 26, 2008 ICS854S013 LOW SKEW, DUAL, 1-TO-3 DIFFERENTIAL-TO-LVDS FANOUT BUFFER PRELIMINARY LVPECL Clock Input Interface The PCLK /nPCLK accepts LVPECL, CML, SSTL and other differential signals. Both signals must meet the VPP and VCMR input requirements. Figures 2A to 2F show interface examples for the HiPerClockS PCLK/nPCLK input driven by the most common driver types. The input interfaces suggested here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements. 3.3V 3.3V 3.3V 3.3V 3.3V R1 50 Zo = 50Ω R2 50 Zo = 50Ω PCLK R1 100 PCLK Zo = 50Ω nPCLK Zo = 50Ω nPCLK HiPerClockS PCLK/nPCLK CML HiPerClockS PCLK/nPCLK CML Built-In Pullup Figure 2A. HiPerClockS PCLK/nPCLK Input Driven by an Open Collector CML Driver Figure 2B. HiPerClockS PCLK/nPCLK Input Driven by a Built-In Pullup CML Driver 3.3V 3.3V 3.3V 3.3V R3 125 3.3V R4 125 3.3V Zo = 50Ω R3 84 3.3V LVPECL PCLK Zo = 50Ω C1 Zo = 50Ω C2 R4 84 PCLK Zo = 50Ω nPCLK nPCLK HiPerClockS Input LVPECL R1 84 R2 84 R5 100 - 200 Figure 2C. HiPerClockS PCLK/nPCLK Input Driven by a 3.3V LVPECL Driver R6 100 - 200 R1 125 HiPerClockS PCLK/nPCLK R2 125 Figure 2D. HiPerClockS PCLK/nPCLK Input Driven by a 3.3V LVPECL Driver with AC Couple 2.5V 3.3V 3.3V 2.5V R3 120 3.3V 3.3V R4 120 R3 1k Zo = 50Ω Zo = 60Ω R4 1k C1 PCLK PCLK R5 100 Zo = 60Ω nPCLK SSTL R1 120 R2 120 nPCLK Zo = 50Ω HiPerClockS PCLK/nPCLK LVDS R1 1k Figure 2E. HiPerClockS PCLK/nPCLK Input Driven by an SSTL Driver IDT™ / ICS™ LVDS FANOUT BUFFER C2 R2 1k HiPerClockS PCLK/nPCLK Figure 2F. HiPerClockS PCLK/nPCLK Input Driven by a 3.3V LVDS Driver 9 ICS854S013BG REV. A FEBRUARY 26, 2008 ICS854S013 LOW SKEW, DUAL, 1-TO-3 DIFFERENTIAL-TO-LVDS FANOUT BUFFER PRELIMINARY 3.3V LVDS Driver Termination A general LVDS interface is shown in Figure 3. In a 100Ω differential transmission line environment, LVDS drivers require a matched load termination of 100Ω across near the receiver input. For a multiple LVDS outputs buffer, if only partial outputs are used, it is recommended to terminate the unused outputs. 3.3V 50Ω 3.3V LVDS Driver + R1 100Ω – 50Ω 100Ω Differential Transmission Line Figure 3. Typical LVDS Driver Termination IDT™ / ICS™ LVDS FANOUT BUFFER 10 ICS854S013BG REV. A FEBRUARY 26, 2008 ICS854S013 LOW SKEW, DUAL, 1-TO-3 DIFFERENTIAL-TO-LVDS FANOUT BUFFER PRELIMINARY Power Considerations This section provides information on power dissipation and junction temperature for the ICS854S013. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS854S013 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. • Power (core)MAX = VDD_MAX * IDD_MAX = 3.465V * 135mA = 467.77mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockS devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 87.2°C/W per Table 6 below. Therefore, Tj for an ambient temperature of 70°C with all outputs switching is: 70°C + 0.468W * 87.2°C/W = 110.8°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (single layer or multi-layer). Table 6. Thermal Resistance θJA for 20 Lead TSSOP, Forced Convection θJA by Velocity Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards IDT™ / ICS™ LVDS FANOUT BUFFER 0 1 2.5 87.2°C/W 82.9°C/W 80.7°C/W 11 ICS854S013BG REV. A FEBRUARY 26, 2008 ICS854S013 LOW SKEW, DUAL, 1-TO-3 DIFFERENTIAL-TO-LVDS FANOUT BUFFER PRELIMINARY Reliability Information Table 7. θJA vs. Air Flow Table for a 20 Lead TSSOP θJA by Velocity Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 87.2°C/W 82.9°C/W 80.7°C/W Transistor Count The transistor count for ICS854S013 is: 363 Package Outline and Package Dimensions Package Outline - G Suffix for 20 Lead TSSOP Table 8 Package Dimensions All Dimensions in Millimeters Symbol Minimum Maximum N 20 A 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 6.40 6.60 E 6.40 Basic E1 4.30 4.50 e 0.65 Basic L 0.45 0.75 α 0° 8° aaa 0.10 Reference Document: JEDEC Publication 95, MO-153 IDT™ / ICS™ LVDS FANOUT BUFFER 12 ICS854S013BG REV. A FEBRUARY 26, 2008 ICS854S013 LOW SKEW, DUAL, 1-TO-3 DIFFERENTIAL-TO-LVDS FANOUT BUFFER PRELIMINARY Ordering Information Table 9. Ordering Information Part/Order Number ICS854S013BG ICS854S013BGT ICS854S013BGLF ICS854S013BGLFT Marking ICS854S013BG ICS854S013BG ICS54S013BL ICS54S013BL Package 20 Lead TSSOP 20 Lead TSSOP “Lead-Free” 20 Lead TSSOP “Lead-Free” 20 Lead TSSOP Shipping Packaging Tube 2500 Tape & Reel Tube 2500 Tape & Reel Temperature 0°C to 70°C 0°C to 70°C 0°C to 70°C 0°C to 70°C NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications, such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDT™ / ICS™ LVDS FANOUT BUFFER 13 ICS854S013BG REV. A FEBRUARY 26, 2008 ICS854S013 LOW SKEW, DUAL, 1-TO-3 DIFFERENTIAL-TO-LVDS FANOUT BUFFER PRELIMINARY Innovate with IDT and accelerate your future networks. Contact: www.IDT.com www.IDT.com For Sales For Tech Support 800-345-7015 408-284-8200 Fax: 408-284-2775 [email protected] 480-763-2056 Corporate Headquarters Asia Japan Europe Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.) Integrated Device Technology IDT (S) Pte. Ltd. 1 Kallang Sector, #07-01/06 Kolam Ayer Industrial Park Singapore 349276 +65 67443356 Fax: +65 67441764 NIPPON IDT KK Sanbancho Tokyu, Bld. 7F, 8-1 Sanbancho Chiyoda-ku, Tokyo 102-0075 +81 3 3221 9822 Fax: +81 3 3221 9824 IDT Europe, Limited 321 Kingston Road Leatherhead, Surrey KT22 7TU England +44 (0) 1372 363 339 Fax: +44 (0) 1372 37885 [email protected] © 2008 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. 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