ICS8702 Integrated Circuit Systems, Inc. LOW SKEW ¸1, ¸2 CLOCK GENERATOR GENERAL DESCRIPTION FEATURES The ICS8702 is a very low skew, ÷1, ÷2 Clock Generator and a member of the HiPerClockS HiPerClockS™ family of High Performance Clock Solutions from ICS. The ICS8702 is designed to translate any differential signal levels to LVCMOS levels. True or inverting, single-ended to LVCMOS translation can be achieved with a resistor bias on the nCLK or CLK inputs, respectively. The effective fanout can be increased from 20 to 40 by utilizing the ability of the outputs to drive two series terminated lines. 20 LVCMOS outputs, 7Ω typical output impedance ,&6 Output frequency up to 250 MHz 150ps bank skew, 200ps output, 250ps multiple frequency skew, 650ps part-to-part skew Translates any differential input signal (PECL, HSTL, LVDS) to LVCMOS levels without external bias networks Translates any single-ended input signal to LVCMOS levels with a resistor bias on nCLK input The divide select inputs, DIV_SELx, control the output frequency of each bank. The outputs can be utilized in the ÷1, ÷2 or a combination of ÷1 and ÷2 modes. The bank enable inputs, BANK_EN0:1, supports enabling and disabling each bank of outputs individually. The master reset input, nMR/OE, resets the internal frequency dividers and also controls the enabling and disabling of all outputs simultaneously. Translates any single-ended input signal to inverted LVCMOS levels with a resistor bias on CLK input LVCMOS / LVTTL control inputs Bank enable logic allows unused banks to be disabled in reduced fanout applications 3.3V or mixed 3.3V input, 2.5V output operating supply modes The ICS8702 is characterized at 3.3V and mixed 3.3V input supply, and 2.5V output supply operating modes. Guaranteed bank, output, multiple frequency and part-to-part skew characteristics make the ICS8702 ideal for those clock distribution applications demanding well defined performance and repeatability. 48 lead low-profile QFP (LQFP), 7mm x 7mm x 1.4mm package body, 0.5mm package lead pitch 0°C to 70°C ambient operating temperature Other divide values available on request BLOCK DIAGRAM ÷1 1 ÷2 0 GND QB2 GND QB3 VDDO QB4 QC0 VDDO QC1 GND QC2 GND CLK nCLK PIN ASSIGNMENT QAO - QA4 QC3 VDDO QC4 QD0 VDDO QD1 GND QD2 GND QD3 VDDO QD4 DIV_SELA 1 QB0 - QB4 0 DIV_SELB 1 QC0 - QC4 0 DIV_SELC 1 QD0 - QD4 0 ICS8702 QB1 VDDO QB0 QA4 VDD0 QA3 GND QA2 GND QA1 VDDO QA0 DIV_SELA DIV_SELB CLK nCLK VDDI BANK_EN0 GND BANK_EN1 VDDI nMR/OE DIV_SELC DIV_SELD DIV_SELD nMR/OE BANK_EN0 BANK_EN1 48 47 46 45 44 43 42 41 40 39 38 37 1 36 2 35 3 34 4 33 5 32 6 31 7 30 8 29 9 28 10 27 11 26 12 25 13 14 15 16 17 18 19 20 21 22 23 24 Bank Enable Logic 48-Lead LQFP Y Package Top View 8702 www.icst.com 1 REV. A - AUGUST 7, 2000 ICS8702 Integrated Circuit Systems, Inc. LOW SKEW ¸1, ¸2 CLOCK GENERATOR TABLE 1. PIN DESCRIPTIONS Number Name Ty pe Description 2, 5, 11, 26, 32, 35, 41, 44 VDDO Pow er Output pow er supply. Connect to 3.3V or 2.5V. 7, 9, 28, 30, 37, 39, 46, 48 16, 20 GND Pow er Output pow er supply. Connect to ground. VDDI Pow er Input pow er supply. Connect to 3.3V. 18 25, 27, 29, 31, 33 34, 36, 38, 40, 42 43, 45, 47, 1, 3 4, 6, 8, 10, 12 22 GND QA0, QA1, QA2, QA3, QA4 QB0, QB1, QB2, QB3, QB4 QC0, QC1, QC2, QC3, QC4 QD0, QD1, QD2, QD3, QD4 CLK Pow er Input pow er supply. Connect to ground. Output Bank A outputs. 7Ω typical output impedance. Output Bank B outputs. 7Ω typical output impedance. Output Bank C outputs. 7Ω typical output impedance. Output Bank D outputs. 7Ω typical output impedance. 21 nCLK Input Pulldow n Input Pullup Non-inverting differential clock input. Accepts any differential levels. Inverting differential clock input. Accepts any differential levels. 13 DIV_SELD Input Pullup Controls frequency division for bank D outputs. LVCMOS interface levels. 14 DIV_SELC Input Pullup Controls frequency division for bank C outputs. LVCMOS interface levels. 23 DIV_SELB Input Pullup Controls frequency division for bank B outputs. LVCMOS interface levels. 24 DIV_SELA BANK_EN1, BANK_EN0 Input Pullup Controls frequency division for bank A outputs. LVCMOS interface levels. Input Pullup Enables and disables outputs by banks. LVCMOS interface levels. Input Pullup Asynchronous master reset. Resets clock dividers. Enables and disables all outputs. LVCMOS interface levels. 17, 19 15 nMR/OE TABLE 2. PIN CHARACTERISTICS Sy mbol Parameter CIN Input Capacitance Test Conditions Minimum Ty pical Maximum Units RPULLUP Input Pullup Resistor 51 KΩ RPULLDOWN Input Pulldow n Resistor 51 KΩ pF CPD Pow er Dissipation Capacitance (per output) ROUT Output Impedance VDDI, VDDO = 3.465V pF VDDI = 3.465V, VDDO = 2.625V pF Ω 7 TABLE 3A. CONTROL INPUTS FUNCTION TABLE Inputs Outputs nMR/OE BANK_EN1 BANK_EN0 DIV_SELx QA0 - QA4 QB0 - QB4 QC0 - QC4 QD0 - QD4 Qx frequency 0 X X X Hi Z Hi Z Hi Z Hi Z zero 1 0 0 0 Active Hi Z Hi Z Hi Z fIN/2 1 1 0 0 Active Active Hi Z Hi Z fIN/2 1 0 1 0 Active Active Active Hi Z fIN/2 8702 1 1 1 0 Active Active Active Active fIN/2 1 0 0 1 Active Hi Z Hi Z Hi Z fIN 1 1 0 1 Active Active Hi Z Hi Z fIN 1 0 1 1 Active Active Active Hi Z fIN 1 1 1 1 Active Active Active Active fIN www.icst.com 2 REV. A - AUGUST 7, 2000 ICS8702 Integrated Circuit Systems, Inc. LOW SKEW ¸1, ¸2 CLOCK GENERATOR TABLE 3B. CLOCK INPUTS FUNCTION TABLE Inputs Outputs nMR/OE CLK nCLK Qx0 thru Qx4 1 0 1 LOW Input to Output Mode Polarity Differential to Single Ended Non Inverting 1 1 0 HIGH Differential to Single Ended Non Inverting 1 0 Biased; NOTE 1 LOW Single Ended to Single Ended Non Inverting 1 1 Biased; NOTE 1 HIGH Single Ended to Single Ended Non Inverting 1 Biased; NOTE 1 0 HIGH Single Ended to Single Ended Inverting 1 Biased; NOTE 1 1 LOW Single Ended to Single Ended Inverting NOTE 1: Single ended input use requires that one of the differential inputs be biased. The voltage at the biased input sets the sw itch point for the single ended input. For LVCMOS input levels the recommended input bias netw ork is a resistor to VDDI, a resistor of equal value to ground and a 0.1µF capacitor from the input to ground. The resulting sw itch point is approximately VDD/2 ± 300mV. ABSOLUTE MAXIMUM RATINGS Supply Voltage 4.6V Inputs Outputs Ambient Operating Temperature Storage Temperature -0.5V to VDD + 0.5V -0.5V to VDDO + 0.5V 0°C to 70°C -65°C to 150°C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of product at these condition or any conditions beyond those listed in the DC Electrical Characteristics or AC Electrical Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. 8702 www.icst.com 3 REV. A - AUGUST 7, 2000 ICS8702 Integrated Circuit Systems, Inc. LOW SKEW ¸1, ¸2 CLOCK GENERATOR TABLE 4A. DC ELECTRICAL CHARACTERISTICS, VDDI=VDDO=3.3V±5%, TA=0°C TO 70°C Sy mbol Parameter Test Conditions Minimum Ty pical Maximum Units VDDI Input Pow er Supply Voltage 3.135 3.3 3.465 V VDDO Output Pow er Supply Voltage 3.135 3.3 3.465 V VIH Input High Voltage All except CLK, nCLK VDDI = 3.465V 2 3.8 V VIL Input Low Voltage All except CLK, nCLK; VDDI = 3.135V -0.3 0.8 V VPP Peak-to-Peak Input Voltage CLK, nCLK 0.15 1.3 V VCM R Common M ode Input Voltage; NOTE 1 CLK, nCLK LVPECL Levels 1.8 2.4 V DCM , HSTL, LVDS, SSTL Levels 0.31 1.3 V IIH Input High Current IIL Input Low Current All except CLK VDDI = VIN = 3.465V 5 µA CLK VDDI = VIN = 3.465V 150 µA All except CLK CLK VDDI = 3.465, VIN = 0V -150 µA VDDI = 3.465, VIN = 0 -5 µA VDDI = VIH = 3.465V 70 mA VIL = 0V VDDI = VDDO = 3.135V 2.6 V VOH Output High Voltage IOH = -36mA VDDI = VDDO = 3.135V VOL Output Low Voltage 0.5 V IOL = 36mA NOTE 1: Common mode input voltage for LVPECL is defined as the minimum VIH. The LVPECL values noted in Table 4A are for VCCI = 3.3V. VCM R for LVPECL w ill vary 1:1 w ith VCCI. Common mode input voltage for DCM , HSTL, LVDS and SSTL is defined as the crossover voltage. See Figure 1. IDD Quiescent Pow er Supply Current TABLE 5A. AC ELECTRICAL CHARACTERISTICS, VDDI=VDDO=3.3V±5%, TA=0°C TO 70°C Sy mbol Parameter Test Conditions Minimum Ty pical Maximum Units fMAX Maximum Input Frequency 250 MHz tpLH Propagation Delay, Low -to-High 0MHZ < f ≤ 200MHz 2.2 3.5 ns tpHL Propagation Delay, High-to-Low 0MHZ < f ≤ 200MHz 2.2 3.5 ns tsk(b) Bank Skew ; NOTE 2 Measured on rising edge at VDDO/2 150 ps tsk(o) Output Skew ; NOTE 3 Measured on rising edge at VDDO/2 200 ps tsk(ω) Multiple Frequency Skew ; NOTE 4 Measured on rising edge at VDDO/2 250 ps tsk(pp) Part to Part Skew ; NOTE 5 Measured on rising edge at VDDO/2 650 ps tR Output Rise Time; NOTE 6 30% to 70% 280 850 ps tF Output Fall Time; NOTE 6 30% to 70% 280 850 ps tPW Output Pulse Width tEN tDIS NOTE 1: NOTE 2: NOTE 3: NOTE 4: NOTE 5: NOTE 6: 8702 Output Enable Time; NOTE 6 0MHZ < f < 200MHz f = 200MHz f = 10MHz tCY CLE/2 - 0.5 2 tCY CLE/2 2.5 tCY CLE/2 + 0.5 3 ns 6 ns ns Output Disable Time; NOTE 6 f = 10MHz 6 ns All parameters measured at fIN = 200MHz and VPP = 300mV unless noted otherw ise. All outputs terminated w ith 50Ω to VDDO/2. Defined as skew w ithin a bank of outputs at the same supply voltages and w ith equal load conditions. Defined as skew across banks of outputs at the same supply voltages and w ith equal load conditions. Defined as skew across banks of outputs operating at different frequency w ith the same supply voltages and equal load conditions. Defined as the skew at different outputs on different devices operating at the same supply voltages and w ith equal load conditions. These parameters are guaranteed by characterization. Not tested in production. www.icst.com 4 REV. A - AUGUST 7, 2000 ICS8702 Integrated Circuit Systems, Inc. LOW SKEW ¸1, ¸2 CLOCK GENERATOR TABLE 4B. DC ELECTRICAL CHARACTERISTICS, VDDI=3.3V±5%, VDDO=2.5V±5%, TA=0°C TO 70°C Sy mbol Parameter VDDI VDDO Test Conditions Minimum Ty pical Maximum Units Input Pow er Supply Voltage 3.135 3.3 3.465 V Output Pow er Supply Voltage 2.375 2.5 2.625 V VIH Input High Voltage All except CLK, nCLK VDDI = 3.465V 2 3.8 V VIL Input Low Voltage Peak-to-Peak Input Voltage Common Mode Input Voltage; NOTE 1 All except CLK, nCLK VDDI = 3.135V -0.3 0.8 V 0.15 1.3 LVPECL Levels 1.8 2.4 DCM, HSTL, LVDS, SSTL Levels 0.31 1.3 VPP VCMR IIH Input High Current IIL Input Low Current CLK, nCLK CLK, nCLK All except CLK VDDI = VIN = 3.465V 5 µA CLK VDDI = VIN = 3.465V 150 µA All except CLK VDDI = 3.465V, VIN = 0V -150 µA CLK VDDI = 3.465V, VIN = 0V -5 µA VDDI = VIH = 3.465V 70 mA VIL = 0V VDDI = 3.135V, VDDO = 2.375V 1.9 V VOH Output High Voltage IOH = -27mA VDDI = 3.135V, VDDO = 2.375V 0.5 V VOL Output Low Voltage IOL = 27mA NOTE 1: Common mode input voltage for LVPECL is defined as the minimum VIH. The LVPECL values noted in Table 4B are for VCCI = 3.3V. VCMR for LVPECL w ill vary 1:1 w ith VCCI. Common mode input voltage for DCM, HSTL, LVDS and SSTL is defined as the crossover voltage. See Figure 1. IDD Quiescent Pow er Supply Current TABLE 5B. AC ELECTRICAL CHARACTERISTICS, VDDI=3.3V±5%, VDDO=2.5V±5%, TA=0°C TO 70°C Sy mbol Parameter Test Conditions Minimum Ty pical Maximum Units fMAX Maximum Input Frequency 250 MHz tpLH Propagation Delay, Low -to-High 0MHZ < f ≤ 200MHz 2.3 3.6 ns tpHL Propagation Delay, High-to-Low 0MHZ < f ≤ 200MHz 2.3 3.6 ns tsk(b) Bank Skew ; NOTE 2 Measured on rising edge at VDDO/2 150 ps tsk(o) Output Skew ; NOTE 3 Measured on rising edge at VDDO/2 200 ps tsk(ω) Multiple Frequency Skew ; NOTE 4 Measured on rising edge at VDDO/2 250 ps tsk(pp) Part to Part Skew ; NOTE 5 Measured on rising edge at VDDO/2 700 ps tR Output Rise Time; NOTE 6 30% to 70% 280 850 ps tF Output Fall Time; NOTE 6 30% to 70% 280 850 ps tPW Output Pulse Width tEN tDIS NOTE 1: NOTE 2: NOTE 3: NOTE 4: NOTE 5: NOTE 6: 8702 Output Enable Time; NOTE 6 0MHZ < f < 200MHz f = 200MHz f = 10MHz tCY CLE/2 - 0.5 2 tCY CLE/2 2.5 tCY CLE/2 + 0.5 3 ns 6 ns ns Output Disable Time; NOTE 6 f = 10MHz 6 ns All parameters measured at fIN = 200MHz and VPP = 300mV unless noted otherw ise. All outputs terminated w ith 50Ω to VDDO/2. Defined as skew w ithin a bank of outputs at the same supply voltages and w ith equal load conditions. Defined as skew across banks of outputs at the same supply voltages and w ith equal load conditions. Defined as skew across banks of outputs operating at different frequency w ith the same supply voltages and equal load conditions. Defined as the skew at different outputs on different devices operating at the same supply voltages and w ith equal load conditions. These parameters are guaranteed by characterization. Not tested in production. www.icst.com 5 REV. A - AUGUST 7, 2000 ICS8702 Integrated Circuit Systems, Inc. LOW SKEW ¸1, ¸2 CLOCK GENERATOR FIGURE 1A, 1B - TIMING DIAGRAMS CLK nCLK Qx, ÷1 Qx, ÷2 FIGURE 1A - ACTIVE, ÷1, ÷2 nMR/OE CLK n CLK Qx, ÷1 Qx, ÷2 High Impedance Active FIGURE 1B - RESET TO ACTIVE, ÷1, ÷2 8702 www.icst.com 6 REV. A - AUGUST 7, 2000 ICS8702 Integrated Circuit Systems, Inc. LOW SKEW ¸1, ¸2 CLOCK GENERATOR FIGURE 2A, 2B, 2C - INPUT CLOCK WAVEFORMS VDDI CLK CROSS POINTS VPP VCMR nCLK GND FIGURE 2A - DCM, HSTL, LVDS, SSTL DIFFERENTIAL INPUT LEVELS VDDI CLK CROSS POINTS VPP VCMR nCLK GND FIGURE 2B - LVPECL DIFFERENTIAL INPUT LEVEL VDDI CLK or nCLK GND FIGURE 2C- LVCMOS AND LVTTL SINGLE ENDED INPUT LEVEL 8702 www.icst.com 7 REV. A - AUGUST 7, 2000 ICS8702 Integrated Circuit Systems, Inc. LOW SKEW ¸1, ¸2 CLOCK GENERATOR FIGURE 3A, 3B - TIMING WAVEFORMS CLK Vpp nCLK tPHL tPLH Q VDDO/2 FIGURE 3A - PROPAGATION DELAYS fin = 200MHz, Vpp = 300mV, tr = tf = 200ps nMR/OE, BANK_ENx 3.3V BANK_ENx 0V tPHZ Q VOH tPZH VOH - 300mV VDDO/2 tPLZ tPZL VDDO/2 Q VOL VOL + 300mV FIGURE 3B - DISABLE AND ENABLE TIMES fin = 10MHz, Vamp = 3.3V, tr = tf = 600ps 8702 www.icst.com 8 REV. A - AUGUST 7, 2000 ICS8702 Integrated Circuit Systems, Inc. LOW SKEW ¸1, ¸2 CLOCK GENERATOR FIGURE 4A, 4B- SKEW DEFINITIONS & WAVEFORMS Bank Skew - Skew between outputs within a bank. Outputs operating at the same temperature, supply voltages and with equal load conditions. CLK Vpp nCLK ○ ○ Qx0 VDDO/2 ○ ○ ○ ○ ○ VDDO/2 ○ tsk(b) tsk(b) Qx4 VDDO/2 VDDO/2 FIGURE 4A - BANK SKEW fin = 200MHz, Vpp = 300mV, tr = tf = 200ps Output Skew - Skew between outputs of any bank. Outputs operating at the same temperature, supply voltages and with equal load conditions. CLK Vpp nCLK QA0 - QA4 VDDO/2 VDDO/2 tsk(o) QB0 - QB4 QC0 - QC4 QD0 - QD4 tsk(o) VDDO/2 VDDO/2 FIGURE 4B - OUTPUT SKEW fin = 200MHz, Vpp = 300mV, tr = tf = 200ps 8702 www.icst.com 9 REV. A - AUGUST 7, 2000 ICS8702 Integrated Circuit Systems, Inc. LOW SKEW ¸1, ¸2 CLOCK GENERATOR FIGURE 4C, 4D- SKEW DEFINITIONS & WAVEFORMS Multiple Frequency Skew - Skew between banks of outputs operating at different frequencies. Outputs operating at the same temperature, supply voltages and with equal load conditions. CLK Vpp nCLK QA0 - QA4, QB0 - QB4, QC0 - QC4, or QD0 - QD4 VDDO/2 VDDO/2 in ÷1 tsk(w) tsk(w) VDDO/2 QA0 - QA4, QB0 - QB4, QC0 - QC4, or QD0 - QD4 in ÷2 VDDO/2 FIGURE 4C - MULTIPLE FREQUENCY SKEW fin = 200MHz, Vpp = 300mV, tr = tf = 200ps Part to Part Skew - Skew between outputs of any bank on different parts. Outputs operating at the same temperature, supply voltages and with equal load conditions. CLK Vpp nCLK PART 1 QA0 - QA4 QB0 - QB4 QC0 - QC4 QD0 - QD4 VDDO/2 VDDO/2 tsk(p) PART 2 QA0 - QA4 QB0 - QB4 QC0 - QC4 QD0 - QD4 tsk(p) VDDO/2 VDDO/2 FIGURE 4B - OUTPUT SKEW fin = 200MHz, Vpp = 300mV, tr = tf = 200ps 8702 www.icst.com 10 REV. A - AUGUST 7, 2000 ICS8702 Integrated Circuit Systems, Inc. LOW SKEW ¸1, ¸2 CLOCK GENERATOR PACKAGE OUTLINE AND DIMENSIONS - Y SUFFIX e /2 NOTE 4 D NOTE 5, 7 D1 D/2 NOTE 3 -D- -A, B, OR -D- D1/2 b NOTE 3 -B- NOTE 3 -A- E1 -A, B, OR -D- N O T E 4 E/2 N/4 T IPS 0.20 C A-B D 4X E N O T E 5, 7 e E1/2 SEE DETAIL “A” 8 PLACES 11 / 13° A -H- NOT E 2 / / 0.10 C ccc -CSEE DETAIL “B” NOTE 9 ddd M C A-B S D S 0.09 / 0.20 S Y M B O L WIT H LEAD FINISH b NOTES: 1. ALL DIMENSIONS AND TOLERANCING CONFORM TO ANSI Y14.5-1982 2. DATUM PLANE -H- LOCATED AT MOLD PARTING LINE AND COINCIDENT WITH LEAD, WHERE LEAD EXITS PLASTIC BODY AT BOTTOM OF PARTING LINE. 3. DATUMS A-B AND -D- TO BE DETERMINED AT CENTERLINE BETWEEN LEADS WHERE LEADS EXIT PLASTIC AT DATUM PLANE -H- . 4. TO BE DETERMINED AT SEATING PLACE -C- . 5. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD PROTRUSION. 6. “N” IS THE TOTAL NUMBER OF TERMINALS. 7. THESE DIMENSIONS TO BE DETEREMINED AT DATUM PLANE -H-. 8. PACKAGE TOP DIMENSIONS ARE SMALLER THAN BOTTOM DIMENSIONS AND TOP OF PACKAGE WILL NOT OVERHANG BOTTOM OF PACKAGE. 9. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08mm TOTAL IN EXCESS OF THE b DIMENSION AT MAXIMUM MATERIAL CONDITION. 10. CONTROLLING DIMENSION: MILLIMETER. 11. THIS OUTLINE CONFORMS TO JEDEC PUBLIBCATION 95 REGISTRATION MS-026, VARIATION BBC. 12. A1 IS DEFINED AS THE DISTANCE FROM THE SEATING PLANE TO THE LOWEST POINT OF THE PACKAGE. 0.09 / 0.16 JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS BBC MIN. NOM. A b1 BASE METAL 0° MIN. - 0.05 S A2 0.08/0.20 R. DATUM PLANE -H- 0.05 A2 1.35 0.08 R. MIN. 0.20 MIN. L 1.00 REF. 8702 www.icst.com 11 12 1.45 D 9.00 BSC. 4 7.00 BSC. 7, 8 E 9.00 BSC. 4 E1 7.00 BSC. 7, 8 0.45 0.60 0.75 48 N 0° - 7 ° 0.15 1.40 D1 e A1 MAX. 1.60 A1 L 0.25 GAUGE PLANE N O T E 0.5 BSC. b 0.17 0.22 0.27 b1 0.17 0.20 0.23 ccc 0.08 ddd 0.08 9 REV. A - AUGUST 7, 2000 ICS8702 Integrated Circuit Systems, Inc. LOW SKEW ¸1, ¸2 CLOCK GENERATOR ORDERING INFORMATION Part/Order Number Marking Package Count ICS8702BY ICS8702BY 48 Lead LQFP 250 per tray Temperature 0°C to 70°C ICS8702BY T ICS8702BY 48 Lead LQFP on Tape and Reel 2000 0°C to 70°C While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 8702 www.icst.com 12 REV. A - AUGUST 7, 2000