TECHNICAL DATA IN74HC623 Octal 3-State Noninverting Bus Transceiver High-Performance Silicon-Gate CMOS The IN74HC623 is identical in pinout to the LS/ALS623. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs. The IN74HC623 is a 3-state noninverting transceiver that is used for 2-way communication between data buses. Two separate enables are available. The enable for bus A to B is active-high, the enable for bus B to A is active-low. • Outputs Directly Interface to CMOS, NMOS, and TTL • Operating Voltage Range: 2.0 to 6.0 V • Low Input Current: 1.0 µA • High Noise Immunity Characteristic of CMOS Devices ORDERING INFORMATION IN74HC623N Plastic IN74HC623DW SOIC TA = -55° to 125° C for all packages PIN ASSIGNMENT LOGIC DIAGRAM FUNCTION TABLE Control Inputs PIN 20=VCC PIN 10 = GND 446 Output Enable Direction Operation L L Data Transmitted from Bus B to Bus A L H Data Transmitted from Bus A to Bus B H L Buses Isolated L H (High Impedance State) IN74HC623 MAXIMUM RATINGS* Symbol Parameter Value Unit -0.5 to +7.0 V VCC DC Supply Voltage (Referenced to GND) VIN DC Input Voltage (Referenced to GND) -1.5 to VCC +1.5 V DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V DC Input Current, per Pin ±20 mA IOUT DC Output Current, per Pin ±35 mA ICC DC Supply Current, VCC and GND Pins ±75 mA PD Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ 750 500 mW -65 to +150 °C 260 °C VOUT IIN Tstg TL Storage Temperature Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C SOIC Package: : - 7 mW/°C from 65° to 125°C RECOMMENDED OPERATING CONDITIONS Symbol VCC VIN, VOUT Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) TA Operating Temperature, All Package Types tr, tf Input Rise and Fall Time (Figure 1) VCC =2.0 V VCC =4.5 V VCC =6.0 V Min Max Unit 2.0 6.0 V 0 VCC V -55 +125 °C 0 0 0 1000 500 400 ns This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND≤(VIN or VOUT)≤VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. I/O pins must be connected to a properly terminated line or bus. 447 IN74HC623 DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND) VCC V 25 °C to -55°C ≤85 °C ≤125 °C Unit VOUT=0.1 V or VCC-0.1 V IOUT≤ 20 µA 2.0 4.5 6.0 1.5 3.15 4.2 1.5 3.15 4.2 1.5 3.15 4.2 V Maximum Low Level Input Voltage VOUT=0.1 V or VCC-0.1 V IOUT ≤ 20 µA 2.0 4.5 6.0 0.5 1.35 1.8 0.5 1.35 1.8 0.5 1.35 1.8 V Minimum High-Level Output Voltage VIN=VIH or VIL IOUT ≤ 20 µA 2.0 4.5 6.0 1.9 4.4 5.9 1.9 4.4 5.9 1.9 4.4 5.9 V 4.5 6.0 3.98 5.48 3.84 5.34 3.7 5.2 2.0 4.5 6.0 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 4.5 6.0 0.26 0.26 0.33 0.33 0.4 0.4 Symbol Parameter VIH Minimum High-Level Input Voltage VIL VOH Test Conditions VIN=VIH or VIL IOUT ≤ 6.0 mA IOUT ≤ 7.8 mA VOL Maximum Low-Level Output Voltage VIN= VIL or VIH IOUT ≤ 20 µA VIN= VIL or VIH IOUT ≤ 6.0 mA IOUT ≤ 7.8 mA 448 Guaranteed Limit V IIN Maximum Input Leakage Current VIN=VCC or GND, Pin 1 or 19 6.0 ±0.1 ±1.0 ±1.0 µA IOZ Maximum ThreeState Leakage Current Output in High-Impedance State VIN= VIL or VIH VOUT=VCC or GND, I/O Pins 6.0 ±0.5 ±5.0 ±10 µA ICC Maximum Quiescent Supply Current (per Package) VIN=VCC or GND IOUT=0µA 6.0 8.0 80 160 µA IN74HC623 AC ELECTRICAL CHARACTERISTICS(CL=50pF,Input tr=tf=6.0 ns) Guaranteed Limit VCC Symbol Parameter V 25 °C to -55°C ≤85°C ≤125°C Unit tPLH, tPHL Maximum Propagation Delay, A to B , B to A (Figures 1 and 3) 2.0 4.5 6.0 100 20 17 125 25 21 150 30 26 ns tPLZ, tPHZ Maximum Propagation Delay , Direction or Output Enable to A or B (Figures 2 and 4) 2.0 4.5 6.0 150 30 26 190 38 33 225 45 38 ns tPZL, tPZH Maximum Propagation Delay , Direction or Output Enable to A or B (Figures 2 and 4) 2.0 4.5 6.0 150 30 26 190 38 33 225 45 38 ns tTLH, tTHL Maximum Output Transition Time, Any Output (Figures 1 and 3) 2.0 4.5 6.0 60 12 10 75 15 13 90 18 15 ns CIN Maximum Input Capacitance (Pin 1 or Pin 19) - 10 10 10 pF Maximum Three-State I/O Capacitance (I/O in High-Impedance State) - 15 15 15 pF COUT Power Dissipation Capacitance (Per Transceiver Channel) CPD Used to determine the no-load dynamic power consumption: PD=CPDVCC2f+ICCVCC Figure 1. Switching Waveforms Typical @25°C,VCC=5.0 V 40 pF Figure 2. Switching Waveforms 449 IN74HC623 Figure 3. Test Circuit Figure 4. Test Circuit EXPANDED LOGIC DIAGRAM 450