IRF IRF6714MPBF

PD - 96130
IRF6714MPbF
IRF6714MTRPbF
DirectFET™ Power MOSFET ‚
l
l
l
l
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Typical values (unless otherwise specified)
RoHs Compliant Containing No Lead and Bromide 
VDSS
VGS
RDS(on)
RDS(on)
Low Profile (<0.6 mm)
25V max ±20V max 1.6mΩ@ 10V 2.6mΩ@ 4.5V
Dual Sided Cooling Compatible 
Ultra Low Package Inductance
Qg tot Qgd
Qgs2
Qrr
Qoss Vgs(th)
Optimized for High Frequency Switching 
29nC
8.3nC 4.1nC
36nC
23nC
1.9V
Ideal for CPU Core DC-DC Converters
Optimized for Sync. FET socket of Sync. Buck Converter
Low Conduction and Switching Losses
Compatible with existing Surface Mount Techniques 
100% Rg tested
MX
DirectFET™ ISOMETRIC
Applicable DirectFET Outline and Substrate Outline (see p.7,8 for details)
SQ
SX
ST
MX
MQ
MT
MP
Description
The IRF6714MPbF combines the latest HEXFET® Power MOSFET Silicon technology with the advanced DirectFET TM packaging to achieve
the lowest on-state resistance in a package that has the footprint of a SO-8 and only 0.6 mm profile. The DirectFET package is compatible
with existing layout geometries used in power applications, PCB assembly equipment and vapor phase, infra-red or convection soldering
techniques, when application note AN-1035 is followed regarding the manufacturing methods and processes. The DirectFET package allows
dual sided cooling to maximize thermal transfer in power systems, improving previous best thermal resistance by 80%.
The IRF6714MPbF balances both low resistance and low charge along with ultra low package inductance to reduce both conduction and
switching losses. The reduced total losses make this product ideal for high efficiency DC-DC converters that power the latest generation of
processors operating at higher frequencies. The IRF6714MPbF has been optimized for parameters that are critical in synchronous buck
including Rds(on), gate charge and Cdv/dt-induced turn on immunity. The IRF6714MPbF offers particularly low Rds(on) and high Cdv/dt
immunity for synchronous FET applications.
Absolute Maximum Ratings
Max.
Parameter
VDS
Drain-to-Source Voltage
Gate-to-Source Voltage
Continuous Drain Current, VGS @ 10V
Continuous Drain Current, VGS @ 10V
Continuous Drain Current, VGS @ 10V
VGS
ID @ TA = 25°C
ID @ TA = 70°C
ID @ TC = 25°C
IDM
EAS
IAR
g
Pulsed Drain Current
Single Pulse Avalanche Energy
Avalanche Current
ID = 29A
4
3
T J = 125°C
2
1
T J = 25°C
0
2
4
6
8
10
12
14
16
18
20
VGS, Gate -to -Source Voltage (V)
Fig 1. Typical On-Resistance Vs. Gate Voltage
Notes:
 Click on this section to link to the appropriate technical paper.
‚ Click on this section to link to the DirectFET Website.
ƒ Surface mounted on 1 in. square Cu board, steady state.
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e
e
f
VGS, Gate-to-Source Voltage (V)
Typical RDS(on) (mΩ)
5
Units
25
±20
29
23
166
234
175
23
V
A
mJ
A
14
ID= 23A
12
VDS= 20V
VDS= 13V
10
8
6
4
2
0
0
10
20
30
40
50
60
70
80
QG Total Gate Charge (nC)
Fig 2. Typical Total Gate Charge vs Gate-to-Source Voltage
„ TC measured with thermocouple mounted to top (Drain) of part.
… Repetitive rating; pulse width limited by max. junction temperature.
† Starting TJ = 25°C, L = 0.651mH, RG = 25Ω, IAS = 23A.
1
09/21/07
IRF6714MPbF
Parameter
Min.
Drain-to-Source Breakdown Voltage
25
–––
–––
∆ΒVDSS/∆TJ
RDS(on)
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
–––
–––
18
1.6
–––
2.1
2.6
1.9
3.4
2.4
VGS = 0V, ID = 250µA
mV/°C Reference to 25°C, ID = 1mA
VGS = 10V, ID = 29A
mΩ
VGS = 4.5V, ID = 23A
V
VGS(th)
Gate Threshold Voltage
–––
1.4
∆VGS(th)/∆TJ
IDSS
Gate Threshold Voltage Coefficient
Drain-to-Source Leakage Current
–––
–––
-6.5
–––
–––
1.0
IGSS
Gate-to-Source Forward Leakage
–––
–––
–––
–––
150
100
Gate-to-Source Reverse Leakage
Forward Transconductance
–––
122
–––
–––
-100
–––
Total Gate Charge
Pre-Vth Gate-to-Source Charge
–––
–––
29
9.0
44
–––
Post-Vth Gate-to-Source Charge
Gate-to-Drain Charge
–––
–––
4.1
8.3
–––
–––
Gate Charge Overdrive
Switch Charge (Qgs2 + Qgd)
–––
–––
8.1
12
–––
–––
Output Charge
Gate Resistance
–––
–––
23
1.2
–––
2.2
Turn-On Delay Time
Rise Time
–––
–––
18
26
–––
–––
Turn-Off Delay Time
Fall Time
–––
–––
13
9.6
–––
–––
Input Capacitance
Output Capacitance
–––
–––
3890
1110
–––
–––
Reverse Transfer Capacitance
–––
490
–––
Min.
Typ. Max. Units
gfs
Qg
Qgs1
Qgs2
Qgd
Qgodr
Qsw
Qoss
RG
td(on)
tr
td(off)
tf
Ciss
Coss
Crss
Conditions
Typ. Max. Units
BVDSS
V
mV/°C
i
i
VDS = VGS, ID = 100µA
µA
VDS = 20V, VGS = 0V
VDS = 20V, VGS = 0V, TJ = 125°C
nA
VGS = 20V
VGS = -20V
S
VDS = 13V, ID = 23A
nC
VDS = 13V
VGS = 4.5V
ID = 23A
See Fig. 15
nC
VDS = 16V, VGS = 0V
Ω
i
VDD = 13V, VGS = 4.5V
ns
ID = 23A
RG = 1.8Ω, RD = 0.54Ω
See Fig. 17
VGS = 0V
pF
VDS = 13V
ƒ = 1.0MHz
Diode Characteristics
Parameter
IS
Continuous Source Current
ISM
(Body Diode)
Pulsed Source Current
VSD
trr
Qrr
g
(Body Diode)
Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
–––
–––
Conditions
MOSFET symbol
112
A
showing the
integral reverse
p-n junction diode.
TJ = 25°C, IS = 23A, VGS = 0V
TJ = 25°C, IF = 23A
–––
–––
234
–––
–––
1.0
V
–––
–––
26
36
39
54
ns
nC
di/dt = 200A/µs
i
i
Notes:
‡ Pulse width ≤ 400µs; duty cycle ≤ 2%
2
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IRF6714MPbF
Absolute Maximum Ratings
c
c
f
PD @TA = 25°C
PD @TA = 70°C
PD @TC = 25°C
TP
TJ
TSTG
Max.
Parameter
Units
2.8
1.8
89
270
-40 to + 150
Power Dissipation
Power Dissipation
Power Dissipation
Peak Soldering Temperature
Operating Junction and
Storage Temperature Range
W
°C
Thermal Resistance
Parameter
cg
dg
eg
fg
RθJA
RθJA
RθJA
RθJC
RθJ-PCB
Junction-to-Ambient
Junction-to-Ambient
Junction-to-Ambient
Junction-to-Case
Junction-to-PCB Mounted
Linear Derating Factor
c
Typ.
Max.
Units
–––
12.5
20
–––
1.0
45
–––
–––
1.4
–––
°C/W
0.022
W/°C
Thermal Response ( Z thJA )
100
10
D = 0.50
0.20
0.10
0.05
1
0.02
0.01
τJ
0.1
R1
R1
τJ
τ1
R2
R2
R3
R3
τA
τ2
τ1
τ3
τ2
τ3
τ4
τ4
Ci= τi/Ri
Ci= τi/Ri
0.01
0.001
1E-006
0.0001
τA
1.3634
τi (sec)
0.000202
7.8361
0.096325
19.8534
1.3861
15.9581
51
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthja + Tc
SINGLE PULSE
( THERMAL RESPONSE )
1E-005
Ri (°C/W)
R4
R4
0.001
0.01
0.1
1
10
100
1000
t1 , Rectangular Pulse Duration (sec)
Fig 3. Maximum Effective Transient Thermal Impedance, Junction-to-Ambient ƒ
Notes:
ˆ Used double sided cooling , mounting pad with large heatsink.
‰ Mounted on minimum footprint full size board with metalized
Š Rθ is measured at TJ of approximately 90°C.
back and with small clip heatsink.
ƒ Surface mounted on 1 in. square Cu
(still air).
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‰ Mounted to a PCB with
small clip heatsink (still air)
‰ Mounted on minimum
footprint full size board with
metalized back and with small
clip heatsink (still air)
3
IRF6714MPbF
1000
1000
ID, Drain-to-Source Current (A)
100
BOTTOM
10
VGS
10.0V
5.00V
4.50V
4.00V
3.50V
3.25V
3.00V
2.75V
TOP
ID, Drain-to-Source Current (A)
TOP
100
1
2.75V
0.1
≤60µs PULSE WIDTH
BOTTOM
10
2.75V
≤60µs PULSE WIDTH
Tj = 25°C
Tj = 150°C
0.01
1
0.1
1
10
100
1000
0.1
VDS, Drain-to-Source Voltage (V)
Typical RDS(on) (Normalized)
ID, Drain-to-Source Current (A)
T J = 150°C
T J = 25°C
T J = -40°C
1
0.1
3
4
1.5
V GS = 10V
V GS = 4.5V
1.0
0.5
5
-60 -40 -20 0
Fig 7. Normalized On-Resistance vs. Temperature
Fig 6. Typical Transfer Characteristics
20
VGS = 0V,
f = 1 MHZ
C iss = C gs + C gd, C ds SHORTED
C rss = C gd
Vgs = 3.5V
Vgs = 4.0V
Vgs = 4.5V
Vgs = 5.0V
Vgs = 8.0V
Vgs = 10V
16
Typical RDS(on) ( mΩ)
C oss = C ds + C gd
C, Capacitance(pF)
20 40 60 80 100 120 140 160
T J , Junction Temperature (°C)
VGS, Gate-to-Source Voltage (V)
100000
1000
ID = 29A
100
2
100
2.0
VDS = 15V
≤60µs PULSE WIDTH
1
10
Fig 5. Typical Output Characteristics
1000
10
1
V DS, Drain-to-Source Voltage (V)
Fig 4. Typical Output Characteristics
10000
Ciss
Coss
1000
Crss
12
T J = 25°C
8
4
0
100
1
10
100
VDS, Drain-to-Source Voltage (V)
Fig 8. Typical Capacitance vs.Drain-to-Source Voltage
4
VGS
10.0V
5.00V
4.50V
4.00V
3.50V
3.25V
3.00V
2.75V
0
50
100
150
200
ID, Drain Current (A)
Fig 9. Typical On-Resistance Vs.
Drain Current and Gate Voltage
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IRF6714MPbF
1000
100
ID, Drain-to-Source Current (A)
ISD, Reverse Drain Current (A)
1000
OPERATION IN THIS AREA
LIMITED BY R DS(on)
100µsec
100
T J = 150°C
T J = 25°C
T J = -40°C
10
1
10
1msec
1
DC
0.1
T A = 25°C
T J = 150°C
VGS = 0V
Single Pulse
0
0.01
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1
0.01
VSD, Source-to-Drain Voltage (V)
Typical VGS(th) Gate threshold Voltage (V)
160
140
120
100
80
60
40
20
0
50
75
100
125
1.00
10.00
100.00
Fig11. Maximum Safe Operating Area
180
25
0.10
VDS, Drain-to-Source Voltage (V)
Fig 10. Typical Source-Drain Diode Forward Voltage
ID, Drain Current (A)
10msec
3.5
3.0
2.5
2.0
ID = 100µA
1.5
1.0
ID = 250µA
ID = 1.0mA
ID = 1.0A
0.5
-75 -50 -25
150
0
25
50
75 100 125 150
T J , Temperature ( °C )
T C , Case Temperature (°C)
Fig 13. Typical Threshold Voltage vs. Junction
Temperature
Fig 12. Maximum Drain Current vs. Case Temperature
EAS , Single Pulse Avalanche Energy (mJ)
800
ID
2.43A
3.22A
BOTTOM 23.0A
700
TOP
600
500
400
300
200
100
0
25
50
75
100
125
150
Starting T J , Junction Temperature (°C)
Fig 14. Maximum Avalanche Energy vs. Drain Current
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5
IRF6714MPbF
Id
Vds
Vgs
L
VCC
DUT
0
20K
1K
Vgs(th)
S
Qgodr
Fig 15a. Gate Charge Test Circuit
Qgd
Qgs2 Qgs1
Fig 15b. Gate Charge Waveform
V(BR)DSS
15V
D.U.T
V
RGSG
20V
DRIVER
L
VDS
tp
+
- VDD
IAS
tp
A
I AS
0.01Ω
Fig 16b. Unclamped Inductive Waveforms
Fig 16a. Unclamped Inductive Test Circuit
VDS
VGS
RG
RD
VDS
90%
D.U.T.
+
- V DD
VGS
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
10%
VGS
td(on)
Fig 17a. Switching Time Test Circuit
6
tr
t d(off) tf
Fig 17b. Switching Time Waveforms
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IRF6714MPbF
Driver Gate Drive
D.U.T
ƒ
+
-
-

RG
*
•
•
•
•
„
***
D.U.T. ISD Waveform
Reverse
Recovery
Current
+
dv/dt controlled by RG
Driver same type as D.U.T.
I SD controlled by Duty Factor "D"
D.U.T. - Device Under Test
P.W.
Period
VGS=10V
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
‚
D=
Period
P.W.
+
V DD
**
+
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
-
Body Diode
VDD
Forward Drop
Inductor Curent
Ripple ≤ 5%
* Use P-Channel Driver for P-Channel Measurements
** Reverse Polarity for P-Channel
ISD
*** VGS = 5V for Logic Level Devices
Fig 18. Diode Reverse Recovery Test Circuit for HEXFET® Power MOSFETs
DirectFET™ Board Footprint, MX Outline
(Medium Size Can, X-Designation).
Please see DirectFET application note AN-1035 for all details regarding the assembly of DirectFET.
This includes all recommendations for stencil and substrate designs.
G = GATE
D = DRAIN
S = SOURCE
D
D
S
G
S
D
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D
7
IRF6714MPbF
DirectFET™ Outline Dimension, MX Outline
(Medium Size Can, X-Designation).
Please see DirectFET application note AN-1035 for all details regarding the assembly of DirectFET. This includes
all recommendations for stencil and substrate designs.
DIM EN SION S
METRIC
CO DE
A
B
C
D
E
F
G
H
J
K
L
M
R
P
MIN
6.25
4.80
3.85
0.35
0.68
0.68
1.38
0.80
0.38
0.88
2.28
0.616
0.020
0.08
M AX
6.35
5.05
3.95
0.45
0.72
0.72
1.42
0.84
0.42
1.01
2.41
0.676
0.080
0.17
IMPE RIAL
M IN
0.246
0.189
0.152
0.014
0.027
0.027
0.054
0.032
0.015
0.035
0.090
0.0235
0.0008
0.003
M AX
0.250
0.201
0.156
0.018
0.028
0.028
0.056
0.033
0.017
0.039
0.095
0.0274
0.0031
0.007
DirectFET™ Part Marking
GATE MARKING
LOGO
PART NUMBER
BATCH NUMBER
DATE CODE
Line above the last character of
the date code indicates "Lead-Free"
8
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IRF6714MPbF
DirectFET™ Tape & Reel Dimension (Showing component orientation).
NOTE: Controlling dimensions in mm
Std reel quantity is 4800 parts. (ordered as IRF6714MTRPBF). For 1000 parts on 7"
reel, order IRF6714MTR1PBF
STANDARD OPTION
METRIC
CODE
MIN
MAX
A
330.0
N.C
B
20.2
N.C
C
12.8
13.2
D
1.5
N.C
E
100.0
N.C
F
N.C
18.4
G
12.4
14.4
H
11.9
15.4
REEL DIMENSIONS
(QTY 4800)
TR1 OPTION
IMPERIAL
METRIC
MIN
MAX
MAX
MIN
12.992
N.C
177.77 N.C
0.795
N.C
19.06
N.C
0.504
0.520
13.5
12.8
0.059
1.5
N.C
N.C
3.937
N.C
58.72
N.C
N.C
N.C
13.50
0.724
0.488
11.9
12.01
0.567
0.469
11.9
0.606
12.01
(QTY 1000)
IMPERIAL
MAX
MIN
N.C
6.9
N.C
0.75
0.53
0.50
0.059
N.C
2.31
N.C
N.C
0.53
0.47
N.C
0.47
N.C
LOADED TAPE FEED DIRECTION
NOTE: CONTROLLING
DIMENSIONS IN MM
CODE
A
B
C
D
E
F
G
H
DIMENSIONS
METRIC
IMPERIAL
MIN
MAX
MIN
MAX
0.311
0.319
8.10
7.90
0.154
0.161
3.90
4.10
0.484
0.469
12.30
11.90
0.215
0.219
5.55
5.45
0.209
0.201
5.30
5.10
0.256
0.264
6.70
6.50
0.059
N.C
1.50
N.C
0.059
0.063
1.60
1.50
Data and specifications subject to change without notice.
This product has been designed and qualified for the Consumer market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.09/2007
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9