INTERSIL ISL54224

ISL54224
Features
The Intersil ISL54224 is a single supply dual 2:1
multiplexer that can operate from a single 2.7V to 5.25V
supply. It contains two SPDT (Single Pole/Double
Throw) switches configured as a DPDT. The part was
designed for switching of USB data signals in portable
battery powered products.
• High-Speed (480Mbps) and Full-Speed (12Mbps)
Signaling Capability per USB 2.0
• 1.8V Logic Compatible (2.7V to +3.6V supply)
• OE/ALM Pin to Open all Switches and Indicate
Overvoltage Fault Condition
• Power OFF Protection
• D-/D+ Pins Overvoltage Protection for +5.25V and
-5V Fault Voltages
• -3dB Frequency . . . . . . . . . . . . . . . . . . 780MHz
• Low ON Capacitance @ 240MHz . . . . . . . . . 3.3pF
• Low ON-Resistance . . . . . . . . . . . . . . . . . . 6.5Ω
• Single Supply Operation (VDD) . . . . 2.7V to 5.25V
• Available in µTQFN and TDFN Packages
• Pb-Free (RoHS Compliant)
• Compliant with USB 2.0 Short Circuit and
Overvoltage Requirements Without Additional
External Components
The 6.5Ω switches were specifically designed to pass
USB high speed/full speed data signals. They have high
bandwidth and low capacitance to pass USB high speed
data signals with minimal distortion.
The ISL54224 has OVP circuitry on the D-/D+ com pins
that opens the USB in-line switches when the voltage at
these pins exceeds 3.8V (typ) or goes negative by -0.5V
(typ). It isolates fault voltages up to +5.25V or down to
-5V from getting passed to the other-side of the switch,
thereby protecting the USB transceivers.
The digital logic inputs are 1.8V logic compatible when
operated with a 2.7V to 3.6V supply. The ISL54224 has
an open drain OE/ALM pin that can be driven Low to
open all switches and outputs a Low when the OVP
circuitry is activated. It can be used to facilitate proper
bus disconnect and connection when switching between
the USB sources.
The ISL54224 is available in 10 Ld 1.8mmx1.4mm
µTQFN and 10 Ld TDFN packages. It operates over a
temperature range of -40 to +85°C.
Applications*(see page 16)
•
•
•
•
•
MP3 and other Personal Media Players
Cellular/Mobile Phones
PDA’s
Digital Cameras and Camcorders
USB Switching
Related Literature*(see page 16)
• See AN1571 “ISL54224IRTZEVAL1Z Evaluation
Board User's Manual”
Typical Application
USB 2.0 HS Eye Pattern With
Switches in the Signal Path
3.3V
100kΩ
USB CONNECTOR
VDD
LOGIC
CONTROL
VBUS
SEL
HSD1-
D-
D-
D+
D+
HSD1+
OVP
GND
OE/ALM
ISL54224
µP
USB
TRANSCEIVER
HSD2HSD2+
GND
USB
TRANSCEIVER
VOLTAGE SCALE (0.1V/DIV)
3.3V
500Ω
TIME SCALE (0.2ns/DIV)
June 7, 2010
FN6969.0
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2010. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL54224
High-Speed USB 2.0 (480Mbps) Multiplexer with
Overvoltage Protection (OVP) and Overvoltage
Indicator Output
ISL54224
Pin Configuration
ISL54224
(10 LD 3X3 TDFN)
TOP VIEW
ISL54224
(10 LD 1.8X1.4 µTQFN)
TOP VIEW
HSD1+ HSD17
VDD 9
SEL 10
5
LOGIC
CONTROL
OE/ALM 8
4MΩ
PD
6
4MΩ
SEL
D-
LOGIC CONTROL
1
OVP
1
4
GND
3
D+
10 VDD
4MΩ
4MΩ
HSD2-
2
9
OE/ALM
HSD2+
3
8
HSD1+
D+
4
7 HSD1-
GND
5
2
HSD2- HSD2+
6
OVP
D-
NOTE:
1. Switches Shown for SEL = Logic “1” and OE/ALM = Logic “1”.
Pin Descriptions
Truth Table
OE/ALM
SEL
HSD1-, HSD1+
HSD2-, HSD2+
0
X
OFF
OFF
1
0
ON
OFF
1
1
OFF
ON
PIN
NAME
µTQFN
TDFN
1
2
HSD2- USB Data Port Channel 2
2
3
HSD2+ USB Data Port Channel 2
3
4
D+
USB Data COM Port
4
5
GND
Ground Connection
5
6
D-
USB Data COM Port
6
7
HSD1- USB Data Port Channel 1
7
8
HSD1+ USB Data Port Channel 1
8
9
OE/ALM Switch Enable/Alarm (open drain
connection)
Drive Low to Open All Switches
Outputs Low when OTV is
Activated
9
10
VDD
Power Supply
10
1
SEL
Select Logic Control Input
-
PD
PD
Thermal Pad. Tie to Ground or
Float
Logic “0” when ≤ 0.5V, Logic “1” when ≥ 1.4V with a 2.7V
to 3.6V Supply.
DESCRIPTION
TABLE 1. USB - OVP POSSIBLE SITUATIONS AND TRIP POINT VOLTAGE
TRIP POINT
CODEC SUPPLY
SWITCH SUPPLY (VDD)
COMs SHORTED TO
PROTECTED
MIN
MAX
OE/ALM
2.7V to 3.3V
2.7V to 5.25V
VBUS
Yes
3.63V
3.95V
Low
2.7V to 3.3V
2.7V to 5.25V
-5V
Yes
-0.76V
-0.29V
Low
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FN6969.0
June 7, 2010
ISL54224
Ordering Information
PART
NUMBER
PART
MARKING
ISL54224IRUZ-T (Notes 2, 3)
TEMP. RANGE
(°C)
PACKAGE
(Pb-Free)
PKG.
DWG. #
T9
-40 to +85
10 Ld 1.8x1.4mm µTQFN (Tape and Reel)
L10.1.8x1.4A
ISL54224IRUZ-T7A (Notes 2, 3) T9
-40 to +85
10 Ld 1.8x1.4mm µTQFN (Tape and Reel)
L10.1.8x1.4A
ISL54224IRTZ (Note 4)
4224
-40 to +85
10 Ld 3x3 TDFN
L10.3x3A
ISL54224IRTZ-T (Notes 2, 4)
4224
-40 to +85
10 Ld 3x3 TDFN (Tape and Reel)
L10.3x3A
ISL54224IRUEVAL1Z
Evaluation Board
2. Please refer to TB347 for details on reel specifications.
3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach
materials and NiPdAu plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free
soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J STD-020.
4. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both
SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
5. For Moisture Sensitivity Level (MSL), please see device information page for ISL54224. For more information on MSL please
see techbrief TB363.
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FN6969.0
June 7, 2010
ISL54224
Absolute Maximum Ratings
VDD to GND . . . . . . . . . . . . . . . . . . . . . .
VDD to Dx . . . . . . . . . . . . . . . . . . . . . . . .
Dx to HSD1x, HSD2x . . . . . . . . . . . . . . . .
Input Voltages
HSD2x, HSD1x . . . . . . . . . . . . . . . . . . .
SEL, OE/ALM. . . . . . . . . . . . . . . . . . . . .
Output Voltages
D+, D- . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous Current (HSD2x, HSD1x) . . . . .
Peak Current (HSD2x, HSD1x)
(Pulsed 1ms, 10% Duty Cycle, Max) . . . .
ESD Rating:
Human Body Model . . . . . . . . . . . . . . . . .
Machine Model . . . . . . . . . . . . . . . . . . . .
Charged Device Model . . . . . . . . . . . . . . .
Latch-up Tested per JEDEC; Class II Level A
Thermal Information
. . . -0.3 to 6.5V
. . . . . . . 10.5V
. . . . . . . . 8.6V
. - 0.3V to 6.5V
. . . -0.3 to 6.5V
. . . -5V to 6.5V
. . . . . . ±40mA
. . . . . ±100mA
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
. >5.5kV
. >250V
. . >2kV
at 85°C
Thermal Resistance (Typical)
θJA (°C/W) θJC (°C/W)
10 Ld µTQFN Package (Note 6, 7) .
210
165
10 Ld TDFN Package (Notes 8, 9). .
58
22
Maximum Junction Temperature (Plastic Package). . +150°C
Maximum Storage Temperature Range . . . -65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Temperature Range . . . . . .
VDD Supply Voltage Range.
Logic Control Input Voltage
Analog Signal Range
VDD = 2.7V to 5.25V . . .
. . . . . . . . . . . . -40°C to +85°C
. . . . . . . . . . . . . 2.7V to 5.25V
. . . . . . . . . . . . . . . 0V to 5.25V
. . . . . . . . . . . . . . . . 0V to 3.6V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact
product reliability and result in failures not covered by warranty.
NOTES:
6. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief
TB379 for details.
7. For θJC, the “case temp” location is taken at the package top center.
8. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach”
features. See Tech Brief TB379.
9. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications - 2.7V to 5.25V Supply Test Conditions: VDD = +3.3V, GND = 0V, VSELH = 1.4V, VSELL = 0.5V,
VOE/ALMH = 1.4V, VOE/ALML = 0.5V, (Note 10), Unless Otherwise
Specified. Boldface limits apply over the operating temperature
range, -40°C to +85°C.
PARAMETER
TEST CONDITIONS
TEMP
MIN
(°C) (Notes 11, 12)
TYP
MAX
(Notes 11, 12) UNITS
ANALOG SWITCH CHARACTERISTICS
ON-Resistance, rON
(High-Speed)
VDD = 2.7V, SEL = 0.5V or 1.4V,
OE/ALM = 1.4V, IDx = 17mA, VHSD1x or
VHSD2x = 0V to 400mV (see Figure 3, Note 15)
rON Matching Between
Channels, ΔrON
(High-Speed)
VDD = 2.7V, SEL = 0.5V or 1.4V,
OE/ALM = 1.4V, IDx = 17mA, V VHSD1x or
VHSD2x = Voltage at max rON, (Notes 14, 15)
rON Flatness, RFLAT(ON) VDD = 2.7V, SEL = 0.5V or 1.4V,
OE/ALM = 1.4V, IDx = 17mA, VHSD1x or
(High-Speed)
VHSD2x = 0V to 400mV, (Notes 13, 15)
ON-Resistance, rON
VDD = 3.3V, SEL = 0.5V or 1.4V,
OE/ALM = 1.4V, ICOMx = 17mA, VD+ or
VD-= 3.3V (See Figure 4, Note 15)
OFF Leakage Current,
IHSD1x(OFF)
VDD = 5.25V, SEL = VDD and OE/ALM = VDD or
OE/ALM = 0V, VDx = 0.3V, 3.3V,
VHSD1x = 3.3V, 0.3V, VHSD2x = 0.3V, 3.3V
ON Leakage Current,
IHSD1x(ON)
VDD = 5.25V, SEL = 0V, OE/ALM = VDD,
VDx = 0.3V, 3.3V, VHSD1X = 0.3V, 3.3V,
VHSD2x = 3.3V, 0.3V
OFF Leakage Current,
IHSD2x(OFF)
VDD = 5.25V, SEL = 0V and OE/ALM = VDD or
OE/ALM = 0V, VDx = 3.3V, 0.3V, VHSD2x = 0.3V,
3.3V, VHSD1X = 3.3V, 0.3V
ON Leakage Current,
IHSD2x(ON)
VDD = 5.25V, SEL = VDD, OE/ALM = VDD,
VDx = 0.3V, 3.3V, VHSD2x = 0.3V, 3.3V,
VHSD1x = 3.3V, 0.3V
4
25
-
6.5
7
Ω
Full
-
-
9
Ω
25
-
0.2
0.45
Ω
Full
-
-
0.5
Ω
25
-
0.3
0.5
Ω
Full
-
-
1
Ω
25
-
12
20
Ω
Full
-
-
25
Ω
25
-20
1
20
nA
Full
-30
-
30
nA
25
-
2
3
µA
Full
-
-
4
µA
25
-20
1
20
nA
Full
-30
-
30
nA
25
-
2
3
µA
Full
-
-
4
µA
FN6969.0
June 7, 2010
ISL54224
Electrical Specifications - 2.7V to 5.25V Supply Test Conditions: VDD = +3.3V, GND = 0V, VSELH = 1.4V, VSELL = 0.5V,
VOE/ALMH = 1.4V, VOE/ALML = 0.5V, (Note 10), Unless Otherwise
Specified. Boldface limits apply over the operating temperature
range, -40°C to +85°C. (Continued)
PARAMETER
Power OFF Leakage
Current, ID+, ID-
TEST CONDITIONS
VDD = 0V, VD+ = 5.25V, VD-= 5.25V,
SEL = OE/ALM = VDD
TEMP
MIN
(°C) (Notes 11, 12)
TYP
MAX
(Notes 11, 12) UNITS
25
-
5
13
µA
Power OFF Logic Current, VDD = 0V, SEL = OE/ALM = 5.25V
ISEL, IOE/ALM
25
-
19
26
µA
Power OFF D+/DVDD = 0V, SEL = OE/ALM = VDD,
Current, IHSDX+, IHSDX- VHSDX+ = VHSDX- = 5.25V
25
-
0.05
1
µA
Positive Fault-Protection VDD = 2.7V to 5.25V, SEL = 0V or VDD,
OE/ALM = VDD, see Table 1 on page 2
Trip Threshold, VPFP
25
3.63
3.8
3.95
V
Negative
Fault-Protection Trip
Threshold, VNFP
VDD = 2.7V to 5.25V, SEL = 0V or VDD,
OE/ALM = VDD, see Table 1 on page 2
25
-0.76
-0.5
-0.29
V
OFF Persistence Time
Fault Protection
Response Time
Negative OVP Response: VDD = 2.7V, SEL = 0V
or VDD, OE/ALM = VDD, VDx = 0V to -5V,
RL = 15kΩ
25
-
1
-
µs
Positive OVP Response: VDD = 2.7V, SEL = 0V
or VDD, OE/ALM = VDD, VDx = 0V to 5.25V,
RL = 15kΩ
25
-
2
-
µs
VDD = 2.7V, SEL = 0V or VDD, OE/ALM = VDD,
VDx = 0V to 5.25V or 0V to -5V, RL = 15kΩ
25
-
40
-
µs
OVERVOLTAGE PROTECTION DETECTION
ON Persistence Time
Fault Protection
Recovery Time
DYNAMIC CHARACTERISTICS
Turn-ON Time, tON
VDD = 3.3V, Vinput = 3V, RL = 50Ω, CL = 50pF
(see Figure 1)
25
-
110
-
ns
Turn-OFF Time, tOFF
VDD = 3.3V, Vinput = 3V, RL = 50Ω, CL = 50pF
(see Figure 1)
25
-
70
-
ns
Break-Before-Make Time
Delay, tD
VDD = 3.3V, RL = 50Ω, CL = 50pF (see Figure 2)
25
-
40
-
ns
Turn-ON Enable Time,
tENABLE
VDD = 3.3V, VINPUT = 3V, RL = 15kΩ,
CL = 50pF, Time out of All-Off state
25
-
90
-
ns
Turn-OFF Disable Time,
tDISABLE
VDD = 3.3V, VINPUT = 3V, RL = 15kΩ,
CL = 50pF, Time into All-Off state, Time is
highly dependent on the load (RL, CL) time
constant.
25
-
120
-
ns
Skew, (tSKEWOUT tSKEWIN)
VDD = 3.3V, SEL = 0V or 3.3V, OE/ALM = VDD,
RL = 45Ω, CL = 10pF, tR = tF = 500ps at
480Mbps, (Duty Cycle = 50%) (see Figure 6)
25
-
50
-
ps
Rise/Fall Degradation
VDD = 3.3V, SEL = 0V or 3.3V, OE/ALM = VDD,
(Propagation Delay), tPD RL = 45Ω, CL = 10pF (see Figure 6)
25
-
250
-
ps
25
-
-32
-
dB
Crosstalk
VDD = 3.3V, RL = 50Ω, f = 240MHz
(see Figure 5)
OFF-Isolation
VDD = 3.3V, RL = 50Ω, f = 240MHz
25
-
-30
-
dB
-3dB Bandwidth
Signal = 0dBm, 0.2VDC offset, RL = 50Ω
25
-
780
-
MHz
OFF Capacitance,
CHSxOFF
f = 1MHz, VDD = 3.3V, SEL = 0V or 3.3V,
OE/ALM = 0V (see Figure 4)
25
-
2.5
-
pF
COM ON Capacitance,
CDX(ON)
f = 1MHz, VDD = 3.3V, SEL = 0V or 3.3V,
OE/ALM = VDD (see Figure 4)
25
-
5.4
-
pF
5
FN6969.0
June 7, 2010
ISL54224
Electrical Specifications - 2.7V to 5.25V Supply Test Conditions: VDD = +3.3V, GND = 0V, VSELH = 1.4V, VSELL = 0.5V,
VOE/ALMH = 1.4V, VOE/ALML = 0.5V, (Note 10), Unless Otherwise
Specified. Boldface limits apply over the operating temperature
range, -40°C to +85°C. (Continued)
PARAMETER
COM ON Capacitance,
CDX(ON)
TEST CONDITIONS
f = 240MHz, VDD = 3.3V, SEL = 0V or 3.3V,
OE/ALM = VDD (see Figure 4)
TEMP
MIN
(°C) (Notes 11, 12)
TYP
3.3
MAX
(Notes 11, 12) UNITS
25
-
-
pF
Power Supply Range, VDD
Full
2.7
5.25
V
Positive Supply Current, VDD = 5.25V, SEL = 0V or VDD, OE/ALM = VDD
IDD
25
-
45
58
µA
Full
-
-
66
µA
25
-
23
30
µA
Full
-
-
35
µA
25
-
23
30
µA
Full
-
-
35
µA
25
-
35
45
µA
Full
-
-
52
µA
25
-
25
32
µA
Full
-
-
38
µA
POWER SUPPLY CHARACTERISTICS
Positive Supply Current, VDD = 3.6V, SEL = 0V or VDD, OE/ALM = VDD
IDD
Positive Supply Current, VDD = 3.6V, SEL = 0V or VDD, OE/ALM = 0V
IDD
Positive Supply Current, VDD = 4.3V, SEL = 2.6V, OE/ALM = 0V or 2.6V
IDD
Positive Supply Current, VDD = 3.6V, SEL = 1.4V, OE/ALM = 0V or 1.4V
IDD
DIGITAL INPUT CHARACTERISTICS
Input Voltage Low,
VSELL, VOE/ALML
VDD = 2.7V to 3.6V
Full
-
-
0.5
V
Input Voltage High,
VSELH, VOE/ALMH
VDD = 2.7V to 3.6V
Full
1.4
-
5.25
V
Input Voltage Low,
VSELL, VOE/ALML
VDD = 3.7V to 4.2V
Full
-
-
0.7
V
Input Voltage High,
VSELH, VOE/ALMH
VDD = 3.7V to 4.2
Full
1.7
-
-
V
Input Voltage Low,
VSELL, VOE/ALML
VDD = 4.3V to 5.25V
Full
-
-
0.8
V
Input Voltage High,
VSELH, VOE/ALMH
VDD = 4.3V to 5.25V
Full
2.0
-
-
V
Input Current, ISELL,
IOE/ALML
VDD = 5.25V, SEL = 0V, OE/ALM = 0V
Full
-
2
-
nA
Input Current, ISELH
VDD = 5.25V, SEL = 5.25V, 4MΩ pull-down
resistor
Full
-
1.4
-
µA
Full
-
1.4
-
µA
Input Current, IOE/ALMH VDD = 5.25V, OE/ALM = 5.25V, 4MΩ pull-down
resistor
NOTES:
10. VLOGIC = Input voltage to perform proper function.
11. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this
data sheet.
12. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established
by characterization and are not production tested
13. Flatness is defined as the difference between maximum and minimum value of ON-resistance over the specified analog signal
range
14. rON matching between channels is calculated by subtracting the channel with the highest max rON value from the channel with
lowest max rON value, between HSD2+ and HSD2- or between HSD1+ and HSD1-.
15. Limits established by characterization and are not production tested.
6
FN6969.0
June 7, 2010
ISL54224
Test Circuits and Waveforms
VDD
LOGIC
INPUT
VDD
tr < 20ns
tf < 20ns
50%
0V
VINPUT
tOFF
SWITCH
INPUT
VINPUT
OE/ALM
VOUT
HSDxx
Dx
SEL
VOUT
90%
SWITCH
OUTPUT
SWITCH
INPUT
C
90%
VIN
CL
RL
GND
0V
tON
Logic input waveform is inverted for switches that have the
opposite logic sense.
Repeat test for all switches. CL includes fixture and stray
capacitance.
RL
----------------------V OUT = V
(INPUT) R + r
L
ON
FIGURE 1B. TEST CIRCUIT
FIGURE 1A. MEASUREMENT POINTS
FIGURE 1. SWITCHING TIMES
VDD
VDD
LOGIC
INPUT
SWITCH
OUTPUT
VOUT
OE/ALM
HSD2x
VINPUT
0V
RL
50Ω
SEL
90%
VOUT
Dx
HSD1x
CL
10pF
GND
VIN
0V
C
tD
Repeat test for all switches. CL includes fixture and stray
capacitance.
FIGURE 2A. MEASUREMENT POINTS
FIGURE 2B. TEST CIRCUIT
FIGURE 2. BREAK-BEFORE-MAKE TIME
VDD
C
rON = V1/17mA
OE/ALM
HSDx
VHSDx
SEL
V1
17mA
OV OR VDD
Dx
GND
Repeat test for all switches.
FIGURE 3. rON TEST CIRCUIT
7
FN6969.0
June 7, 2010
ISL54224
Test Circuits and Waveforms (Continued)
VDD
VDD
C
C
OE/ALM
OE/ALM
HSDxx
SIGNAL
GENERATOR
HSD1x
50Ω
Dx
SEL
SEL
IMPEDANCE
ANALYZER
0V OR
VDD
Dx
VIN
GND
HSD2x
Dx
ANALYZER
NC
GND
RL
Repeat test for all switches.
Signal direction through switch is reversed.
Repeat test for all switches.
FIGURE 5. CROSSTALK TEST CIRCUIT
FIGURE 4. CAPACITANCE TEST CIRCUIT
VDD
C
tri
OE/ALM
90%
DIN+
DIN-
10%
50%
VIN
tskew_i
90%
SEL
15.8Ω
COMD2
DIN+
50%
143Ω
10%
DIN-
tfi
tro
15.8Ω
OUT+
D2
45Ω
CL
COMD1
OUT-
D1
45Ω
CL
143Ω
90%
OUT+
OUT-
10%
50%
GND
tskew_o
90%
50%
|tfo - tfi| Delay Due to Switch for Falling Input and Falling Output Signals.
10%
tf0
|tro - tri| Delay Due to Switch for Rising Input and Rising Output Signals.
|tskew_0| Change in Skew through the Switch for Output Signals.
|tskew_i| Change in Skew through the Switch for Input Signals.
FIGURE 6A. MEASUREMENT POINTS
FIGURE 6B. TEST CIRCUIT
FIGURE 6. SKEW TEST
8
FN6969.0
June 7, 2010
ISL54224
Application Block Diagram
3.3V
500Ω
ISL54224
USB CONNECTOR
VDD
LOGIC CIRCUITRY
4MΩ
D-
D-
D+
D+
µCONTROLLER
100kΩ
OE/ALM
SEL
VBUS
3.3V
4MΩ
HSD1HSD1+
OVP
HSD2HSD2+
GND
GND
USB
HIGH-SPEED
OR
FULL-SPEED
TRANSCEIVER
#1
USB
HIGH_SPEED
OR
FULL-SPEED
TRANSCEIVER
#2
PORTABLE MEDIA DEVICE
Detailed Description
The ISL54224 device is a dual single pole/double throw
(SPDT) analog switch configured as a DPDT that operates
from a single DC power supply in the range of 2.7V to
5.25V.
It was designed to function as a dual 2-to-1 multiplexer
to select between two USB high-speed differential data
signals in portable battery powered products. It is offered
in a TDFN, and a small µTQFN packages for use in MP3
players, cameras, PDAs, cellphones, and other personal
media players.
The part contains special overvoltage detection and
protection (OVP) circuitry on the D-/D+ com pins. This
circuitry acts to open the USB in-line switches when the
part senses a voltage on the com pins that is >3.8V (typ)
or < -0.5V (typ). It isolates voltages up to 5.25V and
down to -5V from getting through to the other side of the
switch to protect the USB transceivers connected at the
signal pins (HSD1-, HSD1+, HSD2-, HSD2+).
The device has an open drain OE/ALM pin that can be
driven “Low” to open all switches. The OE/ALM pin gets
internally pulled “Low” whenever the part senses an
overvoltage condition. The pin must be externally pulled
“High” with a 100kΩ pull-up resistor and monitored for a
“Low” to determine when an overvoltage condition has
occurred.
The part consists of four 6.5Ω high speed (HSx) switches.
These switches have high bandwidth and low capacitance
to pass USB high-speed (480Mbps) differential data
signals with minimal edge and phase distortion. They can
also swing from 0V to 3.6V to pass USB full speed
(12Mbps) differential data signals with minimal
distortion.
9
The ISL54224 was designed for MP3 players, cameras,
cellphones, and other personal media player applications
that have multiple high-speed or full-speed transceivers
sections and need to multiplex between these USB
sources to a single USB host (computer). A typical
application block diagram of this functionality is
previously shown.
A detailed description of the HS switches is provided in
the following section.
High-Speed (HSx) Data Switches
The HSx switches (HSD1-, HSD1+, HSD2-, HSD2+) are
bi-directional switches that can pass USB high-speed and
USB full-speed signals when VDD is in the range of 2.7V
to 5.25V.
When powered with a 2.7V supply, these switches have a
nominal rON of 6.5Ω over the signal range of 0V to
400mV with a rON flatness of 0.3Ω. The rON matching
between the HSD1x switches and HSD2x switches over
this signal range is only 0.2Ω, ensuring minimal impact
by the switches to USB high-speed signal transitions. As
the signal level increases, the rON switch resistance
increases. At a signal level of 3.3V, the switch resistance
is nominally 12Ω. See Figures 9, 10, 11, 12, 13, 14, 15,
and 16 in the “Typical Performance Curves” beginning on
page 12.
The HSx switches were specifically designed to pass USB
2.0 high-speed (480Mbps) differential signals in the
range of 0V to 400mV. They have low capacitance and
high bandwidth to pass the USB high-speed signals with
minimum edge and phase distortion to meet USB 2.0
high speed signal quality specifications. See Figure 20 in
the “Typical Performance Curves” on page 14 for USB
High-speed Eye Pattern taken with switch in the signal
path.
FN6969.0
June 7, 2010
ISL54224
The HSx switches can also pass USB full-speed signals
(12Mbps) with minimal distortion and meet all the USB
requirements for USB 2.0 full-speed signaling. See
Figure 21 in the “Typical Performance Curves” on
page 14 for USB Full-speed Eye Pattern taken with
switch in the signal path.
The HS1 channel switches are active (turned ON)
whenever the SEL voltage is logic “0”(Low) and the
OE/ALM voltage is logic “1”(High).
The HS2 channel switches are active (turned ON)
whenever the SEL voltage is logic “1” (High) and the
OE/ALM voltage is logic “1” (High).
the IC that can trigger parasitic SCR structures to turn
ON, creating a low impedance path from the VDD
power supply to ground. This will result in a significant
amount of current flow in the IC, which can potentially
create a latch-up state or permanently damage the IC.
The external VDD resistor limits the current during this
over-stress situation and has been found to prevent
latch-up or destructive damage for many overvoltage
transient events.
Under normal operation, the low microamp IDD current
of the IC produces an insignificant voltage drop across
the series resistor resulting in no impact to switch
operation or performance.
Overvoltage Protection (OVP)
VSUPPLY
The maximum normal operating signal range for the HSx
switches is from 0V to 3.6V. For normal operation, the
signal voltage should not be allowed to exceed this voltage
range or go below ground by more than -0.3V.
PROTECTION
RESISTOR
100Ω to 1kΩ
However, in the event that a positive voltage > 3.8V
(typ) to 5.25V, such as the USB 5V VBUS voltage, gets
shorted to one or both of the COM+ and COM- pins or a
negative voltage < -0.5V (typ) to -5V gets shorted to one
or both of the COM pins, the ISL54224 has OVP circuitry
to detect the overvoltage condition and open the SPDT
switches to prevent damage to the USB down-stream
transceivers connected at the signal pins (HS1D-,
HS1D+, HS2D-, HS2D+).
The OE/ALM pin gets internally pulled low whenever the
part senses an overvoltage condition. The pin must be
externally pulled “High” with a pull-up resistor and
monitored for a “Low” to determine when an overvoltage
condition has occurred.
External VDD Series Resistor to Limit IDD
Current during Negative OVP Condition
A 100Ω to 1kΩ resistor in series with the VDD pin (see
Figure 7) is required to limit the IDD current draw from
the system power supply rail during a negative OVP fault
event.
With a negative -5V fault voltage at both com pins, the
graph in Figure 8 shows the IDD current draw for
different external resistor values for supply voltages of
2.7V, 3.6V, and 5.25V. Note: With a 500Ω resistor the
current draw is limited to around 5mA. When the
negative fault voltage is removed the IDD current will
return to it’s normal operation current of 25µA to 45µA.
The series resistor also provides improved ESD and
latch-up immunity. During an overvoltage transient
event (such as occurs during system level IEC 61000
ESD testing), substrate currents can be generated in
10
IDD
VDD
HSD1+
D+
-5V
D-
FAULT
VOLTAGE
VSUPPLY
HSD2+
HSD1HSD2-
OVP
SEL LOGIC
100kΩ
OE/ALM
GND
PULLED “LOW”
TO INDICATE OVP
FIGURE 7. VDD SERIES RESISTOR TO LIMIT IDD
CURRENT DURING NEGATIVE OVP AND FOR
ENHANCED ESD AND LATCH-UP IMMUNITY
25
VCOM+ = VCOM- = -5V
20
IDD (mA)
The OVP and power-off protection circuitry allows the
COM pins (D-, D+) to be driven up to 5.25V while the
VDD supply voltage is in the range of 0V to 5.25V. In this
condition the part draws < 100µA of ICOMx and IDD
current and causes no stress to the IC. In addition, the
SPDT switches are OFF and the fault voltage is isolated
from the other side of the switch.
C
5.25V
15
10
5
0
100
3.6V
2.7V
200
300
400 500 600 700
RESISTOR (Ω)
800
900 1k
FIGURE 8. NEGATIVE OVP IDD CURRENT vs RESISTOR
VALUE vs VSUPPLY
ISL54224 Operation
The following will discuss using the ISL54224 shown in
the “Application Block Diagram” on page 9.
POWER
The power supply connected at the VDD pin provides the
DC bias voltage required by the ISL54224 part for proper
operation. The ISL54224 can be operated with a VDD
voltage in the range of 2.7V to 5.25V.
FN6969.0
June 7, 2010
ISL54224
For lowest power consumption you should use the lowest
VDD supply.
A 0.01µF or 0.1µF decoupling capacitor should be
connected from the VDD pin to ground to filter out any
power supply noise from entering the part. The
capacitor should be located as close to the VDD pin as
possible.
In a typical application, VDD will be in the range of
2.8V to 4.3V and will be connected to the battery or
LDO of the portable media device.
LOGIC CONTROL
The state of the ISL54224 device is determined by the
voltage at the SEL pin and the OE/ALM pin. SEL is only
active when the OE/ALM pin is logic “1” (High). Refer to
“Truth Table” on page 2.
The ISL54224 logic pins are designed to minimize
current consumption when the logic control voltage is
lower than the VDD supply voltage. With VDD = 3.6V and
logic pins at 1.4V the part typically draws only 25µA.
With VDD = 4.3V and logic pins at 2.6V the part typically
draws only 35µA. Driving the logic pins to the VDD supply
rail minimizes power consumption.
When a computer or USB hub is plugged into the
common USB connector and Channel 1 is active, a link
will be established between the USB 1 transceiver section
of the media player and the computer. The device will be
able to transmit and receive data from the computer.
HSD2 USB Channel
If the SEL pin = Logic “1” and the OE/ALM pin = Logic
“1”, high-speed Channel 2 will be ON. The HSD2- and
HSD2+ switches are ON and the HSD1- and HSD1+
switches are OFF (high impedance).
When a USB cable from a computer or USB hub is
connected at the common USB connector and Channel 2
is active, a link will be established between the USB 2
driver section of the media player and the computer. The
device will be able to transmit and receive data from the
computer.
All Switches OFF Mode
If the SEL pin = Logic “0” or Logic “1” and the OE/ALM
pin = Logic “0”, all of the switches will turn OFF (high
impedance).
The SEL pin and OE/ALM pin have special circuitry that
allows them to be driven with a voltage higher than the
VDD supply voltage. These pins can be driven up to
5.25V with a VDD supply in the range of 2.7V to 5.25V.
The all OFF state can be used to switch between the two
USB sections of the media player. When disconnecting
from one USB device to the other USB device, you can
momentarily put the ISL54224 switch in the “all off”
state in order to get the computer to disconnect from
the one device so it can properly connect to the other
USB device when that channel is turned ON.
The SEL pin and OE/ALM pin are internally pulled low
through 4MΩ resistors to ground and can be tri-stated by
a µProcessor.
Whenever the ISL54224 senses a fault condition on the
COM pins, the OE/ALM pin will be internal pulled low by
the device and all switches will be turned OFF.
The OE/ALM pin is an open drain connection. It should be
pulled high through an external 100kΩ pull-up resistor.
The OE/ALM pin can then be driven “Low” by a
µProcessor to open all switches or it can be monitored by
the µProcessor for a “Low” when the part goes into an
over-voltage condition.
USB 2.0 VBUS Short Requirements
Logic Control Voltage Levels
TABLE 2. LOGIC CONTROL VOLTAGE LEVELS
VDD
SUPPLY
RANGE
LOGIC = “0” (LOW) LOGIC = “1” (HIGH)
OE/ALM
SEL
OE/ALM
SEL
2.7V to 3.6V
≤ 0.5V
or floating
≤ 0.5V
or floating
≥1.4V
≥1.4V
3.7V to 4.2V
≤ 0.7V
or floating
≤ 0.7V
or floating
≥1.7V
≥1.7V
4.3V to 5.25V
≤ 0.8V
≤ 0.8V
or floating or floating
≥2.0V
≥2.0V
HSD1 USB Channel
If the SEL pin = Logic “0” and the OE/ALM pin = Logic
“1”, high-speed Channel 1 will be ON. The HSD1- and
HSD1+ switches are ON and the HSD2- and HSD2+
switches are OFF (high impedance).
11
The USB specification in section 7.1.1 states a USB
device must be able to withstand a VBUS short (4.4V to
5.25V) or a -1V short to the D+ or D- signal lines when
the device is either powered off or powered on for at
least 24 hours.
The ISL54224 part has special power-off protection and
OVP detection circuitry to meet these short circuit
requirements. This circuitry allows the ISL54224 to
provide protection to the USB down-stream transceivers
connected at its signal pins (HS1D-, HS1D+, HS2D-,
HS2D+) to meet the USB specification short circuit
requirements.
The power-off protection and OVP circuitry allows the
COM pins (D-, D+) to be driven up to 5.25V or down to
-5V while the VDD supply voltage is in the range of 0V to
5.25V. In these overvoltage conditions with a 500Ω
external VDD resistor the part draws < 55µA of current
into the COM pins and causes no stress/damage to the
IC. In addition, all switches are OFF and the shorted
VBUS voltage will be isolated from getting through to the
other side of the switch channels, thereby protecting the
USB transceivers.
FN6969.0
June 7, 2010
ISL54224
Typical Performance Curves
6.5
6.4
TA = +25°C, Unless Otherwise Specified
30
ICOM = 17mA
ICOM = 17mA
25
2.7V
6.3
20
6.1
rON (Ω)
rON (Ω)
6.2
3.0V
6.0
3.3V
5.9
3.6V
5.8
4.3V
5.7
5.25V
5.6
0
0.1
2.7V
15
10
3.3V
5
0.2
0.3
0
0
0.4
0.6
1.2
VCOM (V)
FIGURE 9. ON-RESISTANCE vs SUPPLY VOLTAGE vs
SWITCH VOLTAGE
1.8
VCOM (V)
2.4
3.0
3.6
FIGURE 10. ON-RESISTANCE vs SUPPLY VOLTAGE vs
SWITCH VOLTAGE
12
8
ICOM = 17mA
+85°C
10
7
3.6V
rON (Ω)
rON (Ω)
3.0V
8
5.25V
+25°C
6
4.3V
-40°C
5
6
VDD = 2.7V
ICOM = 17mA
4
0
0.6
1.2
1.8
2.4
3.0
4
0
3.6
0.1
VCOM (V)
FIGURE 11. ON-RESISTANCE vs SUPPLY VOLTAGE vs
SWITCH VOLTAGE
8
VDD = 3.3V
ICOM = 17mA
0.4
8
VDD = 4.3V
ICOM = 17mA
+85°C
+85°C
7
rON (Ω)
rON (Ω)
0.3
FIGURE 12. ON-RESISTANCE vs SWITCH VOLTAGE
7
+25°C
6
5
4
0
0.2
VCOM (V)
0.2
0.3
0.4
VCOM (V)
FIGURE 13. ON-RESISTANCE vs SWITCH VOLTAGE
12
+25°C
5
-40°C
0.1
6
4
0
-40°C
0.1
0.2
VCOM (V)
0.3
0.4
FIGURE 14. ON-RESISTANCE vs SWITCH VOLTAGE
FN6969.0
June 7, 2010
ISL54224
Typical Performance Curves
18
VDD = 2.7V
ICOM = 17mA
25
15
20
12
rON (Ω)
rON (Ω)
30
TA = +25°C, Unless Otherwise Specified (Continued)
15
+85°C
+85°C
9
+25°C
6
10
-40°C
+25°C
5
0
VDD = 3.3V
ICOM = 17mA
3
-40°C
0
0.6
1.2
1.8
2.4
3.0
0
0
3.6
0.6
1.2
VCOM (V)
1.6
5.0
-40°C TO +85°C
IOL/ALM CURRENT (mA)
1.4
VINH AND VINL (V)
3.0
3.6
D+ = D- = 5V (OVP)
4.5
VINH
1.0
2.4
FIGURE 16. ON-RESISTANCE vs SWITCH VOLTAGE
FIGURE 15. ON-RESISTANCE vs SWITCH VOLTAGE
1.2
1.8
VCOM (V)
VINL
0.8
0.6
4.0
VDD = 5.25V
3.5
3.0
2.5
2.0
VDD = 2.7V
1.5
1.0
0.5
0.4
2.7
3.2
3.7
4.2
4.7
0
5.25
0
1
VDD (V)
2
3
VOL/ALM VOLTAGE (V)
4
5.25
FIGURE 18. OE/ALM IOL vs VOL DURING OVP STATE
FIGURE 17. DIGITAL SWITCHING POINT vs SUPPLY
VOLTAGE
12
IOL/ALM LEAKAGE CURRENT (µA)
D+ = D- = 3V (NORMAL OPERATION)
10
8
VDD = 2.7V
6
4
2
0
VDD = 5.25V
0
1
2
3
VOL/ALM VOLTAGE (V)
4
5
FIGURE 19. OE/ALM LEAKAGE CURRENT vs DIGITAL VOLTAGE DURING NORMAL OPERATION
13
FN6969.0
June 7, 2010
ISL54224
Typical Performance Curves
TA = +25°C, Unless Otherwise Specified (Continued)
VOLTAGE SCALE (0.1V/DIV)
VDD = 3.3V
TIME SCALE (0.2ns/DIV)
FIGURE 20. EYE PATTERN: 480Mbps WITH USB SWITCHES IN THE SIGNAL PATH
VOLTAGE SCALE (0.5V/DIV)
VDD = 3.3V
TIME SCALE (10ns/DIV)
FIGURE 21. EYE PATTERN: 12Mbps WITH USB SWITCHES IN THE SIGNAL PATH
14
FN6969.0
June 7, 2010
ISL54224
Typical Performance Curves
TA = +25°C, Unless Otherwise Specified (Continued)
-10
1
RL = 50Ω
-20 VIN = 0dBm, 0.2VDC BIAS
0
-30
NORMALIZED GAIN (dB)
NORMALIZED GAIN (dB)
-1
-2
-3
-4
RL = 50Ω
VIN = 0dBm, 0.86VDC BIAS
1M
-40
-50
-60
-70
-80
-90
-100
10M
100M
FREQUENCY (Hz)
1G
-110
0.001
0.01
0.1
1M
10M
100
500
FREQUENCY (MHz)
FIGURE 22. FREQUENCY RESPONSE
FIGURE 23. OFF-ISOLATION
Die Characteristics
SUBSTRATE AND TDFN THERMAL PAD
POTENTIAL (POWERED UP):
-10
NORMALIZED GAIN (dB)
RL = 50Ω
-20 VIN = 0dBm, 0.2VDC BIAS
GND
-30
TRANSISTOR COUNT:
-40
-50
1297
-60
PROCESS:
Submicron CMOS
-70
-80
-90
-100
-110
0.001
0.01
0.1
1
10
100
500
FREQUENCY (MHz)
FIGURE 24. CROSSTALK
15
FN6969.0
June 7, 2010
ISL54224
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to
web to make sure you have the latest Rev.
DATE
REVISION
6/7/10
FN6969.0
CHANGE
Initial Release.
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The
Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones,
handheld products, and notebooks. Intersil's product families address power management and analog signal
processing functions. Go to www.intersil.com/products for a complete list of Intersil product families.
*For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device
information page on intersil.com: ISL54224
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Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications
at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by
Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any
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patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
16
FN6969.0
June 7, 2010
ISL54224
Package Outline Drawing
L10.1.8x1.4A
10 LEAD ULTRA THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 5, 3/10
1.80
B
6
PIN #1 ID
A
1
1
1.40
3
10
0.50
6 PIN 1
INDEX AREA
9 X 0.40
2
10X 0.20 4
0.10 M C A B
0.05 M C
0.70
8
5
0.10
7
2X
4X 0.30
6
6X 0.40
TOP VIEW
BOTTOM VIEW
SEE DETAIL "X"
0.10 C
MAX. 0.55
C
SEATING PLANE
0.08 C
(9 X 0.60)
1
(10X 0.20)
(4X 0.30)
3
10
8
(0.70)
SIDE VIEW
(0.70)
C
5
6
0 .1 27 REF
7
(6X 0.40)
PACKAGE OUTLINE
0-0.05
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
NOTES:
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2.
Dimensioning and tolerancing conform to ASME Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4.
Dimension applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5.
JEDEC reference MO-255.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
17
FN6969.0
June 7, 2010
ISL54224
Thin Dual Flat No-Lead Plastic Package (TDFN)
L10.3x3A
2X
0.10 C A
A
10 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE
D
MILLIMETERS
2X
0.10 C B
E
B
//
A
C
SEATING
PLANE
D2
(DATUM B)
6
INDEX
AREA
0.10 C
0.08 C
A3
SIDE VIEW
7
8
MAX
NOTES
A
0.70
0.75
0.80
-
A1
-
-
0.05
-
0.20 REF
b
0.20
0.25
1
0.30
5, 8
D
2.95
3.0
3.05
-
D2
2.25
2.30
2.35
7, 8
E
2.95
3.0
3.05
-
E2
1.45
1.50
1.55
7, 8
e
0.50 BSC
-
k
0.25
-
-
-
L
0.25
0.30
0.35
8
N
10
2
Nd
5
3
Rev. 4 8/09
NOTES:
2
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
NX k
3. Nd refers to the number of terminals on D.
4. All dimensions are in millimeters. Angles are in degrees.
E2
E2/2
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
NX L
N
N-1
NX b
e
(Nd-1)Xe
REF.
BOTTOM VIEW
5
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
0.10 M C A B
8. Nominal dimensions are provided to assist with PCB Land
Pattern Design efforts, see Intersil Technical Brief TB389.
9. Compliant to JEDEC MO-229-WEED-3 except for D2
dimensions.
CL
NX (b)
NOMINAL
D2/2
(DATUM A)
8
MIN
A3
6
INDEX
AREA
TOP VIEW
SYMBOL
(A1)
L1
5
9 L
( 2.30 )
e
SECTION "C-C"
C C
( 2.00 )
TERMINAL TIP
FOR ODD TERMINAL/SIDE
( 10X 0.50)
(1.50)
( 2.90 )
Pin 1
(8x 0.50)
( 10X 0.25)
TYPICAL RECOMMENDED LAND PATTERN
18
FN6969.0
June 7, 2010