ISL97702 ® Data Sheet October 13, 2005 FN7462.0 Boost with Dual Reference Outputs Features The ISL97702 represents a high efficiency, boost converter with integrated boost FET, boost diode and input disconnect FET. A dual feedback circuit allows simple switching between two pre-defined output vbltages using a single logic input.. • Up to 87% efficiency With an input voltage of 2.3V to 5.5V the ISL97702 has an output capability of up to 50mA at 18V using integrated 500mA switches. Efficiencies are up to 87%. The integrated protection FET is used to disconnect the boost inductor from the input supply whenever an output fault condition is detected, or when the device is disabled. This gives 0 output current in the disabled mode, compared to standard boost converters where current can still flow when the device is disabled. • Integrated boost Schottky diode The ISL97702 comes in the 10 Ld 3x3 DFN package and is specified for operation over the -40°C to 85°C temperature range. Ordering Information • Up to 28V output • 50mA at 18V • Input voltage disconnect switch • Dual output voltage selectable • Synchronization input • Chip enable • 10 Ld 3x3 DFN package • Pb-free plus anneal available (RoHS compliant) Applications • OLED display power • LED display power PART TAPE & MARKING REEL PACKAGE PKG. DWG. # ISL97702IRZ (Note) 97702IRZ - 10 Ld 3x3 DFN MDP0047 (Pb-Free) ISL97702IRZ-T7 (Note) 97702IRZ 7” 10 Ld 3x3 DFN MDP0047 (Pb-Free) ISL97702IRZ-T13 97702IRZ (Note) 13” 10 Ld 3x3 DFN MDP0047 (Pb-Free) NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. • Adjustable power supplies Typical Application Diagram L1 6.8µ VDDOUT LX 2.3V-5.5V VDD C0 5µ NEN OSCILLATOR & CONTROL PART NUMBER • 2.3V to 5.5V input VOUT VDD+2V - 30V C1 R1 3.3µ 390K NSYNC FB0 GND R3 26.1K Pinout FB1 ISL97702 (10 LD 3X3 DFN) TOP VIEW GND 1 VDD 3 SEL BOOST WITH DUAL REFERENCE 10 LX 9 VOUT VDDOUT 2 THERMAL PAD 8 NEN V(VOUT)0 = (390K + 39K) / 39K * 1.15V = 12.65V V(VOUT)1 = (390K + 26.1K) / 26.1K * 1.15V = 18.33V NEN SEL VOUT NSYNC 4 7 SEL 1 X High Z FB0 5 6 FB1 0 0 VOUT0 0 1 VOUT1 1 R2 39K CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ISL97702 Block Diagram VDD Synchronization Signal Detector Under-Voltage Detector Over-Temperature Detector NSYNC 1 Over-Current Detector (DC) MUX Oscillator VDD S2 0 VDD CLK NEW START RESTART State Machine (Default Sequence) 1. Soft Inrush 2. VDDOUT Enable 3. Soft Boost 25 4. Soft Boost 50 5. Soft Boost 75 6. Normal VDD SEL AND VDDout DISABLE & WAIT OverVoltage Detector 2 Vout AND Slope Compensation Ramp-Generator FB1 S1 Error Amplifier Av Ccomp FB0 As Clamp Ai LX EN Control Logic -PWM Timing -Current Limit -Pulse Skipping Gate Driver Current Limit Comparator S0 Voltage Reference Rsense Rsense GND ISL97702 FIGURE 1. ISL97702 BLOCK DIAGRAM 2 FN7462.0 October 13, 2005 ISL97702 Absolute Maximum Ratings (TA = 25°C) Continuous Current in VDD, GND, VDDOUT, LX . . . . . . . . . 650mA Continuos Current in NSYNC, FB0, FB1, SEL, NEN. . . . . . . . 10mA Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C TA Ambient Operating Temperature. . . . . . . . . . . . .-40°C to +85°C TJ Operating Junction Temperature. . . . . . . . . . . . . . . . . . . +125°C VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to 6V VOUT to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to 31V LX to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VOUT+1V VDDOUT, NSYNC, FB0, FB1, SEL, NEN to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VDD+0.3V CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Electrical Specifications VDD = 3.6V, GND = NEN = 0V, SEL = NSYNC = VDD, R1 = 390K, R2 = 39K, R3 = 26.1K, L = 10µH, TA = -40°C to +85°C unless otherwise stated PARAMETER DESCRIPTION CONDITION MIN TYP MAX UNIT 5.5 V 0.1 3 µA 250 350 kΩ 1 µA SUPPLY VDD Supply Operating Voltage Range IDIS Supply Current when Disabled 2.3 NEN = VDD LOGIC INPUTS – NEN, NSYNC, SEL Rup Pull-up Resistor Enabled, Input at GND 150 IIL Leakage Current when Disabled Disabled, Input at GND -1 VHI Logic High Threshold VLO Logic Low Threshold 1.8 V 0.7 V 2.3 V POWER-ON RESET – VDD VRES_ON Power On Reset Threshold VDD rising VRES_OFF Power Off Threshold VDD falling 2.2 1.9 2 0.9 1 V LX OUTPUT DRIVER fosc LX Switching Frequency with Internal Oscillator fsync LX Switching Frequency when Externally Synchronized at NSYNC ton-min Minimum On-Time toff-min 1.1 MHz f (NSYNC) - FB1 = 0V, I(LX) > Ilim(LX) 60 ns Minimum Off-time (≥ Maximum Duty Cycle) FB1 = 0V, I(LX) < Ilim(LX) 60 ns Ron LX On-Resistance I(LX) = 100mA 0.4 Ω Ileak LX Leakage Current NEN = VDD, V(LX) = 30V Ipeak LX Peak Current Limit t > 8.32ms (end of soft-start) 1 5 1200 µA mA SCHOTTKY DIODE – LX, VOUT Vdiode Forward Voltage from LX to VOUT I = 10mA, TA = +25°C 0.4 0.5 0.6 V I = 10mA, TA = -40°C to +85°C 0.3 0.5 0.7 V SEL = GND, TA = +25°C 1.13 1.15 1.17 V SEL = GND, TA = -40°C to +85°C 1.12 1.15 1.18 v SEL = VDD, TA = +25°C 1.135 1.15 1.165 V SEL = GND, TA = -40°C to +85°C 1.125 1.15 1.175 V FEEDBACK INPUTS AND SELECTION – FB0, FB1, SEL VrefFB0 VrefFB1 Input Reference Voltage on FB0 Input Reference Voltage on FB1 IFB0 Input Current in FB0 SEL = GND, FB0 = 1.3V -0.2 0.2 µA IFB1 Input Current in FB1 SEL = VDD, FB1 = 1.3V -0.2 0.2 µA 3 FN7462.0 October 13, 2005 ISL97702 Electrical Specifications VDD = 3.6V, GND = NEN = 0V, SEL = NSYNC = VDD, R1 = 390K, R2 = 39K, R3 = 26.1K, L = 10µH, TA = -40°C to +85°C unless otherwise stated (Continued) PARAMETER DESCRIPTION CONDITION MIN TYP MAX UNIT RFB0 FB0 Pull-Down Switch Resistance SEL = VDD, IFB0 = 10mA 15 25 Ω RFB1 FB1 Pull-Down Switch Resistance SEL = GND, IFB1 = 10mA 15 25 Ω 1400 kHz 100 ns SYNCHRONIZATION INPUT – NSYNC fNSYNC External Sync. Frequency Range tdNSYNC NSYNC Falling Edge to LX Falling Edge Delay 600 fNSYNC = 600kHz 80 OVERVOLTAGE DETECTOR - VOUT VOUT Overvoltage Threshold FB1 = GND 31 35 V t > 2.048ms, DC current 800 mA OVERCURRENT DETECTOR IOCTVDDOUT Overcurrent Threshold OVER-TEMPERATURE DETECTOR toff Shut-Down Temperature Threshold T rising 135 °C ton Turn-On Temperature Threshold T falling 100 °C Ω FAULT SWITCH – VDD, VDDOUT RonFS On-Resistance from VDD to VDDOUT IOUT = 50mA, t > 2.048ms 0.2 IleakVDDOUT Leakage Current VDDOUT = 0V 0.01 ISS_VDDOUT Soft Inrush Current Source at VDDOUT VDD-VDDOUT = 0.5V, ton < 2.048ms Output Voltage Accuracy, Assuming Resistor Divider Tolerances of 0.1% or Better IOUT = 10mA, TA = +25°C -1.5 1.5 % IOUT = 10mA, TA = -40°C to +85°C -2.5 2.5 % ∆VOUT/∆IOUT Load Regulation IOUT = 0mA to 50mA 0.05 % ∆VOUT/∆VDD Line Regulation VDD = 3.6V to 2.6V, IOUT = 30mA 0.1 %/V 3 50 µA mA REGULATION ACC 4 FN7462.0 October 13, 2005 ISL97702 Typical Performance Curves 90 90 4.2V 4.2V 85 80 EFFICIENCY (%) EFFICIENCY (%) 85 3.6V 2.7V 75 80 3.6V 2.7V 75 70 70 65 65 0 50 100 0 150 50 100 150 IOUT (mA) LOAD CURRENT (mA) FIGURE 2. EFFICIENCY vs LOAD CURRENT(VOUT = 18.3V) L = 10µH (CDRH4D28C-100NC) C = 6.6µF FIGURE 3. EFFICIENCY vs IOUT (VOUT = 18.3V) L = 6.8µH (TDK RLF7030) C = 6.6µF 90 90 4.2V 4.2V 85 EFFICIENCY (%) EFFICIENCY (%) 85 3.6V 80 2.7V 75 70 3.6V 80 2.7V 75 70 65 65 0 50 100 150 IOUT (mA) FIGURE 4. EFFICIENCY vs IOUT(VOUT = 12.6V) L = 6.8µH (TDK RLF7030) C = 6.6µF FIGURE 6. START-UP TO 12V @ SEL = 0 (VDD=3.6V, RL=360Ω) 5 200 0 50 100 150 200 IOUT (mA) FIGURE 5. EFFICIENCY vs IOUT (VOUT = 12.7V) L = 10µH (CDRH4D28C-100NC) C = 6.6µF FIGURE 7. START-UP TO 18V @ SEL = 1 (VDD=3.6V, RL=360Ω) FN7462.0 October 13, 2005 ISL97702 Typical Performance Curves (Continued) FIGURE 9. 18V->12V TRANSITION (VDD=3.6V, RL=360Ω) FIGURE 8. 12V->18V TRANSITION (VDD=3.6V, RL=360Ω) FIGURE 10. SHUT DOWN @ SEL = 1 (VDD=3.6V, RL=360Ω) 6 FN7462.0 October 13, 2005 ISL97702 Typical Performance Curves (Continued) 18.20 18.29 18.19 18.28 18.18 18.27 18.16 VOUT (V) VOUT (V) 18.17 18.15 18.14 18.13 18.26 18.25 18.12 18.11 18.24 18.10 18.09 0 50 100 18.23 2.6 150 3.1 LOAD CURRENT (mA) 3.6 4.1 4.6 5.1 VIN (V) FIGURE 11. LOAD REGULATION (VIN = 3.6V) FIGURE 12. LINE REGULATION (IOUT = 30mA) 1000 800 600 400 200 0 0 1 2 3 4 5 6 VIN (V) (CH1 = VOUT; CH4 = iL; CH2 = IOUT) FIGURE 14. TRANSIENT RESPONSE (VIN = 3.3V; VOUT = 18.3V; STEP LOAD CURRENT FROM 2.6mA TO 70mA) FIGURE 13. QUIESCENT CURRENT vs VIN 3.2 2.9 2.6 POUT (W) QUIESCENT CURRENT (µA) 1200 2.3 2.0 1.7 1.4 1.1 0.8 0.5 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 VIN (V) FIGURE 15. RECOMMENDED MAXIMUM OUTPUT POWER vs INPUT VOLTAGE 7 FN7462.0 October 13, 2005 ISL97702 Description of Operation Pin Descriptions Enable Pin (active low) - NEN PIN NUMBER PIN NAME 1 GND 2 VDDOUT 3 VDD 4 NSYNC 5 FB0 Feedback Input 0 6 FB1 Feedback Input 1 7 SEL Select Input 8 NEN Enable Input (Active Low) 9 VOUT Boost Output Voltage 10 LX PIN FUNCTION Ground Protection Switch Output Supply Input Synchronization Input (Falling Edge) Boost FET Function Overview The ISL97702 is a high frequency, high efficiency boost regulator which operates in constant frequency PWM mode. The boost converter generates a stable, higher output voltage from a variable, low voltage input source (e.g. Li-Ion battery). Two output voltage levels are pin selectable with values defined from the feedback resistor network. The switching frequency is either generated from the fixed 1MHz internal oscillator or provided externally at the synchronization pin in the range from 600kHz to 1.4MHz. The compensation network and soft-start functions are built in with fixed parameters without any need for further external components. If NEN is high the ISL97702 shuts down all its internal functions and deactivates its I/Os. Only the internal pull-up resistor at NEN remains active. If NEN is high the input disconnect switch between VDD and VDDOUT interrupts the circuit path from the input voltage VDD through inductor and diode to the output load at VOUT. If shut down the total supply current in VDD is typically less than 0.1µA. When NEN is driven low the ISL97702 begins with the startup sequence. Start-Up Sequence After pin NEN is pulled low or a restart is triggered from Fault Control during operation, the ISL97702 goes through a startup sequence with the following six states: Soft Inrush -> VDDOUT Enable -> Soft Boost 25 -> Soft Boost 50 -> Soft Boost 75 -> Normal. If the sequence has completed, the ISL97702 stays in the “Normal” state until NEN is high again or any fault is detected. Soft Inrush: State Duration ~2.048ms The switch at VDDOUT is configured as current source and provides a limited current through the inductor to pre-charge the capacitor at VOUT. VDDOUT Enable: State Duration ~128µs The switch at VDDOUT is fully enabled and connects the inductor to VDD with a low on-resistance. Soft Boost 25 -> 50 -> 75: State Duration 3x ~2.048ms To stop battery discharge into the output load when disabled the inductor is disconnected from the input supply with a low on resistance power switch. The boost regulator begins to switch at LX. Built in fault protection monitors inductor current and output voltage as well as junction temperature in order to interrupt the high current circuit path through the inductor and diode in the event of a load failure. Normal Low logic input thresholds allow the ISL97702 to interface directly to micro controllers with lower supply voltage. Alternatively the internal pull-up resistors on all logic inputs provide level shifting when driven from open collector outputs. 8 The LX current limit increases in three steps representing 25%, 50% 75% of its final value. If no fault was detected Normal state is entered ~8.256ms after NEN is pulled low. The LX current limit steps up to 100%. In all states Fault Control can force the sequence to restart or even to shut down (see Table 1). FN7462.0 October 13, 2005 ISL97702 If NSYNC is tied to VDD the internal oscillator defines Dmax to: Dmax(fosc) = 1 - toff(LX)min*fosc With external synchronization at pin NSYNC Dmax(NSYNC) = 1 - toff(LX)min*f(NSYNC) The duty cycle at LX can be 0% (pulse skipping), if the output voltage exceeds the target voltage set with the feedback resistors. Internal Schottky Diode – LX, VOUT The inductor node LX internally connects to the power FET and to the anode of the integrated power Schottky diode. The cathode of the diode is pin VOUT. An overvoltage detector at VOUT continuously monitors the cathode voltage and immediately disables the boost regulator if the voltage exceeds the maximum allowable voltage. FIGURE 16. Fault Control Feedback Input Pins – FB0, FB1 The input voltage at VDD, current in the VDDOUT switch, voltage at VOUT and junction temperature Tj are continuously monitored and can either restart the start-up sequence or in some cases disable the ISL97702 boost function as long as the fault is present. Each feedback pin is either configured as feedback input pin or as ground reference output pin for the external feedback resistor chain. Configured as output the feedback pin is switched to the internal reference ground via a low Ron MOS transistor to achieve maximum accuracy of the regulated output voltage. A current limit at FB0 and FB1 prevents overloading in a fault condition. TABLE 1. FAULT PROTECTION FAULT DESCRIPTION Undervoltage at VDD Overcurrent drawn from VDDOUT FAULT CONDITION V(VDD) < V(VDD)off ISL97702 FAULT REACTION Disables I/Os and waits until V(VDD) reaches V(VDD)on to begin with the start-up sequence I(VDDOUT) > Disables VDDOUT switch It(VDDOUT)err and LX driver and immediately restarts the start-up sequence Overvoltage at VOUT V(VOUT) > Vt(VOUT)err Disables VDDOUT switch and LX driver and waits until output voltage V(VOUT) drops to Vt(VOUT) to restart the start-up sequence Over Temperature on chip Tj > Toff Disables VDDOUT switch and LX driver and waits until junction temp drops to “Ton” to restart the start-up sequence TABLE 2. PIN FEEDBACK CONFIGURATION DEPENDENT ON SEL SEL FB0 FB1 0 Feedback Input Ground Reference Output 1 Ground Reference Output Feedback Input External Synchronization Pin - NSYNC Pin NSYNC can be used to synchronize the LX output pin with an external clock signal in the range from 600kHz to 1.4MHz. A frequency detector monitoring NSYNC enables external synchronization if f(NSYNC) is higher than about 300kHz. If the pin is e.g. static high the internal oscillator defines the LX output frequency and phase. When externally synchronized all falling edges at LX are timed from the falling edge of the clock signal applied at NSYNC. The timing of the rising edge at LX is defined by the boost controller. Maximum Duty Cycle – LX The maximum duty cycle Dmax, at which the power FET can operate defines the upper limit of the regulator output to input voltage ratio according to the formula: VOUT/VIN = 1/ (1-Dmax). In the ISL97702, Dmax is defined from the minimum off-time toff(LX)min and the switching frequency. 9 FN7462.0 October 13, 2005 ISL97702 FIGURE 17. NSYNC TO LX SYNCHRONIZATION DELAY FIGURE 18. LX SYNCHRONIZATION WITH f(SYNC) = 600kHz FIGURE 19. LX SYNCHRONIZATION WITH f(SYNC) = 1.4MHz 10 FN7462.0 October 13, 2005 ISL97702 C7 3.3µF/50V C3 OPEN R1 390K R2 OPEN L1 J2 J7 VOUT C6 1nF/50V C8 100n J3 6.8µH U1 VDD_IN VDD J4 VDD 100n C9 4.7µ/10V C2 10µ 2 3 4 5 R4 OPEN FB0 FB1 R3 R5 OPEN 26.1K C4 OPEN C5 VDD OPEN J6 J1 2 VDD 6 NEN J5 J2 2 ISL97702 JP3 GND_OUT 1 C1 J1 R6 39K LX 10 VDDOUT VOUT 9 8 VDD NEN SEL 7 NSYNC GND 3 1 1 GND_IN SEL 3 NSYNC FIGURE 20. ISL97702 APPLICATION BOARD Typical Application Typical applications are passive- or active-matrix organic light emitting diode displays (PMOLED, AMOLED) in handheld devices. Applications with low power or screen saver/ reduced brightness modes are also directly supported. Motivation: In the low power mode the OLED display brightness (~pixel current) is reduced so that the display drivers can operate with equally reduced power. Usually the supply voltage is kept at the same level, although the pixel voltage drops by several volts when the pixel current levels are reduced. Here a further power reduction can be achieved if the supply voltage for the display drivers is reduced according to the pixel diode characteristic. The ISL97702 allows selection between a nominal and a reduced output voltage level in order to supply more effectively OLED display drivers. 1 I LPK = I LAVG + --- ⋅ ∆I L 2 (EQ. 2) V IN ⋅ ( V OUT – V IN ) ∆I L = --------------------------------------------------L ⋅ V OUT ⋅ f OSC (EQ. 3) Where: • ∆IL is the peak-to-peak inductor current ripple in Amperes • L inductance in H • fOSC switching frequency, typically 1.0MHz Optimal combination of the boost inductor L and the output capacitor Cout are listed in table: CAPACITOR (µF) INDUCTOR (µH) MIN MAX 4.7 2.2 10 6.8 3.3 10 10 4.7 10 15 6.8 10 Components Selection The input capacitance is normally 10µf~15µF and the output capacitor is 3.3µf to 6.6µF. X5R or X7R type of ceramic capacitor with correct voltage rating is recommended. The output capacitor value will affect the output voltage ripple. Higher value of the output capacitor, lower ripple of the output voltage. When choosing an inductor, make sure the inductor can handle the average and peak currents given by following formulas (80% efficiency assumed): I OUT ⋅ V OUT I LAVG = ---------------------------------0.8 ⋅ V IN (EQ. 1) 11 Recommended Inductor and Ceramic capacitor manufactures are listed in the following table: INDUCTOR CERAMIC CAPACITOR Sumida: www.sumida.com Taiyo Yuden: www.t-yuden.com TDK: www.tdk.co.jp AVX: www.avxcorp.com Toko: www.tokoam.com Murata: www.murata.com FN7462.0 October 13, 2005 ISL97702 PCB layout Considerations The layout is very important for the converter to function properly. To ensure the high pulse current in the power ground does not interfere with the sensitive feedback signals, the current loops (VIN-L1-LX-GND, and VIN-L1VOUT-COUT-GND) should be as short as possible. For the DFN package, there is no separated GND. All return GNDs should be connected in GND pin but with no sharing branch. The heat of the IC is mainly dissipated through the thermal pad. Maximizing the copper area connected to the thermal pad is preferable. In addition, a solid ground plane is helpful for the EMI performance. The demo board is a good example layout based on the principle. The overview, top layer and bottom layer of the demo board layout are shown in Figures 21, 22 and 23. Demo Board Layout FIGURE 21. OVERVIEW of DEMO BOARD FIGURE 22. BOTTOM LAYER of the DEMO BOARD FIGURE 23. TOP LAYER of the DEMO BOARD 12 FN7462.0 October 13, 2005 ISL97702 DFN Package Outline Drawing NOTE: The package drawings shown here may not be the latest versions. To check the latest revision, please refer to the Intersil website at http://www.intersil.com/design/packages/index.asp All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 13 FN7462.0 October 13, 2005