Preliminary
Direct RDRAM™
K4R271669D
128Mbit RDRAM(D-die)
256K x 16 bit x 32s Banks
Direct RDRAMTM
Version 1.0
December 2001
Page -1
Version 1.0 Dec. 2001
Preliminary
Direct RDRAM™
K4R271669D
Change History
Version 1.0 ( December 2001 ) - Preliminary
* Based on the Rambus RDRAMs for short channel Datasheet 0.97 ver.
Page 0
Version 1.0 Dec. 2001
Preliminary
Direct RDRAM™
K4R271669D
Overview
The Rambus Direct RDRAM™ is a general purpose highperformance memory device suitable for use in a broad
range of applications including communications, graphics,
video, and any other application where high bandwidth and
low latency are required.
SAMSUNG 001
K4R271669D-TCxx
The 128Mbit Direct Rambus DRAMs (RDRAM) are
extremely high-speed CMOS DRAMs organized as 8M
words by 16. The use of Rambus Signaling Level (RSL)
technology permits to 800MHz transfer rates while using
conventional system and board design technologies. Direct
RDRAM devices are capable of sustained data transfers at
1.25 ns per two bytes (10ns per sixteen bytes).
The architecture of the Direct RDRAMs allows the highest
sustained bandwidth for multiple, simultaneous randomly
addressed memory transactions. The separate control and
data buses with independent row and column control yield
over 95% bus efficiency. The Direct RDRAM's 32 banks
support up to four simultaneous transactions.
Figure 1: Direct RDRAM CSP Package
System oriented features for mobile, graphics and communications include power management, byte masking.
The 128Mbit Direct RDRAMs are offered in a horizontal
center-bond fanout CSP.
Key Timing Parameters/Part Numbers
Features
Speed
♦ Highest sustained bandwidth per DRAM device
- 1.6GB/s sustained data transfer rate
- Separate control and data buses for maximized
efficiency
- Separate row and column control buses for
easy scheduling and highest performance
- 32 banks: four transactions can take place simultaneously at full bandwidth data rates
Organization
256Kx16x32sa
I/O
Freq.
MHz
tRAC (Row
Access
Time) ns
Part Number
Bin
-CS8
800
45
K4R271669D-TbCS8
a. “32s” - 32 banks which use a “split” bank architecture.
b. “T” - Lead free consumer package.
♦ Low latency features
- Write buffer to reduce read latency
- 3 precharge mechanisms for controller flexibility
- Interleaved transactions
♦ Advanced power management:
- Multiple low power states allows flexibility in power
consumption versus time to transition to active state
- Power-down self-refresh
♦ Organization: 1Kbyte pages and 32 banks, x 16
- x16 organization for low cost applications
♦ Uses Rambus Signaling Level (RSL) for up to 800MHz
operation
♦ WBGA package(54 Balls)
Page 1
Version 1.0 Dec. 2001
Preliminary
Direct RDRAM™
K4R271669D
Pinouts and Definitions
The following table shows the pin assignments of the centerbonded fanout CSP RDRAM package.
Table 1: Center-Bonded Fanout CSP Device (Top View)
7
DQA7
DQA4
CFM
CFMN
RQ5
RQ3
DQB0
DQB4
DQB7
6
GND
DQA5
DQA2
VDDA
RQ6
RQ2
DQB1
DQB5
GND
5
CMD
VDD
GND
GNDA
VDD
GND
VDD
VDD
SI00
3
SCK
GND
VDD
GND
GND
VDD
GND
GND
SIO1
2
VCMOS
DQA6
DQA1
VREF
RQ7
RQ1
DQB2
DQB6
VCMOS
1
NC
DQA3
DQA0
CTMN
CTM
RQ4
RQ0
DQB3
NC
Top View
A
B
C
D
E
F
G
H
J
4
b. Top marking example
SAMSUNG 001
K4R271669D-TCxx
Top View
Chip
For consumer package, pin #1(ROW 1, COL A) is
located at the A1 position on the top side and the A1
position is marked by the marker “ • “.
Page 2
Version 1.0 Dec. 2001
Preliminary
Direct RDRAM™
K4R271669D
Table 2: Pin Description
Signal
I/O
Type
# Pins
center
SIO1,SIO0
I/O
CMOSa
2
Serial input/output. Pins for reading from and writing to the control registers using a serial access protocol. Also used for power management.
CMD
I
CMOSa
1
Command input. Pins used in conjunction with SIO0 and SIO1 for reading
from and writing to the control registers. Also used for power management.
SCK
I
CMOSa
1
Serial clock input. Clock source used for reading from and writing to the
control registers
VDD
6
Supply voltage for the RDRAM core and interface logic.
VDDa
1
Supply voltage for the RDRAM analog circuitry.
VCMOS
2
Supply voltage for CMOS input/output pins.
GND
9
Ground reference for RDRAM core and interface.
GNDa
1
Ground reference for RDRAM analog circuitry.
Description
DQA7..DQA0
I/O
RSLb
8
Data byte A. Eight pins which carry a byte of read or write data between
the Channel and the RDRAM.
CFM
I
RSLb
1
Clock from master. Interface clock used for receiving RSL signals from
the Channel. Positive polarity.
CFMN
I
RSLb
1
Clock from master. Interface clock used for receiving RSL signals from
the Channel. Negative polarity
1
Logic threshold reference voltage for RSL signals
CTMN
I
RSL
b
1
Clock to master. Interface clock used for transmitting RSL signals to the
Channel. Negative polarity.
CTM
I
RSLb
1
Clock to master. Interface clock used for transmitting RSL signals to the
Channel. Positive polarity.
RQ7..RQ5 or
ROW2..ROW0
I
RSLb
3
Row access control. Three pins containing control and address information for row accesses.
RQ4..RQ0 or
COL4..COL0
I
RSLb
5
Column access control. Five pins containing control and address information for column accesses.
DQB7..
DQB0
I/O
RSLb
8
Data byte B.Eight pins which carry a byte of read or write data between
the Channel and the RDRAM.
NC
2
No Connection.
Total pin count per package
54
VREF
a. All CMOS signals are high-true; a high voltage is a logic one and a low voltage is logic zero.
b. All RSL signals are low-true; a low voltage is a logic one and a high voltage is logic zero.
Page 3
Version 1.0 Dec. 2001
Preliminary
Direct RDRAM™
K4R271669D
RQ7..RQ5 or
ROW2..ROW0
3
DQB7..DQB0
8
RQ4..RQ0 or
COL4..COL0
5
CTM CTMN SCK,CMD SIO0,SIO1 CFM CFMN
2
2
DQA7..DQA0
8
RCLK
RCLK
1:8 Demux
1:8 Demux
TCLK
RCLK
Control Registers
Packet Decode
ROWR
ROWA
11 5
5
9
ROP DR BR
AV
Match
DM
6
R
REFR
Power Modes
Mux
DEVID
Packet Decode
COLC
5
5
5
6
COLX
5
5
XOP DX BX COP DC BC
M
S
Match
Row Decode
Match
C
COLM
8
MB MA
Write
Buffer
XOP Decode
PRER
ACT
8
PREX
Mux
Mux
Column Decode & Mask
Bank 17
Bank 18
Bank 29
Bank 30
Bank 31
•••
8
•••
•••
RCLK
•••
SAmp SAmp SAmp
15
14/15 13/14
SAmp SAmp SAmp
17/18 16/17
16
•••
Bank 16
8:1 Mux
SAmp SAmp SAmp
31
30/31 29/30
Bank 15
8
8
TCLK
Write Buffer
Bank 14
8
1:8 Demux
1:8 Demux
Bank 13
64
Write Buffer
TCLK
Bank 2
SAmp SAmp SAmp
29/30 30/31
31
8:1 Mux
Bank 1
Internal DQA Data Path
SAmp SAmp SAmp
16
16/17 17/18
8
8
Bank 0
64
SAmp SAmp SAmp
13/14 14/15
15
8
8
32x64
RCLK
8
32x64 512x64x128
•••
64
64
RD, WR
PREC
DRAM Core
SAmp SAmp SAmp
0
0/1
1/2
Internal DQB Data Path
SAmp SAmp SAmp
1/2
0/1
0
Sense Amp
32x64
8
Figure 2: 128Mbit(256Kx16x32s) Direct RDRAM Block Diagram
Page 4
Version 1.0 Dec. 2001
Preliminary
Direct RDRAM™
K4R271669D
General Description
24-bit ROWA (row-activate) or ROWR (row-operation)
packet.
Figure 2 is a block diagram of the 128Mbit Direct RDRAM.
It consists of two major blocks: a “core” block built from
banks and sense amps similar to those found in other types
of DRAM, and a Direct Rambus interface block which
permits an external controller to access this core at up to
1.6GB/s.
COL Pins: The principle use of these five pins is to
manage the transfer of data between the DQA/DQB pins and
the sense amps of the RDRAM. These pins are de-multiplexed into a 23-bit COLC (column-operation) packet and
either a 17-bit COLM (mask) packet or a 17-bit COLX
(extended-operation) packet.
Control Registers: The CMD, SCK, SIO0, and SIO1
ACT Command: An ACT (activate) command from an
pins appear in the upper center of Figure 2. They are used to
write and read a block of control registers. These registers
supply the RDRAM configuration information to a
controller and they select the operating modes of the device.
The nine bit REFR value is used for tracking the last
refreshed row. Most importantly, the five bit DEVID specifies the device address of the RDRAM on the Channel.
ROWA packet causes one of the 512 rows of the selected
bank to be loaded to its associated sense amps (two 256 byte
sense amps for DQA and two for DQB).
PRER Command: A PRER (precharge) command from
Clocking: The CTM and CTMN pins (Clock-To-Master)
generate TCLK (Transmit Clock), the internal clock used to
transmit read data. The CFM and CFMN pins (Clock-FromMaster) generate RCLK (Receive Clock), the internal clock
signal used to receive write data and to receive the ROW and
COL pins.
DQA,DQB Pins: These 18 pins carry read (Q) and write
(D) data across the Channel. They are multiplexed/de-multiplexed from/to two 72-bit data paths (running at one-eighth
the data frequency) inside the RDRAM.
Banks: The 16Mbyte core of the RDRAM is divided into
thirty two 0.5Mbyte banks, each organized as 512 rows, with
each row containing 64 dualocts, and each dualoct
containing 16 bytes. A dualoct is the smallest unit of data
that can be addressed.
Sense Amps: The RDRAM contains 34 sense amps. Each
sense amp consists of 512 bytes of fast storage (256 for
DQA and 256 for DQB) and can hold one-half of one row of
one bank of the RDRAM. The sense amp may hold any of
the 512 half-rows of an associated bank. However, each
sense amp is shared between two adjacent banks of the
RDRAM (except for sense amps 0, 15, 16, and 31). This
introduces the restriction that adjacent banks may not be
simultaneously accessed.
RQ Pins: These pins carry control and address information. They are broken into two groups. RQ7..RQ5 are also
called ROW2..ROW0, and are used primarily for controlling
row accesses. RQ4..RQ0 are also called COL4..COL0, and
are used primarily for controlling column accesses.
an ROWR packet causes the selected bank to release its two
associated sense amps, permitting a different row in that
bank to be activated, or permitting adjacent banks to be activated.
RD Command: The RD (read) command causes one of
the 64 dualocts of one of the sense amps to be transmitted on
the DQA/DQB pins of the Channel.
WR Command: The WR (write) command causes a
dualoct received from the DQA/DQB data pins of the
Channel to be loaded into the write buffer. There is also
space in the write buffer for the BC bank address and C
column address information. The data in the write buffer is
automatically retired (written with optional bytemask) to one
of the 64 dualocts of one of the sense amps during a subsequent COP command. A retire can take place during a RD,
WR, or NOCOP to another device, or during a WR or
NOCOP to the same device. The write buffer will not retire
during a RD to the same device. The write buffer reduces the
delay needed for the internal DQA/DQB data path turnaround.
PREC Precharge: The PREC, RDA and WRA
commands are similar to NOCOP, RD and WR, except that
a precharge operation is performed at the end of the column
operation. These commands provide a second mechanism
for performing precharge.
PREX Precharge: After a RD command, or after a WR
command with no byte masking (M=0), a COLX packet may
be used to specify an extended operation (XOP). The most
important XOP command is PREX. This command provides
a third mechanism for performing precharge.
ROW Pins: The principle use of these three pins is to
manage the transfer of data between the banks and the sense
amps of the RDRAM. These pins are de-multiplexed into a
Page 5
Version 1.0 Dec. 2001
Preliminary
Direct RDRAM™
K4R271669D
Packet Format
Figure 3 shows the formats of the ROWA and ROWR
packets on the ROW pins. Table 3 describes the fields which
comprise these packets. DR4T and DR4F bits are encoded to
contain both the DR4 device address bit and a framing bit
which allows the ROWA or ROWR packet to be recognized
by the RDRAM.
The AV (ROWA/ROWR packet selection) bit distinguishes
between the two packet types. Both the ROWA and ROWR
packet provide a five bit device address and a five bit bank
address. An ROWA packet uses the remaining bits to
specify a nine bit row address, and the ROWR packet uses
the remaining bits for an eleven bit opcode field. Note the
use of the “RsvX” notation to reserve bits for future address
field extension.
Table 3: Field Description for ROWA Packet and ROWR Packet
Field
Description
DR4T,DR4F
Bits for framing (recognizing) a ROWA or ROWR packet. Also encodes highest device address bit.
DR3..DR0
Device address for ROWA or ROWR packet.
BR4..BR0
Bank address for ROWA or ROWR packet. RsvB denotes bits ignored by the RDRAM.
AV
Selects between ROWA packet (AV=1) and ROWR packet (AV=0).
R8..R0
Row address for ROWA packet. RsvR denotes bits ignored by the RDRAM.
ROP10..ROP0
Opcode field for ROWR packet. Specifies precharge, refresh, and power management functions.
Figure 3 also shows the formats of the COLC, COLM, and
COLX packets on the COL pins. Table 4 describes the fields
which comprise these packets.
The COLC packet uses the S (Start) bit for framing. A
COLM or COLX packet is aligned with this COLC packet,
and is also framed by the S bit.
The 23 bit COLC packet has a five bit device address, a five
bit bank address, a six bit column address, and a four bit
opcode. The COLC packet specifies a read or write
command, as well as some power management commands.
The remaining 17 bits are interpreted as a COLM (M=1) or
COLX (M=0) packet. A COLM packet is used for a COLC
write command which needs bytemask control. The COLM
packet is associated with the COLC packet from at least
tRTR earlier. An COLX packet may be used to specify an
independent precharge command. It contains a five bit
device address, a five bit bank address, and a five bit opcode.
The COLX packet may also be used to specify some housekeeping and power management commands. The COLX
packet is framed within a COLC packet but is not otherwise
associated with any other packet.
Table 4: Field Description for COLC Packet, COLM Packet, and COLX Packet
Field
Description
S
Bit for framing (recognizing) a COLC packet, and indirectly for framing COLM and COLX packets.
DC4..DC0
Device address for COLC packet.
BC4..BC0
Bank address for COLC packet. RsvB denotes bits reserved for future extension (controller drives 0’s).
C5..C0
Column address for COLC packet. RsvC denotes bits ignored by the RDRAM.
COP3..COP0
Opcode field for COLC packet. Specifies read, write, precharge, and power management functions.
M
Selects between COLM packet (M=1) and COLX packet (M=0).
MA7..MA0
Bytemask write control bits. 1=write, 0=no-write. MA0 controls the earliest byte on DQA7..0.
MB7..MB0
Bytemask write control bits. 1=write, 0=no-write. MB0 controls the earliest byte on DQB7..0.
DX4..DX0
Device address for COLX packet.
BX4..BX0
Bank address for COLX packet. RsvB denotes bits reserved for future extension (controller drives 0’s).
XOP4..XOP0
Opcode field for COLX packet. Specifies precharge, IOL control, and power management functions.
Page 6
Version 1.0 Dec. 2001
Preliminary
Direct RDRAM™
K4R271669D
T0
T1
T2
T3
T8
CTM/CFM
T9
T10
T11
CTM/CFM
ROW2 DR4T DR2 BR0 BR3 RsvR R8
R5
R2
ROW2 DR4T DR2 BR0 BR3
ROW1
DR4F DR1 BR1 BR4 RsvR
R7
R4
R1
ROW1
DR4F DR1 BR1 BR4 ROP9 ROP7 ROP4 ROP1
ROW0
DR3 DR0 BR2 RsvB AV=1 R6
R3
R0
ROW0
DR3 DR0 BR2 RsvB AV=0 ROP6 ROP3 ROP0
ROWA Packet
T0
T1
T2
ROP10 ROP8 ROP5 ROP2
ROWR Packet
T3
T 0 T 1 T 2 T 3 T 4 T 5 T 6 T 7 T 8 T 9 T 10 T 11 T12 T13 T14 T15
CTM/CFM
CTM/CFM
COL4
DC4
S=1
RsvC
C4
COL3
DC3
C5
C3
COL2
DC2 COP1
RsvB BC2
C2
COL1
DC1 COP0
BC4 BC1
C1
COL0
DC0 COP2
COP3 BC3 BC0
C0
ROW2
..ROW0
ACT a0
COL4
..COL0
WR b1
PRER c0
tPACKET
MSK (b1)
PREX d0
DQA8..0
DQB8..0
COLC Packet
T8
T9
T10
T11
CTM/CFM
a
T12
T13
T14
T15
CTM/CFM
COL4
S=1a MA7 MA5 MA3 MA1
COL4
S=1b DX4 XOP4 RsvB BX1
COL3
M=1 MA6 MA4 MA2 MA0
COL3
M=0 DX3 XOP3 BX4 BX0
COL2
MB7 MB4 MB1
COL2
DX2 XOP2 BX3
COL1
MB6 MB3 MB0
COL1
DX1 XOP1 BX2
COL0
MB5 MB2
COL0
DX0 XOP0
The COLM is associated with a
previous COLC, and is aligned
with the present COLC, indicated
by the Start bit (S=1) position.
b The
COLM Packet
COLX Packet
COLX is aligned
with the present COLC,
indicated by the Start
bit (S=1) position.
Figure 3: Packet Formats
Page 7
Version 1.0 Dec. 2001
Preliminary
Direct RDRAM™
K4R271669D
Field Encoding Summary
broadcast operation is indicated when both bits are set.
Broadcast operation would typically be used for refresh and
power management commands. If the device is selected, the
DM (DeviceMatch) signal is asserted and an ACT or ROP
command is performed.
Table 5 shows how the six device address bits are decoded
for the ROWA and ROWR packets. The DR4T and DR4F
encoding merges a fifth device bit with a framing bit. When
neither bit is asserted, the device is not selected. Note that a
Table 5: Device Field Encodings for ROWA Packet and ROWR Packet
DR4T
DR4F
Device Selection
Device Match signal (DM)
1
1
All devices (broadcast)
DM is set to 1
0
1
One device selected
DM is set to 1 if {DEVID4..DEVID0} == {0,DR3..DR0} else DM is set to 0
1
0
One device selected
DM is set to 1 if {DEVID4..DEVID0} == {1,DR3..DR0} else DM is set to 0
0
0
No packet present
DM is set to 0
Table 6 shows the encodings of the remaining fields of the
ROWA and ROWR packets. An ROWA packet is specified
by asserting the AV bit. This causes the specified row of the
specified bank of this device to be loaded into the associated
sense amps.
An ROWR packet is specified when AV is not asserted. An
11 bit opcode field encodes a command for one of the banks
of this device. The PRER command causes a bank and its
two associated sense amps to precharge, so another row or
an adjacent bank may be activated. The REFA (refresh-activate) command is similar to the ACT command, except the
row address comes from an internal register REFR, and
REFR is incremented at the largest bank address. The REFP
(refresh-precharge) command is identical to a PRER
command.
The NAPR, NAPRC, PDNR, ATTN, and RLXR commands
are used for managing the power dissipation of the RDRAM
and are described in more detail in “Power State Management” on page 50. The TCEN and TCAL commands are
used to adjust the output driver slew rate and they are
described in more detail in “Current and Temperature
Control” on page 56.
Table 6: ROWA Packet and ROWR Packet Field Encodings
ROP10..ROP0 Field
DMa
AV
Name
10
9
8
7
6
5
4
3
2:0
-
-
-
-
-
-
-
---
0
-
-
1
1
Row address
Command Description
-
No operation.
ACT
Activate row R8..R0 of bank BR4..BR0 of device and move device to ATTNb.
1
0
1
1
0
0
0
xc
x
x
000
PRER
Precharge bank BR4..BR0 of this device.
1
0
0
0
0
1
1
0
0
x
000
REFA
Refresh (activate) row REFR8..REFR0 of bank BR4..BR0 of device.
Increment REFR if BR4..BR0 = 11111 (see Figure 51).
1
0
1
0
1
0
1
0
0
x
000
REFP
Precharge bank BR4..BR0 of this device after REFA (see Figure 51).
1
0
x
x
0
0
0
0
1
x
000
PDNR
Move this device into the powerdown (PDN) power state (see Figure 48).
1
0
x
x
0
0
0
1
0
x
000
NAPR
Move this device into the nap (NAP) power state (see Figure 48).
1
0
x
x
0
0
0
1
1
x
000
NAPRC
Move this device into the nap (NAP) power state conditionally
1
0
x
x
x
x
x
x
x
0
000
ATTNb
Move this device into the attention (ATTN) power state (see Figure 46).
1
0
x
x
x
x
x
x
x
1
000
RLXR
Move this device into the standby (STBY) power state (see Figure 47).
1
0
0
0
0
0
0
0
0
x
001
TCAL
Temperature calibrate this device (see Figure 54).
1
0
0
0
0
0
0
0
0
x
010
TCEN
Temperature calibrate/enable this device (see Figure 54).
1
0
0
0
0
0
0
0
0
0
000
NOROP
No operation.
a. The DM (Device Match signal) value is determined by the DR4T,DR4F, DR3..DR0 field of the ROWA and ROWR packets. See Table 5.
b. The ATTN command does not cause a RLX-to-ATTN transition for a broadcast operation (DR4T/DR4F=1/1).
c. An “x” entry indicates which commands may be combined. For instance, the three commands PRER/NAPRC/RLXR may be specified in one ROP value (011000111000).
Page 8
Version 1.0 Dec. 2001
Preliminary
Direct RDRAM™
K4R271669D
Table 7 shows the COP field encoding. The device must be
in the ATTN power state in order to receive COLC packets.
The COLC packet is used primarily to specify RD (read) and
WR (write) commands. Retire operations (moving data from
the write buffer to a sense amp) happen automatically. See
Figure 18 for a more detailed description.
The COLC packet can also specify a PREC command,
which precharges a bank and its associated sense amps. The
RDA/WRA commands are equivalent to combining RD/WR
with a PREC. RLXC (relax) performs a power mode transition. See “Power State Management” on page 50.
Table 7: COLC Packet Field Encodings
S
DC4.. DC0
(select device)a
COP3..0 Name
Command Description
0
----
-----
-
No operation.
1
/= (DEVID4 ..0)
-----
-
Retire write buffer of this device.
1
== (DEVID4 ..0)
x000b
NOCOP
Retire write buffer of this device.
1
== (DEVID4 ..0)
x001
WR
Retire write buffer of this device, then write column C5..C0 of bank BC4..BC0 to write buffer.
1
== (DEVID4 ..0)
x010
RSRV
Reserved, no operation.
1
== (DEVID4 ..0)
x011
RD
Read column C5..C0 of bank BC4..BC0 of this device.
1
== (DEVID4 ..0)
x100
PREC
Retire write buffer of this device, then precharge bank BC4..BC0 (see Figure 15).
1
== (DEVID4 ..0)
x101
WRA
Same as WR, but precharge bank BC4..BC0 after write buffer (with new data) is retired.
1
== (DEVID4 ..0)
x110
RSRV
Reserved, no operation.
1
== (DEVID4 ..0)
x111
RDA
Same as RD, but precharge bank BC4..BC0 afterward.
1
== (DEVID4 ..0)
1xxx
RLXC
Move this device into the standby (STBY) power state (see Figur e 47).
a. “/=” means not equal, “==” means equal.
b. An “x” entry indicates which commands may be combined. For instance, the two commands WR/RLXC may be specified in one COP value (1001).
specified without consuming control bandwidth on the ROW
pins. It is also used for the CAL(calibrate) and SAM
(sample) current control commands (see “Current and
Temperature Control” on page 56), and for the RLXX power
mode command (see “Power State Management” on page
50).
Table 8 shows the COLM and COLX field encodings. The
M bit is asserted to specify a COLM packet with two 8 bit
bytemask fields MA and MB. If the M bit is not asserted, an
COLX is specified. It has device and bank address fields,
and an opcode field. The primary use of the COLX packet is
to permit an independent PREX (precharge) command to be
Table 8: COLM Packet and COLX Packet Field Encodings
M
DX4 .. DX0
(selects device)
XOP4..0
Name
Command Description
1
----
-
MSK
MB/MA bytemasks used by WR/WRA.
0
/= (DEVID4 ..0)
-
-
No operation.
0
== (DEVID4 ..0)
00000
NOXOP
No operation.
0
== (DEVID4 ..0)
1xxx0a
PREX
Precharge bank BX4..BX0 of this device (see Figure 15).
0
== (DEVID4 ..0)
x10x0
CAL
Calibrate (drive) IOL current for this device (see Figure 53).
0
== (DEVID4 ..0)
x11x0
CAL/SAM
Calibrate (drive) and Sample ( update) IOL current for this device (see Figure 53).
0
== (DEVID4 ..0)
xxx10
RLXX
Move this device into the standby (STBY) power state (see Figur e 47).
0
== (DEVID4 ..0)
xxxx1
RSRV
Reserved, no operation.
a. An “x” entry indicates which commands may be combined. For instance, the two commands PREX/RLXX may be specified in one XOP value (10010).
Page 9
Version 1.0 Dec. 2001
Preliminary
Direct RDRAM™
K4R271669D
Electrical Conditions
Table 9: Electrical Conditions
Symbol
Parameter and Conditions
Min
Max
Unit
TJ
Junction temperature under bias
-
95
°C
VDD, VDDA
Supply voltage
2.50 - 0.13
2.50 + 0.25
V
VDD,N, VDDA,N
Supply voltage droop (DC) during NAP interval (t
NLIMIT)
-
2.0
%
vDD,N, vDDA,N
Supply voltage ripple (AC) during NAP interval (t
NLIMIT)
-2.0
2.0
%
VCMOSa
Supply voltage for CMOS pins (2.5V controllers)
Supply voltage for CMOS pins (1.8V controllers)
VDD
1.80 - 0.1
VDD
1.80 + 0.2
V
V
VREF
Reference voltage
1.40- 0.2
1.40 + 0.2
V
VDIL
RSL data input - low voltage
VREF - 0.5
VREF - 0.2
V
VREF + 0.2
VREF + 0.5
V
voltageb
VDIH
RSL data input - high
VDIS
RSL data input swing: VDIS = VDIH - VDIL
0.4
1.0
V
RDA
RSL data asymmetry: RDA = (VDIH - VREF) / (VREF - VDIL)
0.67
1.00
-
VCM
RSL clock input - common mode VCM = (VCIH+VCIL)/2
1.3
1.8
V
VCIS,CTM
RSL clock input swing: VCIS = VCIH - VCIL (CTM,CTMN pins).
0.35
1.00
V
VCIS,CFM
RSL clock input swing: VCIS = VCIH - VCIL (CFM,CFMN pins).
0.225
1.00
V
0.3c
VCMOS/2 - 0.25
V
VCMOS/2 + 0.25
VCMOS+0.3d
V
VIL,CMOS
VIH,CMOS
CMOS input low voltage
-
CMOS input high voltage
a. VCMOS must remain on as long as VDD is applied and cannot be turned off.
b. VDIH is typically equal to V TERM (1.8V±0.1V) under DC conditions in a system.
c. Voltage undershoot is limited to -0.7V for a duration of less than 5ns.
d. Voltage overshoot is limited toVCMOS +0.7V for a duration of less than 5ns.
Page 10
Version 1.0 Dec. 2001
Preliminary
Direct RDRAM™
K4R271669D
Electrical Characteristics
Table 10: Electrical Characteristics
Symbol
Parameter and Conditions
ΘJC
Junction-to-Case thermal resistance
IREF
VREF current @ VREF,MAX
IOH
RSL output high current @ (0≤VOUT≤VDD)
VDD,MIN , TJ,MAXa
IALL
RSL IOL current @ VOL = 0.9V,
∆IOL
RSL IOL current resolution step
rOUT
Dynamic output impedance @ VOL= 0.9V
b,c
IOL
RSL IOL current @ VOL = 1.0V
II,CMOS
CMOS input leakage current @ (0≤VI,CMOS≤VCMOS)
VOL,CMOS
CMOS output voltage @ IOL,CMOS= 1.0mA
VOH,CMOS
CMOS output high voltage @ IOH,CMOS = -0.25mA
Min
Max
Unit
-
0.5
°C/Watt
-10
10
µA
-10
10
µA
30.0
90.0
mA
-
2.0
mA
150
-
Ω
26.6
30.6
mA
-10.0
10.0
µA
-
0.3
V
VCMOS-0.3
-
V
a. This measurement is made in manual current control mode; i.e. with all output device legs sinking current.
b. This measurement is made in automatic current control mode after at least 64 current control calibration operations to a device and after CCA and
CCB are initialized to a value of 64. This value applies to all DQA and DQB pins.
c. This measurement is made in automatic current control mode in a 25Ω test system with VTERM= 1.714V and VREF= 1.357V and with the ASYMA
and ASYMB register fields set to 0.
Page 11
Version 1.0 Dec. 2001
Preliminary
Direct RDRAM™
K4R271669D
Timing Conditions
Table 11: Timing Conditions
Symbol
Parameter
Min
Max
Unit
Figure(s)
tCYCLE
CTM and CFM cycle times (-800)
2.50
3.83
ns
Figure 55
tCR, tCF
CTM and CFM input rise and fall times. Use the minimum value of these
parameters during testing.
0.2
0.5
ns
Figure 55
tCH, tCL
CTM and CFM high and low times
40%
60%
tCYCLE
Figure 55
tTR
CTM-CFM differential (MSE/MS=0/0)
CTM-CFM differential (MSE/MS=1/1) a
0.0
0.9
1.0
1.0
tCYCLE
Figure 43
Figure 55
tDCW
Domain crossing window
-0.1
0.1
tCYCLE
Figure 61
tDR, tDF
DQA/DQB/ROW/COL input rise/fall times (20% to 80%). Use the minimum value of these parameters during testing.
0.2
0.65
ns
Figure 56
tS, tH
DQA/DQB/ROW/COL-to-CFM setup/hold @ t CYCLE=2.50
0.250b
-
ns
Figure 56
tDR1, tDF1
SIO0, SIO1 input rise and fall times
-
5.0
ns
Figure 58
tDR2, tDF2
CMD, SCK input rise and fall times
-
2.0
ns
Figure 58
tCYCLE1
SCK cycle time - Serial control register transactions
1000
-
ns
Figure 58
10
-
ns
Figure 58
SCK cycle time - Power transitions
tCH1, tCL1
SCK high and low times
4.25
-
ns
Figure 58
tS1
CMD setup time to SCK rising or falling edgec
1.25
-
ns
Figure 58
tH1
CMD hold time to SCK rising or falling edgec
1
-
ns
Figure 58
tS2
SIO0 setup time to SCK falling edge
40
-
ns
Figure 58
tH2
SIO0 hold time to SCK falling edge
40
-
ns
Figure 58
tS3
PDEV setup time on DQA5..0 to SCK rising edge.
0
-
ns
Figure 49
tH3
PDEV hold time on DQA5..0 to SCK rising edge.
5.5
-
ns
Figure 59
tS4
ROW2..0, COL4..0 setup time for quiet window
-1
-
tCYCLE
Figure 49
tH4
ROW2..0, COL4..0 hold time for quiet window
d
5
-
tCYCLE
Figure 49
tNPQ
Quiet on ROW/COL bits during NAP/PDN entry
4
-
tCYCLE
Figure 48
tREADTOCC
Offset between read data and CC packets (same device)
12
-
tCYCLE
Figure 53
tCCSAMTOREAD
Offset between CC packet and read data (same device)
8
-
tCYCLE
Figure 53
tCE
CTM/CFM stable before NAP/PDN exit
2
-
tCYCLE
Figure 49
tCD
CTM/CFM stable after NAP/PDN entry
100
-
tCYCLE
Figure 48
tFRM
ROW packet to COL packet ATTN framing delay
7
-
tCYCLE
Figure 47
tNLIMIT
Maximum time in NAP mode
10.0
µs
Figure 46
tREF
Refresh interval
32
ms
Figure 51
tBURST
Interval after PDN or NAP (with self-refresh) exit in which all banks of
the RDRAM must be refreshed at least once.
200
µs
Figure 52
Page 12
Version 1.0 Dec. 2001
Preliminary
Direct RDRAM™
K4R271669D
Table 11: Timing Conditions
Symbol
Parameter
tCCTRL
Current control interval
Min
Max
Unit
Figure(s)
34 tCYCLE
100ms
ms/tCY-
Figure 53
CLE
tTEMP
Temperature control interval
tTCEN
TCE command to TCAL command
tTCAL
TCAL command to quiet window
tTCQUIET
Quiet window (no read data)
tPAUSE
RDRAM delay (no RSL operations allowed)
100
ms
Figure 54
150
-
tCYCLE
Figure 54
2
2
tCYCLE
Figure 54
140
-
tCYCLE
Figure 54
200.0
µs
page 38
a. MSE/MS are fields of the SKIP register. For this combination (skip
override) the tDCW parameter range is effectively 0.0 to 0.0.
b. tS,MIN and tH,MIN for other tCYCLE values can be interpolated
between or extrapolated from the timings at the 3 specified tCYCLE
values.
c. With VIL,CMOS =0.5VCMOS-0.4V and VIH,CMOS=0.5VCMOS+0.4V
d. Effective hold becomes tH4’=t H4+[PDNXA•64•tSCYCLE+tPDNXB,MAX]-[PDNX•256•tSCYCLE]
if [PDNX•256•tSCYCLE] < [PDNXA•64•tSCYCLE+tPDNXB,MAX]. See
Figure 49.
Page 13
Version 1.0 Dec. 2001
Preliminary
Direct RDRAM™
K4R271669D
Timing Characteristics
Table 12: Timing Characteristics
Symbol
Parameter
Min
Max
Unit
Figure(s)
tQ
CTM-to-DQA/DQB output time @ tCYCLE=2.50ns
-0.310
+0.310
ns
Figure 57
tQR, tQF
DQA/DQB output rise and fall times
0.2
0.45
ns
Figure 57
tQ1
SCK(neg)-to-SIO0 delay @ CLOAD,MAX = 20pF (SD read data valid).
-
10
ns
Figure 60
tHR
SCK(pos)-to-SIO0 delay @ CLOAD,MAX = 20pF (SD read data hold).
2
-
ns
Figure 60
tQR1, tQF1
SIOOUT rise/fall @ C LOAD,MAX = 20pF
-
5
ns
Figure 60
tPROP1
SIO0-to-SIO1 or SIO1-to-SIO0 delay @ CLOAD,MAX = 20pF
-
10
ns
Figure 60
tNAPXA
NAP exit delay - phase A
-
50
ns
Figure 49
tNAPXB
NAP exit delay - phase B
-
40
ns
Figure 49
tPDNXA
PDN exit delay - phase A
-
4
µs
Figure 49
tPDNXB
PDN exit delay - phase B
-
9000
tCYCLE
Figure 49
tAS
ATTN-to-STBY power state delay
-
1
tCYCLE
Figure 47
tSA
STBY-to-ATTN power state delay
-
0
tCYCLE
Figure 47
tASN
ATTN/STBY-to-NAP power state delay
-
8
tCYCLE
Figure 48
tASP
ATTN/STBY-to-PDN power state delay
-
8
tCYCLE
Figure 48
Page 14
Version 1.0 Dec. 2001
Preliminary
Direct RDRAM™
K4R271669D
Timing Parameters
Table 13: Timing Parameter Summary
Min
-45
-800
Max
Units
Figure(s)
Row Cycle time of RDRAM banks -the interval between ROWA packets with
ACT commands to the same bank.
28
-
tCYCLE
Figure 16
Figure 17
tRAS
RAS-asserted time of RDRAM bank - the interval between ROWA packet with
ACT command and next ROWR packet with PRER a command to the same bank.
20
64µsb
tCYCLE
Figure 16
Figure 17
tRP
Row Precharge time of RDRAM banks - the interval between ROWR packet
with PRER a command and next ROWA packet with ACT command to the same
bank.
8
-
tCYCLE
Figure 16
Figure 17
tPP
Precharge-to-precharge time of RDRAM device - the interval between successive ROWR packets with PRER a commands to any banks of the same device.
8
-
tCYCLE
Figure 13
tRR
RAS-to-RAS time of RDRAM device - the interval between successive ROWA
packets with ACT commands to any banks of the same device.
8
-
tCYCLE
Figure 14
tRCD
RAS-to-CAS Delay - the interval from ROWA packet with ACT command to
COLC packet with RD or WR command). Note - the RAS-to-CAS delay seen by
the RDRAM core (tRCD-C) is equal to t RCD-C = 1 + tRCD because of differences
in the row and column paths through the RDRAM interface.
9
-
tCYCLE
Figure 16
Figure 17
tCAC
CAS Access delay - the interval from RD command to Q read data. The equation
for tCAC is given in the TPARM register in Figure 40.
8
12
tCYCLE
Figure 5
Figure 40
tCWD
CAS Write Delay (interval from WR command to D write data.
6
6
tCYCLE
Figure 5
tCC
CAS-to-CAS time of RDRAM bank - the interval between successive COLC
commands).
4
-
tCYCLE
Figure 16
Figure 17
tPACKET
Length of ROWA, ROWR, COLC, COLM or COLX packet.
4
4
tCYCLE
Figure 3
tRTR
Interval from COLC packet with WR command to COLC packet which causes
retire, and to COLM packet with bytemask.
8
-
tCYCLE
Figure 18
tOFFP
The interval (offset) from COLC packet with RDA command, or from COLC
packet with retire command (after WRA automatic precharge), or from COLC
packet with PREC command, or from COLX packet with PREX command to the
equivalent ROWR packet with PRER. The equation for tOFFP is given in the
TPARM register in Figure 40.
4
4
tCYCLE
Figure 15
Figure 40
tRDP
Interval from last COLC packet with RD command to ROWR packet with
PRER.
4
-
tCYCLE
Figure 16
tRTP
Interval from last COLC packet with automatic retire command to ROWR packet
with PRER.
4
-
tCYCLE
Figure 17
Parameter
Description
tRC
a. Or equivalent PREC or PREX command. See Figure 15.
b. This is a constraint imposed by the core, and is therefore in units of µs rather than tCYCLE.
Page 15
Version 1.0 Dec. 2001
Preliminary
Direct RDRAM™
K4R271669D
Absolute Maximum Ratings
Table 14: Absolute Maximum Ratings
Symbol
Parameter
Min
Max
Unit
VI,ABS
Voltage applied to any RSL or CMOS pin with respect to Gnd
- 0.3
VDD+0.3
V
VDD,ABS, VDDA,ABS
Voltage on VDD and VDDA with respect to Gnd
- 0.5
VDD+1.0
V
TSTORE
Storage temperature
- 50
100
°C
IDD - Supply Current Profile
Table 15: Supply Current Profile
Min
Max
-45
-800
Unit
Device in PDN, self-refresh enabled and INIT.LSR=0.
-
5000
µA
IDD,NAP
Device in NAP.
-
4
mA
IDD,STBY
Device in STBY. This is the average for a device in STBY with (1) no packets on the Channel, and (2) with packets sent to other devices.
-
75
mA
IDD,REFRESH
Device in STBY and refreshing rows at the tREF,MAX period.
-
75
mA
IDD,ATTN
Device in ATTN. This is the average for a device in ATTN with (1) no packets on the Channel, and (2) with packets sent to other devices.
-
115
mA
IDD,ATTN-W
Device in ATTN. ACT command every 8•t CYCLE, PRE command every 8•tCYCLE, WR
command every 4•tCYCLE, and data is 1100..1100
-
500
mA
IDD,ATTN-R
Device in ATTN. ACT command every 8•t CYCLE, PRE command every 8•tCYCLE, RD
command every 4•tCYCLE, and data is 1111..1111b
-
480
mA
I DD value
RDRAM Power State and Steady-State Transaction Ratesa
IDD,PDN
a. CMOS interface consumes power in all power states.
b. This does not include the IOL sink current. The RDRAM dissipates IOL•VOL in each output driver when a logic one is driven.
Table 16: Supply Current at Initialization
Symbol
Parameter
Allowed Range of t CYCLE
VDD
Min
Max
Unit
IDD,PWRUP,D
IDD from power -on to SETR
3.33ns to 3.83ns
2.50ns to 3.32ns
VDD,MIN
-
150a
200
mA
IDD,SETR,D
IDD from SETR to CLRR
3.33ns to 3.83ns
2.50ns to 3.32ns
VDD,MIN
-
250
332
mA
a.The supply current will be 150mA when tCYCLE is in the range 15ns
to 1000ns.
Page 16
Version 1.0 Dec. 2001
Preliminary
Direct RDRAM™
K4R271669D
Capacitance and Inductance
Table 17: RSL Pin Parasitics
Symbol
Parameter and Conditions - RSL pins
Min
Max
Unit
Figure
LI
RSL effective input inductance
4.0
nH
Figure 62
L12
Mutual inductance between any DQA or DQB RSL signals
0.6
nH
Figure 62
Mutual inductance between any ROW or COL RSL signals
0.6
∆LI
Difference in LI value between any RSL pins of a single device.
CI
RSL effective input capacitance a
C12
Mutual capacitance between any RSL signals.
∆CI
Difference in C I value between average of {CTM, CTMN, CFM,
CFMN} and any RSL pins of a single device
RI
RSL effective input resistance
-
2.0
nH
Figure 62
2.0
2.6
pF
Figure 62
-
0.2
pF
Figure 62
0.12
pF
Figure 62
18
Ω
Figure 62
4
a. This value is a combination of the device IO circuitry and package capacitances measured at VDD=2.5V and f=400MHz with pin biased at 1.4V.
Table 18: CMOS Pin Parasitics
Symbol
LI ,CMOS
CI ,CMOS
CI ,CMOS,SIO
Parameter and Conditions - CMOS pins
Min
Max
Unit
Figure
8.0
nH
Figure 62
1.7
2.1
pF
-
7.0
pF
CMOS effective input inductance
a
CMOS effective input capacitance (SCK,CMD)
CMOS effective input capacitance (SIO1,
SIO0)a
a. This value is a combination of the device IO circuitry and package capacitances.
Page 17
Version 1.0 Dec. 2001
Preliminary
Direct RDRAM™
K4R271669D
Center-Bonded Fanout Package
(54 Balls)
Figure 4 shows the form and dimensions of the recommended package for the center-bonded Fanout CSP device
class.
D
A
B
C
D
E
F
G
H
Bottom
J
Top
Bottom
1
2
3
A
4
5
e2
6
7
d
Bottom
e1
E
E1
Figure 4: Center-Bonded Fanout CSP Package
Table 19 lists the numerical values corresponding to dimensions shown in Figure 4
Table 19: Center-Bonded Fanout CSP Package Dimension
Symbol
Parameter
Min
Max
Unit
e1
Ball pitch (x-axis)
1.27
1.27
mm
e2
Ball pitch (y-axis)
1.27
1.27
mm
A
Package body length
11.9
12.1
mm
D
Package body width
11.7
11.9
mm
E
Package total thickness
-
1.25
mm
E1
Ball height
0.45
0.55
mm
d
Ball diameter
0.55
0.65
mm
Page 18
Version 1.0 Dec. 2001