L4901A DUAL 5V REGULATOR WITH RESET . . . . . . . .. .. . OUTPUT CURRENTS : I01 = 400mA I 0 2 = 400mA FIXED PRECISION OUTPUT VOLTAGE 5V ± 2% RESET FUNCTION CONTROLLED BY INPUT VOLTAGE AND OUTPUT 1 VOLTAGE RESET FUNCTION EXTERNALLY PROGRAMMABLE TIMING RESET OUTPUT LEVEL RELATED TO OUTPUT 2 OUTPUT 2 INTERNALLY SWITCHED WITH ACTIVE DISCHARGING LOW LEAKAGE CURRENT, LESS THAN 1µA AT OUTPUT 1 LOW QUIESCENT CURRENT (Input 1) INPUT OVERVOLTAGE PROTECTION UP TO 60V RESET OUTPUT HIGH OUTPUT TRANSISTORS SO A PROTECTION SHORT CIRCUIT AND THERMAL OVERLOAD PROTECTION HEPTAWATT (Vertical) (Plastic Package) ORDERING NUMBER : L4901A DESCRIPTION The L4901A is a monolithic low drop dual 5V regulator designed mainly for supplying microprocessor systems. Reset and data save functions during switch on/off can be realized. PIN CONNECTION June 2000 1/10 L4901A PIN DESCRIPTION N° 1 2 3 Name Input 1 Input 2 Timing Capacitor 4 5 GND Reset Output 6 Output 2 7 Output 1 Function Low Quiescent Current 400mA Regulator Input. 400mA regulator input. If Reg. 2 is switched-ON the delay capacitor is charged with a 10µA constant current. When Reg. 2 is switched-OFF the delay capacitor is decharged. Common Ground. When pin 3 reaches 5V the reset output is switched high. 5V Therefore tRD = Ct ( ); tRD (ms) = Ct (nF) 10µA 5V – 400mA Regulator Output. Enabled if Vo 1 > VRT and VIN 2 > VIT. If Reg. 2 is switched-OFF the C02 capacitor is discharged. 5V – 400mA regulator output with Low leakage (in switch-OFF condition). BLOCK DIAGRAM SCHEMATIC DIAGRAM 2/10 L4901A ABSOLUTE MAXIMUM RATINGS Symbol V IN Parameter Value Unit 24 60 V V DC Input Voltage Transient Input Overvoltage (t = 40ms) Io Output Current Internally Limited Tj Storage and Junction Temperature – 40 to 150 °C Value Unit 4 °C/W THERMAL DATA Symbol R th (j-c) Parameter Thermal Resistance Junction-case Max. ELECTRICAL CHARACTERISTICS (VIN = 14, 4V, Tamb = 25°C unless otherwise specified) Symbol Parameter Test Conditions Min. Typ. Max. Unit 20 V 5.05 5.15 V 5 V01 V Vi DC Operating Input Voltage V01 Output Voltage 1 R Load 1kΩ 4.95 V02 H Output Voltage 2 HIGH R Load 1kΩ V01 –0.1 V02 L Output Voltage 2 LOW I02 = – 5mA I01 Output Current 1 ∆V01 = – 100mV IL01 Leakage Output 1 Current VIN = 0, V01 ≤ 3V I02 Output Current 2 ∆V02 = – 100mV VI01 Output 1 Dropout Voltage (*) I01 = 10mA I01 = 100mA I01 = 300mA 0.1 V 400 mA 1 400 0.7 0.8 1.1 0.8 1 1.4 6.4 V01 + 1.7 VIT Input Threshold Voltage VITH Input Threshold Voltage Hyst. ∆V01 Line Regulation 1 ∆V02 Line Regulation 2 7V < VIN < 18V, I02 = 5mA ∆V01 Load Regulation 1 5mA < I01 < 400mA ∆V02 Load Regulation 2 5mA < I01 < 400mA 50 100 IQ Quiescent Current I02 = I01 ≤ 5mA 0 < VIN < 13V 7V < VIN < 13V IQ1 Quiescent Current 1 V01 + 1.2 250 7V < VIN < 18V, I01 = 5mA 5 VRT Reset Threshold Voltage Reset Threshold Hysteresis VRH Reset Output Voltage HIGH IR = 500µA VRL Reset Output Voltage LOW IR = –<0>5mA tRD Reset Pulse Delay Ct = 10nF V V V V mV 50 mV 5 50 mV 50 100 mV mV mA 4.5 1.6 6.5 3.5 0.6 0.9 V 02 – 0.15 4.9 V02 –0.05 V 30 50 80 mV V02 – 1 4.12 V02 V 0.25 0.4 V 5 11 ms 20 µs I01 ≤ 5mA, I02 = 0, VIN2 = 0 6.3V < VIN < 13V VRTH µA mA 3 mA Timing Capacitor Discharge Time Ct = 10nF ∆V01 ∆T Thermal Drift – 20°C ≤ Tamb ≤ 125°C 0.3 – 0.8 mV/°C ∆V02 ∆T Thermal Drift – 20°C ≤ Tamb ≤ 125°C 0.3 – 0.8 mV/°C SVR1 Supply Voltage Rejection 84 dB Supply Voltage Rejection f = 100Hz, VR = 0.5V Io = 100mA 50 SVR2 50 80 dB td * The dropout voltage is defined as the difference between the input and the output voltage when the output voltage is lowered of 25 mV under constant output current condition. 3/10 L4901A TEST CIRCUIT APPLICATION INFORMATION In power supplies for µP systems it is necessary to provide power continuously to avoid loss of information in memories and in time of day clocks, or to save datawhen the primary supply is removed.The L4901A makes it very easy to supply such equipments ; it provides two voltage regulators (both 5 V high precision) with separate inputs plus a reset output for the data save function. CIRCUIT OPERATION (see Figure 1) After switch on Reg. 1 saturates until V 01 rises to the nominal value. When the input 2 reaches VIT and the output 1 is higher than VRT the output 2 (V02) switches on and the reset output (VR) also goes high after a proFigure 1 4/10 grammable time TRD (timing capacitor). V02 and VR are switched togetherat low level when one of the following conditions occurs : - an input overvoltage - an overload on the output 1 (V01 < VRT) ; - a switch off (VIN < VIT - VITH) ; and they start again as before when the condition is removed. An overload on output 2 does not switch Reg. 2, and does not influence Reg. 1. The V01 output features : - 5 V internal reference without voltage divider between the output and the error comparator ; - very low drop series regulator element utilizing current mirrors ; permit high output impedance and then very low leakage current error even in power down condi- L4901A tion. This output may thereforebe usedto supply circuits continuously, such as volatile RAMs, allowing the use of a back-up battery. The V01 regulator also features low consumption (0.6 mA typ.) to minimize battery drain in applicationswhere the V1 regulator is permanently connected to a battery supply. The V02 output can supply other non essential 5 V circuits which may be powered down when the system is inactive, or that must be powered down to prevent uncorrect operation for supply voltages below the minimum value. The reset output can be usedas a ”POWERDOWN INTERRUPT”, permitting RAM access only in correct powerconditions,or as a ”BACK-UPENABLE” to transfer data into in a NV SHADOW MEMORY when the supply is interrupted. APPLICATIONS SUGGESTIONS Figure 2 shows an application circuit for a µP system typically used in trip computers or in car radios with programmable tuning. Reg. 1 is permanently connected to a battery and supplies a CMOS time-of-day clock and a CMOS microcomputer chip with volatile memory. Reg. 2 may be switched OFF when the system is Figure 2 Figure 3 : P.C. Board Component Layout of Figure 2. 5/10 L4901A inactive. Figure 4 shows the L4901A with a back up battery on the V01 output to maintain a CMOS time-of-day clock and a stand by type N-MOS µP. The reset output makes sure that the RAM is forced into the low consumption stand by state, so the access to memory is inhibit and the back up battery voltage Figure 4 Figure 5 6/10 cannot drop so low that memory contents are corrupted. In this casethe main on-off switch disconnects both regulators from the supply battery. The L4901A is also ideal for microcomputer systems using battery backup CMOS static RAMs. As shown in Figure 5 the reset output is used both to L4901A disable the µP and, through the address decoder M74HC138, to ensure that the RAMS are disabled as soon as the main supply starts to fall. Another interesting application of the L4901A is in µP system with shadow memories (see Figure 6). When the input voltage goes below VIT, the reset ouput enables the execution of a routine that saves the machine’s state in the shadow RAM (xicor x 2201 for example). Thanks to the low consumption of the Reg. 1 a Figure 6 Figure 7 : Quiescent Current (reg.1) versus Output Current Figure 8 : Quiescent Current (reg.1) versus Input Voltage 7/10 L4901A Figure 9 : Total Quiescent Current versus Input Voltage Figure 10 : Regulator 1 Output Current and Short Circuit Current versus Input Voltage Figure 11 : Regulator 1 Output Current and Short Circuit Current versus Input Voltage Figure 12 : Supply Voltage Rejection Regulators 1 and 2 versus Input Ripple Frequence 8/10 L4901A DIM. A C D D1 E E1 F F1 G G1 G2 H2 H3 L L1 L2 L3 L4 L5 L6 L7 L9 M M1 V4 Dia MIN. mm TYP. 2.4 1.2 0.35 0.7 0.6 2.34 4.88 7.42 10.05 16.7 21.24 22.27 2.6 15.1 6 2.55 4.83 2.54 5.08 7.62 16.9 14.92 21.54 22.52 2.8 15.5 6.35 0.2 2.8 5.08 3.65 MAX. 4.8 1.37 2.8 1.35 0.55 0.97 0.8 0.9 2.74 5.28 7.82 10.4 10.4 17.1 inch TYP. MIN. 0.094 0.047 0.014 0.028 0.024 0.095 0.193 0.295 0.396 0.657 21.84 22.77 1.29 3 15.8 6.6 0.386 0.877 0.102 0.594 0.236 3.05 5.33 40° 3.85 0.100 0.190 (typ.) 0.144 0.100 0.200 0.300 0.668 0.587 0.848 0.891 0.110 0.610 0.250 0.008 0.110 0.200 OUTLINE AND MECHANICAL DATA MAX. 0.189 0.054 0.110 0.053 0.022 0.038 0.031 0.035 0.105 0.205 0.307 0.409 0.409 0.673 0.860 0.896 0.051 0.118 0.622 0.260 0.120 0.210 Heptawatt V 0.152 V L V E L1 M1 A M D C D1 L5 H2 L2 L3 F E E1 V4 L9 H3 H1 G G1 G2 Dia. F L7 L4 L6 H2 F1 HEPTAMEC 9/10 L4901A Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supe rsedes and replaces all information previouslysupplied. STMicroelectronics products are not authorized for use as critical comp onents in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics 2000 STMicroelectronics – Printed in Italy – All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com 10/10