SANYO LC74763

Ordering number : EN5039B
SANYO Semiconductors
DATA SHEET
LC74763
LC74763M
CMOS IC
On-Screen Display LSI
Overview
The LC74763 and LC74763M are on-screen display CMOS LSIs that superimpose text and low-level graphics onto
a TV screen (video signal) under the control of a microcontroller. The display characters have a 12 by 18 dots
structure, and 128 characters are provided.
Features
•
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•
•
•
•
•
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•
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Display structure: 12 lines by 24 characters (up to 288 characters)
Maximum character display: Up to 288 characters
Character configuration: 12 (W) by 18 (H) dots structure
Number of characters: 128 characters (128 plus space 2 fonts)
Character sizes: Three sizes (normal, double, and triple sizes)
Display starting positions: 64 horizontal and 64 vertical locations
Reverse video function: Characters can be inverted on a per character basis.
Flashing types: Two types with periods of 0.5 and 1.0 second on a per character basis (duty fixed at 50%)
Background color: One of eight colors (when internal synchronization used)
External control input: Serial data input in 8-bit units
Built-in horizontal/vertical sync separation circuit, AFC circuit, and synchronization detector
Video output: Composite video signal output in NTSC, PAL, PAL-M, PAL-N, PAL60, NTSC4.43, or SECAM
format
Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to
"standard application", intended for the use as general electronics equipment. The products mentioned herein
shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life,
aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal
system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten
human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they
grant any guarantee thereof. If you should intend to use our products for new introduction or other application
different from current conditions on the usage of automotive device, communication device, office equipment,
industrial equipment etc. , please consult with us about usage condition (temperature, operation time etc.)
prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be
solely responsible for the use.
Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate
the performance, characteristics, and functions of the described products in the independent state, and are
not guarantees of the performance, characteristics, and functions of the described products as mounted in the
customer' s products or equipment. To verify symptoms and states that cannot be evaluated in an
independent device, the customer should always evaluate and test devices mounted in the customer' s
products or equipment.
90711HKPC 20110822-S00002,B8-2087/32095TH (OT) No. 5039-1/21
LC74763, LC74763M
Specifications
Absolute Maximum Ratings at Ta = 25°C
Ratings
Unit
Maximum supply voltage
Parameter
VDD max
VDD1, VDD2 pins
VSS – 0.3 to VSS + 7.0
V
Maximum input voltage
VIN max
All input pins
VSS – 0.3 to VDD + 0.3
V
HSYNCOUT, VSYNCOUT,
SYNCDET pins
VSS – 0.3 to VDD + 0.3
Maximum output voltage
Allowable power dissipation
Symbol
VOUT max
Conditions
Pd max
V
300
mW
Operating temperature
Topr
–30 to +70
°C
Storage temperature
Tstg
–40 to +125
°C
Allowable Operating Ranges at Ta = –30 to +70°C
Parameter
Supply voltage
Input high level voltage
Input low level voltage
Input voltage
Composite video signal input voltage
Oscillator frequency
Symbol
Ratings
Conditions
min
typ
Unit
max
VDD1
VDD1 pin
4.5
5.0
5.5
V
VDD2
VDD2 pin
4.5
5.0
1.27 VDD1
V
VIH1
RST, CS, SIN, SCLK pins
0.8 VDD1
VDD1 + 0.3
V
VIH2
SECAM, 525/625,
NTSC/PAL, 3.58/4.43 pins
0.7 VDD1
VDD1 + 0.3
V
VIL1
RST, CS, SIN, SCLK
VSS – 0.3
0.2 VDD1
V
VIL2
SECAM, 525/625,
NTSC/PAL, 3.58/4.43 pins
VSS – 0.3
0.3 VDD1
V
VSS – 0.3
VIN
FC, AMPIN pins
VIN1
CVIN pins
VIN2
CVCR pins
2 VPP
VIN3
SYNCIN pins
2 VPP
FOSC1
VDD1 + 0.3
2 VPP
XtalIN1, XtalOUT1, XtalIN2,
XtalOUT2 pins; 4fsc
V
V
V
2.5 VPP
V
NTSC
14.318
MHz
MHz
PAL
17.734
PAL-M
14.302
MHz
PAL-N
14.328
MHz
Electrical Characteristics at Ta = –30 to +70°C, with VDD1 = VDD2 = 5 V unless otherwise specified
Parameter
Symbol
Conditions
Ratings
min
typ
max
Unit
Output off leakage current
Ileak1
CVOUT pin
10
µA
Input off leakage current
Ileak2
CVIN, CVCR pins
10
µA
Output high level voltage
VOH
HSYNCOUT, VSYNCOUT,
SYNCDET, SECAM, 525/625,
NTSC/PAL, 3.58/4.43, AMPOUT,
PDOUT pins; VDD1 = 4.5 V, IOH = –1.0 mA
Output low level voltage
VOL
HSYNCOUT, VSYNCOUT,
SYNCDET, SECAM, 525/625,
NTSC/PAL, 3.58/4.43, AMPOUT,
PDOUT pins; VDD1 = 4.5 V, IOL = 1.0 mA
1.0
V
IIH
RST, CS, SIN, SCLK, SECAM, 525/625,
NTSC/PAL, 3.58/4.43 pins; VIN = VDD1
1
µA
IIL
SECAM, 525/625, NTSC/PAL,
3.58/4.43 pin; VIN = VSS1
Input current
Oscillator frequency
Operating current dissipation
3.5
V
–1
µA
FOSC3
VCOIN, VCOOUT pins; FC = 1/2 VDD1
IDD1
VDD1 pin; All outputs open, Xtal: 4fsc
14.12
15
MHz
mA
IDD2
VDD2 pin; VDD2 = 5.0 V
20
mA
Timing Characteristics at Ta = –30 to +70°C, VDD = 5 ±0.5 V
Ratings
Parameter
Minimum input pulse width
Data setup time
Data hold time
One word write time
Symbol
tW(SCLK)
Conditions
SCLK pin
tW(CS)
CS pin (during periods when CS is high)
min
typ
max
Unit
200
ns
1
µs
tSU(CS)
CS pin
200
ns
tSU(SIN)
SIN pin
200
ns
th(CS)
CS pin
2
µs
th(SIN)
SIN pin
200
ns
Write time for 8 bits of data
4.2
µs
1
µs
tword
twt
RAM data write time
No. 5039-2/21
LC74763, LC74763M
Pin Functions
Pin No.
Symbol
1
VSS
2
XtalIN1
3
XtalOUT1
4
HSYNCOUT
Function
Description
Ground
Ground connection
Crystal oscillator connection
Connection for the crystal and capacitor used to form the crystal oscillator that generates
the internal synchronization signal. The oscillator can be selected with a command switch.
Horizontal synchronization
output
Outputs the horizontal synchronization signal (AFC). The output polarity can be selected
(metal option). Also functions as general output port (command switch).
Crystal oscillator connection
Connection for the crystal and capacitor used to form the crystal oscillator that generates
the internal synchronization signal.
Vertical synchronization output
Outputs the vertical synchronization signal. The output polarity can be selected (metal
option). Also functions as general output port (command switch).
5
XtalIN2
6
XtalOUT2
7
VSYNCOUT
8
CS
Enable input
Enables/disables serial data input. Serial data is enabled when this pin is low (hysteresis
input). Pull-up resistor built in (metal option).
9
SIN
Data input
Serial data input (hysteresis input). Pull-up resistor built in (metal option).
10
SCLK
Clock input
Clock input for serial data input (hysteresis input). Pull-up resistor built in (metal option).
11
SECAM
SECAM mode switch input/
output (command switch)
During input, switches between SECAM and other modes.
During output, functions as general output port or internal V output (command switch).
Low = other modes, high = SECAM mode
12
525/625
525/625 switch input/output
(command switch)
During input, switches between 525 scan lines and 625 scan lines.
During output, functions as general output port or character data output (command switch).
Low = 525 lines, high = 625 lines
13
NTSC/PAL
NTSC/PAL switch input/output
(command switch)
Switches the color mode between NTSC and PAL.
During output, functions as general output port or frame data output (command switch).
Low = NTSC, high = PAL
14
3.58/4.43
15
RST
16
CVOUT
Video signal output
Composite video output
17
VDD2
Power supply connection
Power supply connection for composite video signal level generation
18
CVIN
Video signal input
Composite video input
19
CVCR
Video signal input
SECAM chroma signal input
20
SYNCIN
Sync separator circuit input
Built-in sync separator circuit video signal input
21
SEPC
Sync separator circuit
Built-in sync separator circuit
22
VSS
23
PDOUT
24
AMPIN
25
AMPOUT
26
FC
27
VCOIN
28
VCOOUT
29
SYNCDET
30
VDD1
3.58/4.43 switch input/output
(command switch)
Reset input
Switch FSC between 3.58 MHz and 4.43 MHz.
During output, functions as general output port or halftone output (command switch).
Low = 3.58, high = 4.43
System reset input pin, low is active (hysteresis input).
Pull-up resistor built in (metal option).
Ground
Ground connection
Control voltage output
AFC control voltage output
AFC filter connection
Filter connection
Control voltage input
AFC control voltage input
LC oscillator connection
VCO LC oscillator circuit coil and capacitor connection
External synchronization signal
detection output
Outputs the exclusive NOR of the horizontal synchronization signal (AFC) and CSYNC (sync
separator). The output polarity can be selected (metal option). Also functions as general
output port (command switch).
Power supply connection
Power supply connection (+5 V: digital system power supply)
No. 5039-3/21
LC74763, LC74763M
Serial Data Input Timing
Package Dimensions
Package Dimensions
unit : mm (typ)
3196A [LC74763]
unit : mm (typ)
3312 [LC74763M]
15.2
27.0
30
7.9
10.5
10.16
15
1.0
0.25
0.35
(0.6)
2.45max
(3.25)
1
0.48
0.1 (2.25)
3.95 MAX
3.0
0.51 MIN
0.65
15
0.95
0.25
1
(1.04)
16
16
8.6
30
1.78
SANYO: DIP30SD(400mil)
SANYO: MFP30SDJ(375mil)
No. 5039-4/21
LC74763, LC74763M
Pin Assignment
Top view
No. 5039-5/21
LC74763, LC74763M
System Block Diagram
No. 5039-6/21
LC74763, LC74763M
Display Control Commands
Display control commands are input in an 8-bit serial format. Commands consist of a command identification code in the
first byte and data in the second and following bytes. The following commands are supported.
①
➁
③
➃
➄
➅
⑦
⑧
COMMAND0:
COMMAND1:
COMMAND2:
COMMAND3:
COMMAND4:
COMMAND5:
COMMAND6:
COMMAND7:
Display memory (VRAM) write address setting command
Display character data write command
Vertical display start position and character size (lines 1 and 2) setting command
Horizontal display start position and character size (lines 9 and 11) setting command
Display control setting command 1
Display control setting command 2
Display control setting command 3
Display control setting command 4
Display Control Command Table
First byte
Command
Second byte
Command identification code
Data
Data
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
COMMAND0
Write address
1
0
0
0
V3
V2
V1
V0
0
0
0
H4
H3
H2
H1
H0
COMMAND1
Character write
1
0
0
1
0
0
at2
at1
c7
c6
c5
c4
c3
c2
c1
c0
COMMAND2
Vertical display start position
1
0
1
0
SZ
21
SZ
20
SZ
11
SZ
10
0
0
VP
5
VP
4
VP
3
VP
2
VP
1
VP
0
COMMAND3
Horizontal display start position
1
0
1
1
SZ
B1
SZ
B0
SZ
91
SZ
90
0
0
HP
5
HP
4
HP
3
HP
2
HP
1
HP
0
COMMAND4
Display control 1
1
1
0
0
RST
RAM
OSC
RND
0
I/N
BLK
1
BLK
0
BK
1
ATS
0
DSP
COMMAND5
Display control 2
1
1
0
1
PH
2
PH
1
PH
0
I/E
0
TST
CHAL
BKL
RSL
1
RSL
0
CVM
XTS
COMMAND6
Display control 3
1
1
1
0
0
HFI
M30S SMS
IOS
BCL
1
BCL
0
CB
COMMAND70
Display control 4
1
1
1
1
0
0
0
LINS
0
VCOS
1
LIN
5
LIN
4
LIN
3
LIN
2
LIN
1
LIN
0
COMMAND71
Display control 5
1
1
1
1
0
1
0
LINS
0
EG
2
PS
2
PS
1
VMN
SVIS
VNS
VSS
COMMAND72
Display control 6
1
1
1
1
1
0
0
LINS
0
0
0
0
MOD MOD MOD MOD
3
2
1
0
COMMAND73
Display control 7
1
1
1
1
1
1
0
LINS
0
0
0
0
VCOS SOUT VOUT HOUT
2
MOD MOD MOD MOD
3
2
1
0
Once the command identification code in the first bite is written, it is stored internally until the first byte of the following
command is written. However, when the display character data write command (COMMAND1) is written, the system
becomes locked in display character data write mode, and the first byte cannot be overwritten.
When the CS pin is set high the command state is set to COMMAND0, i.e., display memory write address setting mode.
No. 5039-7/21
LC74763, LC74763M
① COMMAND0: Display Memory Write Address Setting Command
First data byte
Register content
DA0 to DA7
Register name
7
—
1
6
—
0
5
—
0
4
—
0
3
V3
2
V2
1
V1
0
V0
State
Function
Note
The command 0 identification code:
sets the display memory write address.
0
1
0
1
0
Display memory line address (from 0 to B (hexadecimal))
1
0
1
Second byte
Register content
DA0 to DA7
Register name
State
7
—
0
6
—
0
5
—
0
4
H4
3
H3
2
H2
1
H1
0
H0
Function
Note
Second byte identification code
0
1
0
1
0
1
Display memory character address (from 0 to 17 (hexadecimal))
0
1
0
1
Note: When the chip is reset by the RST pin, the register states (bits) are all cleared to 0.
➁ COMMAND1: Display Character Data Write Setting Command
First byte
Register content
DA0 to DA7
Register name
7
—
1
6
—
0
5
—
0
4
—
1
3
—
0
2
—
0
1
at2
0
at1
State
Function
The command 1 identification code:
sets the display memory write address.
0
Turns character attribute 2 off.
1
Turns character attribute 2 on.
0
Turns character attribute 1 off.
1
Turns character attribute 1 on.
Note
When this command is entered, the
chip locks in display character write
mode until the CS pin is set high.
Specifies highlight or flashing.
Specifies reverse video.
No. 5039-8/21
LC74763, LC74763M
Second byte
Register content
DA0 to DA7
Register name
7
c7
6
c6
5
c5
4
c4
3
c3
2
c2
1
c1
0
c0
State
Note
Function
0
1
0
1
0
1
0
1
0
Character code (from 00 to 7F, FE, FF)
1
0
1
0
1
0
1
Note: When the chip is reset by the RST pin, the register states (bits) are all cleared to 0.
③ COMMAND2: Vertical Display Position Setting Command
First byte
Register content
DA0 to DA7
Register name
7
—
1
6
—
0
5
—
1
4
—
0
3
SZ21
2
SZ20
1
SZ11
0
SZ10
State
The command 2 identification code:
sets the vertical display position.
0
1
Note
Function
SZ20
0
SZ21
1
0
0
Normal size
Double size
1
1
Triple size
Normal size
0
1
SZ10
0
SZ11
Character size for the second line
1
0
0
Normal size
Double size
1
1
Triple size
Normal size
Character size for the first line
Second byte
Register content
DA0 to DA7
Register name
7
—
0
6
—
0
5
VP5
(MSB)
0
4
VP4
3
VP3
2
VP2
1
VP1
0
VP0
(LSB)
State
1
Function
Note
Second byte identification code
The vertical display start position is given by
5
2nVPn)
0
VS = H × ( Σ
1
where H is the horizontal synchronization pulse period.
n=0
0
1
0
The six bits VP0 to VP5 specify the
vertical display start position.
The weight of the lsb is 1 × H.
1
0
1
0
1
Note: When the chip is reset by the RST pin, the register states (bits) are all cleared to 0.
No. 5039-9/21
LC74763, LC74763M
➃ COMMAND3: Horizontal Display Position Setting Command
First byte
Register content
DA0 to DA7
Register name
7
—
1
6
—
0
5
—
1
4
—
1
3
SZB1
2
SZB0
1
SZ91
0
SZ90
State
The command 3 identification code:
sets the horizontal display position.
0
1
Note
Function
SZB0
0
SZB1
1
0
0
Normal size
Double size
1
1
Triple size
Normal size
0
1
SZ90
0
SZ91
The character size for the eleventh line.
1
0
0
Normal size
Double size
1
1
Triple size
Normal size
The character size for the ninth line.
Second byte
Register content
DA0 to DA7
Register name
State
7
—
0
6
—
0
5
HP5
(MSB)
0
4
HP4
3
HP3
2
HP2
1
HP1
0
HP0
(LSB)
Function
Note
Second byte identification code
1
0
1
0
1
The horizontal display start position is given by
5
HS = Tc × ( Σ
The six bits HP0 to HP5 specify the
vertical display start position.
The weight of the lsb is 1 x Tc.
2nHPn)
n=0
0
1
0
where Tc is the period of the OSCIN and OSCOUT oscillator in
operating mode.
1
0
1
Note: When the chip is reset by the RST pin, the register states (bits) are all cleared to 0.
➄ COMMAND4: Display Control Setting Command 1
First byte
Register content
DA0 to DA7
Register name
7
—
1
6
—
1
5
—
0
4
—
0
3
RSTSYS
2
RAMERS
State
Function
The command 4 identification code:
sets display control parameters.
0
Resets all registers. (Clears all registers to 0.)
This reset occurs when the CS pin goes
low, and the reset state cleared when
the CS pin goes high.
1
Erases display RAM. (Sets display RAM to FF (hexadecimal).)
The RAM erase function requires at
least 500 µs.
It is executed on DSPOFF.
0
Continues crystal oscillator operation.
1
Stops the crystal oscillator.
0
Turns off rounding.
1
Turns on rounding.
1
0
1
0
OSCSTP
RNDSEL
Note
Only valid with character display off if
external synchronization is used.
Only valid for double and triple size
characters.
No. 5039-10/21
LC74763, LC74763M
Second byte
Register content
DA0 to DA7
Register name
7
—
6
INT/NON
5
BLK1
4
BLK0
3
BK1
2
ATS
1
—
0
DSPON
State
0
Second byte identification code
0
Interlaced
1
Non-interlaced
0
1
Note
Function
Switches between interlaced and
non-interlaced display.
BLK0
0
BLK1
0
1
1
0
Blanking off
Character size blanking
1
Frame size blanking
Total area blanking
0
Flashing period about 0.5 s
1
Flashing period about 1 s
0
Highlight function
1
Flashing function
Changes the blanking size.
Sets the flashing period.
Selects at2.
0
0
Character display off
1
Character display on
Turns character output on and off.
Note: When the chip is reset by the RST pin, the register states (bits) are all cleared to 0.
➅ COMMAND5: Display Control Setting Command 2
First byte
Register content
—
1
6
—
1
5
—
0
4
—
1
3
PH2
The command 5 identification code:
sets display control parameters.
0
0
PH1
1
0
1
PH0
1
0
INT/EXT
Background color
(phase)
PHASE 2
PHASE 1
PHASE 0
NTSC
PAL
0
0
0
π/2
±π/2
0
0
1
In phase
In phase
0
1
0
3 π/2
0
1
1
π
±π
1
0
0
3 π/4
±3 π/4
1
0
1
π/4
±π/4
1
1
0
7 π/4
1
1
1
5 π/4
1
2
Note
Function
0
External synchronization mode
1
Internal synchronization mode
±
7
State
±
Register name
±
DA0 to DA7
π/2
Sets the phase of the background color
for color burst.sz
π/4
3 π/4
Switches between internal and external
synchronization.
No. 5039-11/21
LC74763, LC74763M
Second byte
Register content
DA0 to DA7
Register name
7
—
6
TST
5
CHAL
4
3
State
0
Second byte identification code
0
Normal operation
1
Test mode
0
Sets the character intensity level to about 85 IRE (bright white).
1
Sets the character intensity level to about 72 IRE (white with a
touch of grey).
0
Sets the blanking intensity level to about 3 IRE (a deep black
as a frame level).
1
Sets the blanking intensity level to about 13 IRE (a dark grey
as a frame level).
BKL
RSL1
1
0
RSL0
CVoutmt
XTALsel
Test mode should not be used. This bit
should always be zero.
0
RSL1
RSL0
1
0
0
About 15 IRE
About 60 IRE
0
1
About 30 IRE
About 60 IRE
1
0
About 45 IRE
About 60 IRE
1
1
About 55 IRE
About 65 IRE
0
2
Note
Function
1
0
Normal CVout output
Intensity level
1
CVout pedestal level output
0
Selects XTAL1
1
Selects XTAL2
Switches the character intensity level.
Switches the blanking intensity level.
Amplitude
Switches the background intensity level.
Switches the oscillator circuit
Note: When the chip is reset by the RST pin, the register states (bits) are all cleared to 0.
⑦ COMMAND6: Display Control Setting Command 3
First byte
Register content
DA0 to DA7
Register name
7
—
1
6
—
1
5
—
1
4
—
0
3
MOD3
2
MOD2
1
MOD1
0
MOD0
State
Function
Note
The command 6 identification code:
sets display control parameters.
0
Sets Fsc to 3.58 MHz.
1
Sets Fsc to 4.43 MHz.
0
Sets the color mode to NTSC.
1
Sets the color mode to PAL.
0
Sets the number of scan lines to 525 lines.
1
Sets the number of scan lines to 625 lines.
0
Sets the mode to a mode other than SECAM.
1
Sets the mode to SECAM mode.
The logical or of this bit and the Fsc
switching input pin (pin 14) is used.
The logical or of this bit and the color
mode switching input pin (pin 13) is
used.
The logical or of this bit and the scan
line count switching input pin (pin 12) is
used.
The logical or of this bit and the mode
switching input pin (pin 11) is used.
No. 5039-12/21
LC74763, LC74763M
Second byte
Register content
DA0 to DA7
Register name
7
—
0
Second byte identification code
HALF
INT
0
Normal mode
1
Half internal synchronous mode
5
P14OUT
SEL
0
Halftone output
1
High output in internal synchronous mode
4
SECAM
SEL
0
In SECAM mode, only the character frame area is on.
1
In SECAM mode, the entire character display area is on.
3
IOS
0
Sets the mode setting pin to be an input pin.
1
Sets the mode setting pin to be an output pin.
2
BCOL1
6
State
0
BCOL1
BCOL0
1
0
0
Background color displayed
0
1
No background color (about 13 IRE)
1
0
No background color (about 23 IRE)
1
1
CVoutmt2 (CSYNC)
0
1
BCOL0
0
CBOFF
Note
Function
1
Selects P14 (3.58/4.43) output.
Selects the CVCR “on” period.
Switches the input/output direction of
the mode setting pins.
Background color
0
Outputs a color burst signal.
1
Stops the output of color burst signals.
Determines whether a background color
is displayed. (Only valid in internal
synchronization mode.)
Only valid when either BCOL0 is 1 or
BCOL1 is 1.
Note: When the chip is reset by the RST pin, the register states (bits) are all cleared to 0.
⑧ COMMAND70: Display Control Setting Command 4
First byte
Register content
DA0 to DA7
Register name
7
—
1
6
—
1
5
—
1
4
—
1
3
—
0
2
—
0
1
—
0
0
LINS
State
Function
Note
The command 7 identification code:
sets display control parameters.
Expansion command 0 identification code
0
Selects the lower 6 bits (bits 0 to 5)
1
Selects the upper 6 bits (bits 6 to B)
Selects the upper or lower six bits when
halftone output line mode is specified.
Second byte
Register content
DA0 to DA7
Register name
State
Function
7
—
0
6
VCO
SELECT1
0
VCO frequency is 14.12 MHz
1
VCO frequency is 7.07 MHz
5
LIN5
0
Turns off (low) sixth line halftone output.
1
Turns on (high) sixth line halftone output.
4
LIN4
0
Turns off (low) fifth line halftone output.
1
Turns on (high) fifth line halftone output.
3
LIN3
0
Turns off (low) fourth line halftone output.
1
Turns on (high) fourth line halftone output.
2
LIN2
0
Turns off (low) third line halftone output.
1
Turns on (high) third line halftone output.
1
LIN1
0
Turns off (low) second line halftone output.
1
Turns on (high) second line halftone output.
0
LIN0
Note
Second byte identification code
0
Turns off (low) first line halftone output.
1
Turns on (high) first line halftone output.
Selects VCO oscillation frequency.
Used for the line 12 setting when LINS
is high.
Used for the line 11 setting when LINS
is high.
Used for the line 10 setting when LINS
is high.
Used for the line 9 setting when LINS is
high.
Used for the line 8 setting when LINS is
high.
Used for the line 7 setting when LINS is
high.
Note: When the chip is reset by the RST pin, the register states (bits) are all cleared to 0.
No. 5039-13/21
LC74763, LC74763M
➈ COMMAND71: Display Control Setting Command 5
First byte
Register content
DA0 to DA7
Register name
7
—
1
6
—
1
5
—
1
4
—
1
3
—
0
2
—
1
1
—
0
0
LINS
State
Function
Note
The command 7 identification code: sets display
control parameters
Expansion command 1 identification code
0
Selects lower 6 bits (0 to 5).
1
Selects upper 6 bits (6 to B).
Selects lower or upper 6 bits for halftone output line setting.
Second byte
Register content
DA0 to DA7
Register name
State
Function
7
—
0
Second byte identification bit
6
EGMODE
2SELECT
0
Normal display
1
Applies frame to inverted characters also.
5
PORTSET
SELECT2
0
Sets port output data
1
Sets port (output switching)
4
PORTSET
SELECT1
0
Sets port output data
1
Sets port (output switching)
3
VMN
SEL
0
Normal V signal
1
VMASK signal
2
VINPsel
1
VNPsel
0
VSEPsel
0
Normal I/O
1
V is input from P11.
0
V rise detection
1
V fall detection
0
VSEP is about 9.3 µs.
1
VSEP is about 18.6 µs.
Note
Selects V detection polarity.
Selects V separation time.
Note: When the chip is reset by the RST pin, the register states (bits) are all cleared to 0.
➉ COMMAND72: Display Control Setting Command 6
First byte
Register content
DA0 to DA7
Register name
7
—
1
6
—
1
5
—
1
4
—
1
3
—
1
2
—
0
1
—
0
0
LINS
State
Function
Note
The command 7 identification code: sets display
control parameters
Expansion command 2 identification code
0
Selects lower 6 bits (0 to 5).
1
Selects upper 6 bits (6 to B).
Selects lower or upper 6 bits for halftone output line setting.
No. 5039-14/21
LC74763, LC74763M
Second byte
Register content
DA0 to DA7
Register name
7
—
0
6
—
0
5
—
0
4
—
0
3
MOD3
SEL
0
Normal MOD3 (P14) output (PS1 = 1)
1
Specifies MOD3 general port output
2
MOD2
SEL
0
Normal MOD2 (P13) output (PS1 = 1)
1
Specifies MOD2 general port output
1
MOD1
SEL
0
Normal MOD1 (P12) output (PS1 =1)
1
Specifies MOD1 general port output
0
MOD0
SEL
0
Normal MOD0 (P11) output (PS1 = 1)
1
Specifies MOD0 general port output
State
Function
Note
Second byte identification bit
Specifies port output data
when PS1 = 0.
Specifies port output data
when PS1 = 0.
Specifies port output data
when PS1 = 0.
Specifies port output data
when PS1 = 0.
Note: When the chip is reset by the RST pin, the register states (bits) are all cleared to 0.
11
COMMAND73: Display Control Setting Command 7
First byte
Register content
DA0 to DA7
Register name
7
—
1
6
—
1
5
—
1
4
—
1
3
—
1
2
—
1
1
—
0
0
LINS
State
Function
Note
The command 7 identification code: sets display
control parameters
Expansion command 3 identification code
0
Selects lower 6 bits (0 to 5).
1
Selects upper 6 bits (6 to B).
Selects lower or upper 6 bits for half
tone output line setting.
Second byte
Register content
DA0 to DA7
Register name
7
—
0
6
—
0
5
—
0
4
—
0
3
VCP
SELECT2
0
No feedback resistance
1
Feedback resistance
2
SDETOUT
SEL
0
Normal SOUT (P29) output (PS2 = 1)
1
Specifies SOUT general port output
1
VOUT
SEL
0
Normal VOUT (P7) output (PS2 =1)
1
Specifies VOUT general port output
0
HOUT
SEL
State
Function
Note
Second byte identification bit
0
Normal HOUT (P4) output (PS2 = 1)
1
Specifies HOUT general port output
Specifies VCO oscillator feedback
resistance connection
Specifies port output data
when PS2 = 0.
Specifies port output data
when PS2 = 0.
Specifies port output data
when PS2 = 0.
Note: When the chip is reset by the RST pin, the register states (bits) are all cleared to 0.
No. 5039-15/21
LC74763, LC74763M
Display Configuration
The display consists of 12 rows of 24 characters each. Up to 288 characters can be displayed unless enlarged characters
are displayed. Display memory addresses are expressed as a row address in the range 0 to B (hexadecimal) and a column
address in the range 0 to 17 (hexadecimal).
Display Configuration and Display Memory Addresses
24 characters by 12 rows
No. 5039-16/21
2.638
2.449
2.262
2.047
1.747
1.610
Character level 2
Background high level 2
Background high level 1
Burst high level
Frame level 2
Output voltage (VDC)
Character level 1
Output level
Sync level
Burst low level
Background low level 1
Pedestal level
Frame level 1
Output level
0.800
1.080
1.212
1.429
1.465
Output voltage (VDC)
LC74763, LC74763M
Composite Video Signal Output Levels (internally generated levels) Metal Option
No. 5039-17/21
2.841
2.652
2.456
2.242
1.943
1.811
Character level 2
Background high level 2
Background high level 1
Burst high level
Frame level 2
Output voltage (VDC)
Character level 1
Output level
Sync level
Burst low level
Background low level 1
Pedestal level
Frame level 1
Output level
1.000
1.275
1.407
1.624
1.665
Output voltage (VDC)
LC74763, LC74763M
Composite Video Signal Output Levels (internally generated levels) Metal Option
No. 5039-18/21
3.342
3.153
2.950
2.735
2.436
2.312
Character level 2
Background high level 2
Background high level 1
Burst high level
Frame level 2
Output voltage (VDC)
Character level 1
Output level
Sync level
Burst low level
Background low level 1
Pedestal level
Frame level 1
Output level
1.500
1.770
1.902
2.118
2.166
Output voltage (VDC)
LC74763, LC74763M
Composite Video Signal Output Levels (internally generated levels) Metal Option
No. 5039-19/21
LC74763, LC74763M
Application Circuit Diagram
SW1
SW2
SW3
NTSC
Signal format
3.579545 × 4
4 Fsc (MHz)
NTSC
Signal format
0
0
0
SW4
0
PAL
4.433618 × 4
PAL
0
1
1
1
SECAM
4.433618 × 4
SECAM
1
(1)
(1)
(1)
PAL-M
3.575611 × 4
PAL-M
0
0
1
0
PAL-N
3.582056 × 4
PAL-N
0
1
1
0
NTSC4.43
4.433618 × 4
NTSC4.43
0
0
0
1
PAL60
4.433618 × 4
PAL60
0
0
1
1
Note: Fix SW1 to SW4 to 0 when setting a mode by command.
No. 5039-20/21
LC74763, LC74763M
SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using
products at values that exceed, even momentarily, rated values (such as maximum ratings, operating
condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor
Co.,Ltd. products described or contained herein.
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semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures
or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give
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adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but
are not limited to protective circuits and error prevention circuits for safe design, redundant design, and
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Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the
SANYO Semiconductor Co.,Ltd. product that you intend to use.
Upon using the technical information or products described herein, neither warranty nor license shall be
granted with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any
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party's intellectual property rights which has resulted from the use of the technical information and products
mentioned above.
This catalog provides information as of September, 2011. Specifications and information herein are subject
to change without notice.
PS No. 5039-21/21