June 2002 LM4851 Integrated Audio Amplifier System General Description Features The LM4851 is an audio power amplifier system capable of delivering 1W (typ) of continuous average power into a mono 8Ω bridged-tied load (BTL) with 1% THD+N and 100mW (typ) per channel of continuous average power into stereo 32Ω BTL loads with 0.5% THD+N, using a 5V power supply. The LM4851 features a 32 step digital volume control and eight distinct output modes. The digital volume control and output modes are programmed through a three-wire SPI serial control interface. n Mono 1W (typ) and stereo 100mW (typ) output n SPI programmable 32 step digital volume control (-40.5dB to +6dB) n Eight distinct SPI programmable output modes n micro-SMD surface mount packaging n “Click and pop” suppression circuitry n No bootstrap capacitors required n Thermal shutdown protection n 0dB power-up volume n Low shutdown current Key Specifications n THD+N at 1kHz, 1W into 8Ω BTL n THD+N at 1kHz, 100mW into 32Ω BTL n Single Supply Operation 1% (typ) 0.5% (typ) 3.0 to 5.0V Applications n Mobile phones n PDAs Typical Application 20040831 FIGURE 1. Typical Audio Amplifier Application Circuit Boomer ® is a registered trademark of National Semiconductor Corporation. © 2002 National Semiconductor Corporation DS200408 www.national.com LM4851 Integrated Audio Amplifier System PRELIMINARY LM4851 Connection Diagrams 18-Bump micro SMD Marking 200408A5 Top View XY- Date Code TT - Die Traceability G - Boomer Family 52 - LM4851IBL-1 20040829 NC = NO CONNECT Top View 18-Bump micro SMD 200408A7 Top View Order Number LM4851LQ See NS Package Number LQA24A for Exposed-DAP LLP www.national.com 2 (Note 2) Thermal Resistance If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage Storage Temperature ESD Susceptibility (Note 4) ESD Machine model (Note 7) Junction Temperature (TJ) LM4851 Absolute Maximum Ratings θJA (typ) - LQA24A 42˚C/W θJC (typ) - LQA24A 3.0˚C/W 6.0V θJA (typ) - BLA18AAB 48˚C/W (Note 9) −65˚C to +150˚C θJC (typ) - BLA18AAB 23˚C/W (Note 9) 2.0kV 100V Operating Ratings (Note 3) 150˚C Solder Information (Note 1) Temperature Range −40˚C to 85˚C Small Outline Package Supply Voltage VDD 3.0V ≤ VDD ≤ 5.0V Vapor Phase (60 sec.) 215˚C Infrared (15 sec.) 220˚C Note 1: See AN-450 ’Surface Mounting and their effects on Product Reliability’ for other methods of soldering surface mount devices. Electrical Characteristics (Notes 2, 8) The following specifications apply for VDD = 5.0V, TA = 25˚C unless otherwise specified. Symbol Parameter Conditions LM4851 Units (Limits) Typical (Note 5) Limit (Note 6) Output mode 7 VIN = 0V; IO = 0A 7.5 14 mA Output modes 1, 2, 3, 4, 5, 6 VIN = 0V; IO = 0A 5.0 9.0 mA IDD Supply Current IDD Shutdown Current Output mode 0 0.1 2 µA VOS Output Offset Voltage VIN = 0V 5.0 50 mV SPKROUT; RL = 8Ω THD+N = 1%; f = 1kHz 1.0 0.8 W (min) ROUT and LOUT; RL = 32Ω THD+N = 0.5%; f = 1kHz 100 80 mW (min) ROUT and LOUT; f = 1kHz POUT = 100mW; RL = 32Ω 0.5 % (max) SPKROUT; f = 1kHz POUT = 800mW; RL = 8Ω 1.0 % (max) PO Output Power THD+N Total Harmonic Distortion Plus Noise ROUT and LOUT; f = 20Hz to 20kHz POUT = 100mW; RL = 32Ω 0.3 % SPKROUT; f = 20Hz to 20kHz POUT = 800mW; RL = 8Ω 0.3 % SNR Signal to Noise Ratio A-weighted; f = 1kHz 90 dB PSRR Power Supply Rejection Ratio VRIPPLE = 200mVPP; f = 217Hz Input floating; Input referred 70 dB VRIPPLE = 200mVPP; f = 217Hz Input terminated into 50Ω; Output referred 62 dB VIH Logic High Input Voltage 1.4 5.0 3 V (min) V (max) www.national.com LM4851 Electrical Characteristics (Notes 2, 8) (Continued) The following specifications apply for VDD = 5.0V, TA = 25˚C unless otherwise specified. Symbol Parameter Conditions LM4851 Typical (Note 5) VIL Limit (Note 6) Logic Low Input Voltage Digital Volume Range (RIN and LRIN) 0.4 Input referred minimum gain Input referred maximum gain Digital Volume Stepsize Stepsize Error Units (Limits) V (max) -40.5 +6 dBdB 1.5 dB ± 0.5 dB Phone In Volume BTL gain from Phone In to SPKROUT 6 dB Phone In Volume BTL gain from Phone In to ROUT,LOUT 0 dB Phone In Input Impedance 20 15 25 kΩ (min) kΩ (max) RIN and LIN 50 37.5 62.5 kΩ (min) kΩ (max) tES Enable Setup Time (ENB) 20 ns (min) tEH Enable Hold Time (ENB) 20 ns (min) tEL Enable Low Time (ENB) 30 ns (min) tDS Data Setup Time (DATA) 20 ns (min) tDH Data Hold Time (DATA) 20 ns (min) tCS Clock Setup Time (CLK) 20 ns (min) tCH Clock Logic High Time (CLK) 50 ns (min) tCL Clock Logic Low Time (CLK) 50 ns (min) tCLK Clock Frequency DC 10 (min) MHz (max) Electrical Characteristics (Notes 2, 8) The following specifications apply for VDD = 3.0V, TA = 25˚C unless otherwise specified. Symbol Parameter Conditions LM4851 Units (Limits) Typical (Note 5) Limit (Note 6) Output mode 7 VIN = 0V; IO = 0A 6.2 11 mA Output modes 1, 2, 3, 4, 5, 6 VIN = 0V; IO = 0A 4.0 7.0 mA IDD Supply Current IDD Shutdown Current Output mode 0 0.1 2 µA VOS Output Offset Voltage VIN = 0V 5.0 50 mV SPKROUT; RL = 8Ω THD+N = 1%; f = 1kHz 340 300 mW (min) ROUT and LOUT; RL = 32Ω THD+N = 0.5%; f = 1kHz 25 20 mW (min) PO Output Power www.national.com 4 LM4851 Electrical Characteristics (Notes 2, 8) (Continued) The following specifications apply for VDD = 3.0V, TA = 25˚C unless otherwise specified. Symbol Parameter Conditions LM4851 Typical (Note 5) THD+N Total Harmonic Distortion Plus Noise Limit (Note 6) Units (Limits) ROUT and LOUT; f = 1kHz POUT = 20mW; RL = 32Ω 0.5 % (max) SPKROUT; f = 1kHz POUT = 300mW; RL = 8Ω 1.0 % (max) ROUT and LOUT; f = 20Hz to 20kHz POUT = 20mW; RL = 32Ω 0.4 % SPKROUT; f = 20Hz to 20kHz POUT = 250mW; RL = 8Ω 0.3 % SNR Signal to Noise Ratio A-weighted; f = 1kHz 90 dB PSRR Power Supply Rejection Ratio VRIPPLE = 200mVPP; f = 217Hz Input floating; Input referred 70 dB VRIPPLE = 200mVPP; f = 217Hz Input terminated into 50Ω; Output referred 62 dB VIH Logic High Input Voltage VIL Logic Low Input Voltage Digital Volume Range (RIN and LRIN) Input referred minimum gain Input referred maximum gain Digital Volume Stepsize 1.4 3.0 V (min) V (max) 0.4 V (max) -40.5 +6 dBdB 1.5 dB ± 0.5 dB Phone In Volume BTL gain from Phone In to SPKROUT 6 dB Phone In Volume BTL gain from Phone In to ROUT,LOUT 0 dB Stepsize Error Phone In Input Impedance 20 15 25 kΩ (min) kΩ (max) RIN and LIN 50 37.5 62.5 kΩ (min) kΩ (max) tES Enable Setup Time (ENB) 20 ns (min) tEH Enable Hold Time (ENB) 20 ns (min) tEL Enable Low Time (ENB) 30 ns (min) tDS Data Setup Time (DATA) 20 ns (min) tDH Data Hold Time (DATA) 20 ns (min) tCS Clock Setup Time (CLK) 20 ns (min) tCH Clock Logic High Time (CLK) 50 ns (min) tCL Clock Logic Low Time (CLK) 50 ns (min) tCLK Clock Frequency DC 10 (min) MHz (max) Note 2: Absolute Maximum Rating indicate limits beyond which damage to the device may occur. Note 3: Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. Note 4: Human body model, 100pF discharged through a 1.5kΩ resistor. Note 5: Typical specifications are specified at +25˚C and represent the most likely parametric norm. Note 6: Datasheet min/max specification limits are guaranteed by design, test, or statistical analysis. Note 7: Machine Model ESD test is covered by specification EIAJ IC-121-1981. A 200pF cap is charged to the specified voltage, then discharged directly into the IC with no external series resistor (resistance of discharge path must be under 50Ω). Note 8: All voltages are measured with respect to the ground pin, unless otherwise specified. Note 9: The given θJA and θJC is for an LM4851 mounted on a demonstration board with a 4 in2 area of 1oz printed circuit board copper ground plane. 5 www.national.com LM4851 External Components Description (Refer to Figure 1.) Components 1. Functional Description Cin This is the input coupling capacitor. It blocks the DC voltage at, and couples the the input signal to, the amplifier’s input terminals. Ci, also creates a highpass filter with the internal resistor Ri at fc = 1/(2πRiCi). 2. Cs This is the supply bypass capacitor. It provides power supply filtering. 3. CB This is the BYPASS pin capacitor. It provides half-supply filtering. Typical Performance Characteristics THD+N vs Frequency THD+N vs Frequency 20040863 20040864 THD+N vs Frequency THD+N vs Frequency 20040865 www.national.com 20040866 6 LM4851 Typical Performance Characteristics (Continued) THD+N vs Frequency THD+N vs Frequency 20040867 20040868 THD+N vs Output Power THD+N vs Output Power 20040839 20040840 THD+N vs Output Power THD+N vs Output Power 20040841 20040842 7 www.national.com LM4851 Typical Performance Characteristics (Continued) THD+N vs Output Power THD+N vs Output Power 20040843 20040844 Power Supply Rejection Ratio Power Supply Rejection Ratio 20040845 20040874 Power Supply Rejection Ratio Power Supply Rejection Ratio 20040860 www.national.com 20040861 8 LM4851 Typical Performance Characteristics (Continued) Power Supply Rejection Ratio Power Supply Rejection Ratio 20040862 20040859 Output Power vs Supply Voltage Output Power vs Supply Voltage 20040847 20040846 Output Power vs Load Resistance Output Power vs Supply Voltage 20040849 20040848 9 www.national.com LM4851 Typical Performance Characteristics (Continued) Output Power vs Load Resistance Power Dissipation vs Output Power 20040869 20040871 Power Dissipation vs Output Power Supply Current vs Supply Voltage 20040872 20040855 Channel Separation vs Frequency 200408A6 www.national.com 10 SPI pin Description the data bits are written to the DATA pin with the least significant bit (LSB) first. All serial data are sampled at the rising edge of the CLK signal. Once all the data bits have been sampled, ENB transitions from logic-high to logic-low to complete the SPI sequence. All 8 bits must be received before any data latch can occur. Any excess CLK and DATA transitions will be ignored after the eighth rising clock edge has occurred. For any data sequence longer than 8 bits, only the first 8 bits will get loaded into the shift register and the rest of the bits will be disregarded. DATA: This is the serial data input pin. CLK: This is the click input pin. ENB: This is the SPI enable pin and is active-high. SPI Operation Description The serial data bits are organized into a field which contains 8 bits of data defined by TABLE 1. The Data 0 to Data 2 bits determine the output mode of the LM4851 as shown in TABLE 2. The Data 3 to Data 7 bits determine the volume level setting as illustrated by TABLE 3. For each SPI transfer, TABLE 1. Bit Allocation Data 0 Mode 1 Data 1 Mode 2 Data 2 Mode 3 Data 3 Volume 1 Data 4 Volume 2 Data 5 Volume 3 Data 6 Volume 4 Data 7 Volume 5 TABLE 2. Output Mode Selection Output Mode # Data 2 Data 1 Data 0 SPKROUT ROUT LOUT 0 0 0 0 SD SD SD 1 0 0 1 P SD SD 2 0 1 0 SD P P 3 0 1 1 R+L SD SD 4 1 0 0 SD R L 5 1 0 1 R+L+P SD SD 6 1 1 0 R+P R+P L+P 7 1 1 1 P R+P L+P (P= Phone Input R = Rin L = Lin SD = Shutdown Power-Up Mode = Output Mode 0) 11 www.national.com LM4851 Application Information LM4851 Application Information (Continued) TABLE 3. Volume Control Settings Gain (dB) Data 7 Data 6 Data 5 Data 4 Data 3 -40.5 0 0 0 0 0 -39.0 0 0 0 0 1 -37.5 0 0 0 1 0 -36.0 0 0 0 1 1 -34.5 0 0 0 0 0 -33.0 0 0 1 0 1 -31.5 0 0 1 1 0 -30.0 0 0 1 1 1 -28.5 0 1 0 0 0 -27.0 0 1 0 0 1 -25.5 0 1 0 1 0 -24.0 0 1 0 1 1 -22.5 0 1 1 0 0 -21.0 0 1 1 0 1 -19.5 0 1 1 1 0 -18.0 0 1 1 1 1 -16.5 1 0 0 0 0 -15.0 1 0 0 0 1 -13.5 1 0 0 1 0 -12.0 1 0 0 1 1 -10.5 1 0 1 0 0 -9.0 1 0 1 0 1 -7.5 1 0 1 1 0 -6.0 1 0 1 1 1 -4.5 1 1 0 0 0 -3.0 1 1 0 0 1 -1.5 1 1 0 1 0 0.0 1 1 0 1 1 1.5 1 1 1 0 0 3.0 1 1 1 0 1 4.5 1 1 1 1 0 6.0 1 1 1 1 1 www.national.com 12 6. ENB must be logic-high at least 20ns (tES ) before the first rising edge of CLK, and ENB has to remain logic-high at least 20ns (tEH) after the eighth rising edge of CLK. 7. If ENB remains logic-low for more than 10ns before all 8 bits are transmitted then the data latch will be aborted. 8. If ENB is logic-high for more than 8 CLK pulses then only the first 8 data bits will be latched and activated when ENB transitions to logic-low. 9. ENB must remain logic-low for at least 30ns (tEL ) to latch in the data. (Continued) SPI Operational Requirements 1. The data bits are transmitted with the LSB first. 2. The maximum clock rate is 10MHz for the CLK pin. 3. CLK must remain logic-high for at least 50ns (tCH ) after the rising edge of CLK, and CLK must remain logic-low for at least 50ns (tCL) after the falling edge of CLK. 4. The serial data bits are sampled at the rising edge of CLK. Any transition on DATA must occur at least 20ns (tDS) before the rising edge of CLK. Also, any transition on DATA must occur at least 20ns (tDH) after the rising edge of CLK and stabilize before the next rising edge of CLK. 10. Coincidental rising or falling edges of CLK and ENB are not allowed. If CLK is to be held logic-high after the data transmission, the falling edge of CLK must occur at least 20ns (tCS) before ENB transitions to logic-high for the next set of data. 5. ENB should be logic-high only during serial data transmission. 20040850 FIGURE 2. SPI Timing Diagram 13 www.national.com LM4851 Application Information LM4851 Demonstration Board Layout 200408A1 200408A2 Top Silkscreen Figure 3. Top Layer Figure 4. 200408A4 200408A3 Bottom Layer Figure 6. Middle Layer Figure 5. www.national.com 14 LM4851 Physical Dimensions inches (millimeters) unless otherwise noted 18-Bump micro SMD Order Number LM4851IBL-1 NS Package Number BLA18AAB X1 = 1.996 X2 = 2.225 X3 = 0.795 15 www.national.com LM4851 Integrated Audio Amplifier System Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 24-Lead MOLDED PKG, Leadless Leadframe Package LLP Order Number LM4851LQ NS Package Number LQA24A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation Americas Email: [email protected] www.national.com National Semiconductor Europe Fax: +49 (0) 180-530 85 86 Email: [email protected] Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +44 (0) 870 24 0 2171 Français Tel: +33 (0) 1 41 91 8790 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Asia Pacific Customer Response Group Tel: 65-2544466 Fax: 65-2504466 Email: [email protected] National Semiconductor Japan Ltd. Tel: 81-3-5639-7560 Fax: 81-3-5639-7507 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.