TI LM5114AMF

LM5114
Single 7.6A Peak Current Low-Side Gate Driver
General Description
Features
The LM5114 is designed to drive low-side MOSFETs in boost
type configurations or to drive secondary synchronous MOSFETs in isolated topologies. With strong sink current capability, the LM5114 can drive multiple FETs in parallel. The
LM5114 also has the features necessary to drive low-side enhancement mode Gallium Nitride (GaN) FETs. The LM5114
provides inverting and non-inverting inputs to satisfy requirements for inverting and non-inverting gate drive in a single
device type. The inputs of the LM5114 are TTL/CMOS Logic
compatible and withstand the input voltages up to 14V regardless of the VDD voltage. The LM5114 has split gate
outputs, providing flexibility to adjust the turn-on and turn-off
strength independently. The LM5114 has fast switching
speed and minimized propagation delays, facilitating highfrequency operation. The LM5114 is available in SOT-23 6pin package and LLP-6 package with an exposed pad to aid
thermal dissipation.
● Independent source and sink outputs for controllable rise
Typical Applications
●
●
●
●
Boost converters
Flyback and forward converters
Secondary synchronous FETs drive in isolated topologies
Motor control
●
●
●
●
●
●
●
●
●
●
●
●
and fall times
+4V to +12.6V single power supply
7.6A/1.3A peak sink/source drive current
0.23Ω open-drain pull-down sink output
2Ω open-drain pull-up source output
12ns (typical) propagation delay
Matching delay time between inverting and non-inverting
inputs
TTL/CMOS logic Inputs
0.68V input hysteresis
Up to +14V logic inputs (Regardless of VDD voltage)
Low input capacitance: 2.5pF (typical)
-40°C to +125°C operating temperature range
Pin-to-Pin compatible with MAX5048
Package
● SOT-23-6
● LLP-6 (3mm x 3mm)
Block Diagram
30180403
FIGURE 1.
PRODUCTION DATA information is current as of
publication date. Products conform to specifications per
the terms of the Texas Instruments standard warranty.
Production processing does not necessarily include
testing of all parameters.
301804 SNVS790D
Copyright © 1999-2012, Texas Instruments Incorporated
LM5114
Input Options
Base Part Number
Input Thresholds
LM5114A
CMOS
LM5114B
TTL
Truth Table
IN
INB
P_OUT
N_OUT
L
L
OPEN
L
L
H
OPEN
L
H
L
H
OPEN
H
H
OPEN
L
Connection Diagram
30180402
Ordering Information
2
Order Number
Package Type
Package Drawing
Supplied As
LM5114AMF
SOT-6
MF06A
1000 Units / Tape & Reel
LM5114AMFX
SOT-6
MF06A
3000 Units / Tape & Reel
LM5114ASD
LLP-6
SDE06A
1000 Units / Tape & Reel
LM5114ASDX
LLP-6
SDE06A
4500 Units / Tape & Reel
LM5114BMF
SOT-6
MF06A
1000 Units / Tape & Reel
LM5114BMFX
SOT-6
MF06A
3000 Units / Tape & Reel
LM5114BSD
LLP-6
SDE06A
1000 Units / Tape & Reel
LM5114BSDX
LLP-6
SDE06A
4500 Units / Tape & Reel
Copyright © 1999-2012, Texas Instruments Incorporated
LM5114
Pin Descriptions
Pin No.
Name
Description
Applications Information
Gate drive supply
Locally decouple to VSS using low ESR/ESL capacitor located as
close as possible to the IC.
P_OUT
Source-current
output
Connect to the gate of the MOSFET with a short, low inductance
path. A gate resistor can be used to adjust the turn-on speed.
3
N_OUT
Sink-current output
Connect to the gate of the MOSFET with a short, low inductance
path. A gate resistor can be used to adjust the turn-off speed.
4
4
VSS
Ground
All signals are referenced to this ground.
5
5
INB
Inverting logic input Connect to VSS when not used.
6
6
IN
SOT-23-6
LLP-6
1
1
VDD
2
2
3
EP
Non-inverting logic
input
Connect to VDD when not used.
It is recommended that the exposed pad on the bottom of the package is soldered to ground plane on
the PC board to aid thermal dissipation.
Copyright © 1999-2012, Texas Instruments Incorporated
3
LM5114
Absolute Maximum Ratings (Note 1)
VDD to VSS
IN, INB to VSS
N_OUT to VSS
P_OUT to VSS
Junction Temperature
Storage Temperature Range
ESD Rating HBM
−0.3 to 14V
−0.3 to 14V
−0.3 to VDD +0.3V
−0.3 to VDD +0.3V
+150°C
−55 to +150°C
2kV
Recommended Operating Conditions
VDD
Junction Temperature
+4.0 to 12.6V
−40 to +125°C
Electrical Characteristics
Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the junction temperature (TJ) range of -40°C to
+125°C. Minimum and Maximum limits are guaranteed through test, design, or statistical correlation. Typical values represent the
most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise specified, VDD = +12V
(Note 2).
Symbol
Parameter
Conditions
Min
Typ
Max
Units
12.6
V
4.00
V
POWER SUPPLY
VDD
VDD Operating Voltage
UVLO
VDD Undervoltage Lockout
4.0
VDD Rising
3.25
VDD Undervoltage Lockout Hysteresis
IDD
3.6
0.4
V
ns
VDD Undervoltage lockout to Output
delay time
VDD Rising
300
VDD Quiescent Current
IN = INB = VDD
0.95
1.9
mA
TJ = +25°C
0.23
0.26
Ω
TJ = +125°C
0.38
0.43
Ω
TJ = +25°C
0.24
0.28
Ω
TJ = +125°C
0.40
0.47
Ω
VDD = 10V,
IN-OUT = -100mA
TJ = +25°C
0.31
0.34
Ω
TJ = +125°C
0.46
0.51
Ω
VDD = 4.5V,
IN-OUT = -100mA
TJ = +25°C
0.32
0.36
Ω
TJ = +125°C
N-CHANNEL OUTPUT
VDD = 10V,
IN-OUT = -100mA
RON-N
Driver Output Resistance – Pulling Down
(SOT-23-6)
VDD = 4.5V,
IN-OUT = -100mA
RON-N
(LLP-6)
Driver Output Resistance – Pulling Down
0.48
0.55
Ω
Power-off Pull Down Resistance
VDD = 0V, IN-OUT = -10mA
3.3
10
Ω
Power-off Pull Down Clamp Voltage
VDD = 0V, IN-OUT = -10mA
0.85
1.0
V
ILK-N
Output Leakage Current
N_OUT = VDD
6.85
20
µA
IPK-N
Peak Sink Current
CL = 10,000pF
7.6
A
P-CHANNEL OUTPUT
RON-P
Driver Output Resistance – Pulling Up
(SOT-23-6)
RON-P
(LLP-6)
Driver Output Resistance – Pulling Up
VDD = 10V,
IP-OUT = 50mA
TJ = +25°C
2.00
3.00
Ω
TJ = +125°C
2.85
4.30
Ω
VDD = 4.5V,
IP-OUT = 50mA
TJ = +25°C
2.20
3.30
Ω
TJ = +125°C
3.10
4.70
Ω
VDD = 10V,
IP-OUT = 50mA
TJ = +25°C
2.08
3.08
Ω
TJ = +125°C
2.93
4.38
Ω
VDD = 4.5V,
IP-OUT = 50mA
TJ = +25°C
2.28
3.38
Ω
TJ = +125°C
3.18
4.78
Ω
0.001
10
uA
ILK-P
Output Leakage Current
P_OUT = 0
IPK-P
Peak Source Current
CL = 10,000pF
1.3
A
LOGIC INPUT
4
Copyright © 1999-2012, Texas Instruments Incorporated
LM5114
Symbol
VIH
VIL
VHYS
Parameter
Logic 1 Input Voltage
Logic 0 Input Voltage
Logic-Input Hysteresis
Logic-Input Current
CIN
Conditions
Min
LM5114A
0.67X
VDD
LM5114B
2.4
Typ
Max
Units
V
V
LM5114A
0.33X
VDD
V
LM5114B
0.8
V
LM5114A
1.6
LM5114B
0.68
INB = VDD or 0
0.001
Input Capacitance
V
V
10
uA
2.5
pF
SOT-23-6
90
°C/W
LLP-6
60
°C/W
CL = 1000pF
8
ns
CL = 5000pF
45
ns
CL = 10,000pF
82
ns
CL = 1000pF
3.2
ns
CL = 5000pF
7.5
ns
THERMAL RESISTANCE
θJA
Junction to Ambient
SWITCHING CHARACTERISTICS FOR VDD = +10V
tR
Rise Time
tF
Fall Time
CL = 10,000pF
tD-ON
Turn-On Propagation Delay
CL = 1000pF
tD-OFF
Turn-Off Propagation Delay
CL = 1000pF
12.5
ns
LM5114A
5
12
30
ns
LM5114B
6
12
25
ns
LM5114A
5
12
30
ns
LM5114B
6
12
25
ns
Break-before-make Time
2.5
ns
CL = 1000pF
12
ns
CL = 5000pF
41
ns
CL = 10,000pF
74
ns
CL = 1000pF
3.0
ns
CL = 5000pF
7.0
ns
SWITCHING CHARACTERISTICS FOR VDD = +4.5V
tR
Rise Time
tF
Fall Time
CL = 10,000pF
tD-ON
Turn-On Propagation Delay
CL = 1000pF
tD-OFF
Turn-Off Propagation Delay
CL = 1000pF
Break-Before-Make Time
11.3
ns
LM5114A
5
17
36
ns
LM5114B
8
14
27
ns
LM5114A
5
17
36
ns
LM5114B
8
14
27
ns
4.2
ns
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
intended to be functional, but does not guarantee specific performance limits. For guaranteed specifications and conditions, see the Electrical Characteristics.
Note 2: Min and Max limits are 100% production tested at 25°C. Limits over the operating temperature range are guaranteed through correlation using Statistical
Quality Control (SQC) methods. Limits are used to calculate National’s Average Outgoing Quality Level (AOQL).
Copyright © 1999-2012, Texas Instruments Incorporated
5
LM5114
Timing Diagram
(Note 3)
30180405
30180406
Note 3: P_OUT and N_OUT are tied together.
Typical Performance Characteristics
Source Current vs. Output Voltage
30180407
Peak Source Current vs. VDD Voltage
30180409
6
Sink Current vs. Output Voltage
30180408
Peak Sink Current vs. VDD Voltage
30180410
Copyright © 1999-2012, Texas Instruments Incorporated
LM5114
LM5114A Turn-On Propagation Delay vs. VDD
30180434
LM5114B Turn-On Propagation Delay vs. VDD
30180411
UVLO Threshold vs. Temperature
30180413
Copyright © 1999-2012, Texas Instruments Incorporated
LM5114A Turn-Off Propagation Delay vs. VDD
30180435
LM5114B Turn-Off Propagation Delay vs. VDD
30180412
Quiescent Current vs. Temperature
30180415
7
LM5114
Supply Current vs. Frequency
Supply Current vs. Capacitive Load
30180416
Input Voltage vs. Output Voltage
(VDD = 4V, CL = 5000pF)
30180417
Input Voltage vs. Output Voltage
(VDD = 4V, CL = 5000pF)
30180418
Input Voltage vs. Output Voltage
(VDD = 12V, CL = 5000pF)
Input Voltage vs. Output Voltage
(VDD = 12V, CL = 5000pF)
30180427
8
30180426
30180428
Copyright © 1999-2012, Texas Instruments Incorporated
LM5114
Input Voltage vs. Output Voltage
(VDD = 4V, CL = 10000pF)
Input Voltage vs. Output Voltage
(VDD = 4V, CL = 10000pF)
30180429
Input Voltage vs. Output Voltage
(VDD = 12V, CL = 10000pF)
Input Voltage vs. Output Voltage
(VDD = 12V, CL = 10000pF)
30180431
Copyright © 1999-2012, Texas Instruments Incorporated
30180430
30180432
9
LM5114
Typical Applications
30180421
FIGURE 2. Non-inverting Application
30180422
FIGURE 3. Non-Inverting Application with Enable Pin
30180423
FIGURE 4. Inverting Application
30180424
FIGURE 5. Inverting Application with Enable Pin
10
Copyright © 1999-2012, Texas Instruments Incorporated
LM5114
30180425
FIGURE 6. A Simplified Boost Converter
Copyright © 1999-2012, Texas Instruments Incorporated
11
LM5114
Detailed Operating Description
The LM5114 is designed to drive low-side MOSFETs in boost type configurations or to drive secondary synchronous MOSFETs
in isolated topologies. The LM5114 offers both inverting and non-inverting inputs to satisfy requirements for inverting and noninverting gate drive in a single device type. Inputs of the LM5114 are TTL Logic compatible and can withstand the input voltages
up to 14V regardless of the VDD voltage. This allows inputs of the LM5114 to be connected directly to most PWM controllers. The
split outputs of the LM5114 offer flexibility to adjust the turn-on and turn-off speed independently by adding additional impedance
in either the turn-on path and/or the turn-off path.
The LM5114 includes an under-voltage lockout (UVLO) circuit. When the VDD voltage is below the UVLO threshold voltage, the
IN and INB inputs are ignored, and if there is sufficient VDD voltage, the output NMOS is turned on to pull the N_OUT low. In
addition, the LM5114 has an internal PNP transistor in parallel with the output NMOS. Under the UVLO condition, the PNP transistor
will be on and clamp the N_OUT voltage below 1V. This feature ensures the N_OUT remaining low when VDD voltage is not
sufficient to enhance the output NMOS.
The LM5114 has the features necessary to drive low-side enhancement mode GaN FETs. Due to the fast switching speed and
relatively low gate voltage of enhancement mode GaN FETs, PCB layout is crucial to achieve reliable operation. Refer to the section
of layout considerations for details.
Power Dissipation
It is important to keep the power consumption of the driver below the maximum power dissipation limit of the package at the operating
temperature. The total power dissipation of the LM5114 is the sum of the gate charge losses and the losses in the driver due to
the internal CMOS stages used to buffer the output as well as the power losses associated with the quiescent current.
The gate charge losses can be calculated with the total input gate charge as follows.
Or
Where Fsw is switching frequency.
The power dissipation associated with the internal circuit operation of the driver can be estimated with the characterization curves
of the LM5114. For a given ambient temperature, the maximum allowable power loss of the IC can be defined as
Where P is the total power dissipation of the driver.
Layout Considerations
Attention must be given to board layout when using LM5114. Some important considerations include:
1. The first priority in designing the layout of the driver is to confine the high peak currents that charge and discharge the FETs
gate into a minimal physical area. This will decrease the loop inductance and minimize noise issues on the gate.
2. To reduce the loop inductance, the driver should be placed as close as possible to the FETs. The gate trace to and from the
FETs are recommended to be placed closely side by side, or directly on top of one another.
3. A low ESR/ESL ceramic capacitor must be connected close to the IC, between VDD and VSS pins to support the high peak
current being drawn from VDD during turn-on of the FETs. It is most desirable to place the VDD decoupling capacitor on the
same side of the PC board as the driver. The inductance of via holes can impose excessive ringing on the IC pins.
4. The parasitic source inductance, along with the gate capacitor and the driver pull-down path, can form a LCR resonant tank,
resulting in gate voltage oscillations. An optional resistor or ferrite bead can be used to damp the ringing.
12
Copyright © 1999-2012, Texas Instruments Incorporated
LM5114
Physical Dimensions inches (millimeters) unless otherwise noted
SOT-23-6 Outline Drawing
NS Package Number MF06A
LLP–6 Outline Drawing
NS Package Number SDE06A
Copyright © 1999-2012, Texas Instruments Incorporated
13
Notes
Copyright © 1999-2012, Texas Instruments
Incorporated
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