LTC1401 Complete SO-8, 12-Bit, 200ksps ADC with Shutdown DESCRIPTION U FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Complete 12-Bit ADC with Reference in SO-8 Single Supply 3V Operation Sample Rate: 200ksps Power Dissipation: 15mW (Typ) 68dB S/(N + D) and – 72dB THD at 50kHz No Missing Codes Over Temperature Nap Mode with Instant Wake-Up: 1.5mW Sleep Mode: 19.5µW Shutdown Mode: 13.5µW High Impedance Analog Input Input Range (0.5mV/LSB): 0V to 2.048V Internal Reference Can Be Overdriven Externally 3-Wire Interface to DSPs and Processors (SPI and MICROWIRETM Compatible) U APPLICATIONS ■ ■ ■ ■ ■ ■ ■ Low Power and Battery-Operated Systems Handheld or Portable Instruments High Speed Data Acquisition Digital Signal Processing Multiplexed Data Acquisition Systems Telecommunication Digital Radio Spectrum Analysis The LTC1401 has three power saving modes: Nap and Sleep, through the serial interface and Shutdown by setting the SHDN pin to zero. In Nap mode, it consumes only 1.5mW of power and can wake up and convert immediately. In Sleep (Shutdown) mode, it consumes 19.5µW (13.5µW) of power typically. Upon power-up from Sleep or Shutdown mode, a reference ready (REFRDY) signal is available in the serial word to indicate that the reference has settled and the chip is ready to convert. The 3-wire serial port allows compact and efficient data transfer to a wide range of microprocessors, microcontrollers and DSPs. , LTC and LT are registered trademarks of Linear Technology Corporation. MICROWIRE is a trademark of National Semiconductor Corporation. U ■ The LTC ®1401 is a complete 200ksps, 12-bit A/D converter that converts 0V to 2.048V unipolar input and draws only 15mW from a single 3V supply. This easy-to-use device comes complete with a 315ns sample-and-hold and a precision reference. Maximum DC specifications include ±1LSB INL, ±1LSB DNL and 45ppm/°C full-scale drift over temperature. TYPICAL APPLICATION Power Consumption vs Sample Rate 100 3.2MHz CLOCK TA = 25°C Single 3V Supply, 200kHz, 12-Bit Sampling A/D Converter 1 + 10µF VCC SHDN 8 0.1µF MPU LTC1401 2 ANALOG INPUT (0V TO 2.048V) 1.20V 10µF 3 + 0.1µF 4 AIN CONV VREF CLK GND DOUT 7 P1.4 6 P1.3 5 SUPPLY CURRENT (mA) 10 3V 1 NORMAL CONVERSION NAP MODE BETWEEN CONVERSION 0.1 SLEEP MODE BETWEEN CONVERSION P1.2 SERIAL DATA LINK 1401 TA01 SHUTDOWN MODE BETWEEN CONVERSION 0.01 0.001 0.01 0.1 1 10 100 1k 10k 100k 1M SAMPLE RATE (Hz) LTC1401 • TA02 1 LTC1401 W U PACKAGE/ORDER INFORMATION U W W W (Notes 1, 2) Supply Voltage (VCC) ................................................. 7V Analog Input Voltage (Note 3) ..... – 0.3V to (VCC + 0.3V) Digital Input Voltage (Note 4) ....................– 0.3V to 12V Digital Output Voltage .................. – 0.3V to (VCC + 0.3V) Power Dissipation .............................................. 300mW Operating Ambient Temperature Range LTC1401C................................................ 0°C to 70°C LTC1401I ............................................ – 40°C to 85°C Operating Junction Temperature ......................... 125°C Storage Temperature Range ................. – 65°C to 150°C Lead Temperature (Soldering, 10 sec).................. 300°C UW POWER REQUIRE E TS SYMBOL VCC ICC PARAMETER Supply Voltage Supply Current PD Power Dissipation U U A ALOG I PUT U ABSOLUTE MAXIMUM RATINGS ORDER PART NUMBER TOP VIEW VCC 1 8 SHDN AIN 2 7 CONV VREF 3 6 CLK GND 4 5 DOUT LTC1401CS8 LTC1401IS8 S8 PART MARKING S8 PACKAGE 8-LEAD PLASTIC SO 1401 1401I TJMAX = 125°C, θJA = 130°C/ W Consult factory for PDIP packages and Military grade parts. (Note 5) CONDITIONS MIN 2.7 fSAMPLE = 200ksps Nap Mode Sleep Mode Shutdown Mode fSAMPLE = 200ksps Nap Mode Sleep Mode Shutdown Mode ● ● ● ● ● ● ● ● TYP 3.0 5 0.5 6.5 4.5 15 1.5 19.5 13.5 MAX 3.6 10 1.0 15 10 30 3.0 45 30 UNITS V mA mA µA µA mW mW µW µW (Note 5) SYMBOL PARAMETER CONDITIONS MIN VIN Analog Input Range IIN Analog Input Leakage Current During Conversions (Hold Mode) CIN Analog Input Capacitance Between Conversions (Sample Mode) During Conversions (Hold Mode) U U U I TER AL REFERE CE CHARACTERISTICS PARAMETER CONDITIONS VREF Output Voltage IOUT = 0 VREF Output Tempco IOUT = 0 VREF Line Regulation 2.7V ≤ VCC ≤ 3.6V TYP MAX 0 to 2.048 ● V ±1 ● UNITS 45 5 µA pF pF (Note 5) ● MIN TYP MAX 1.180 1.200 1.220 ±10 ±45 UNITS V ppm/°C 0.01 LSB/ V VREF Load Regulation 0 ≤ IOUT ≤ 1mA 2 LSB/mA VREF Wake-Up Time from Sleep or Shutdown Mode CVREF = 10µF 3 ms 2 LTC1401 U CO VERTER CHARACTERISTICS PARAMETER With internal reference (Note 5) CONDITIONS Resolution (No Missing Codes) MIN ● Integral Linearity Error (Note 7) Differential Linearity Error TYP 12 Bits ±1 LSB ● ±1 LSB ● ±6 ±8 LSB LSB ±15 LSB ±10 ±45 ppm/°C MIN TYP MAX UNITS 65 68 65 Full-Scale Error IOUT(REF) = 0 W U DY A IC ACCURACY UNITS ● Offset Error Full-Scale Tempco MAX ● (Note 5) SYMBOL PARAMETER CONDITIONS S/(N + D) Signal-to-Noise Plus Distortion Ratio 50kHz Input Signal 100kHz Input Signal ● THD Total Harmonic Distortion Up to 5th Harmonic 50kHz Input Signal 100kHz Input Signal ● – 72 – 66 – 65 dB dB Peak Harmonic or Spurious Noise 50kHz Input Signal 100kHz Input Signal ● – 74 – 67 – 65 dB dB Intermodulation Distortion fIN1 = 49.853kHz, fIN2 = 53.076kHz – 69 dB Full Power Bandwidth 2 MHz Full Linear Bandwidth (S/(N + D) ≥ 68dB) 50 kHz U IMD dB dB U DIGITAL I PUTS AND OUTPUTS (Note 5) SYMBOL PARAMETER CONDITIONS MIN TYP MAX VIH High Level Input Voltage VCC = 3.6V ● VIL Low Level Input Voltage VCC = 2.7V ● 0.8 V IIN Digital Input Current VIN = 0V to VCC ● ±10 µA CIN Digital Input Capacitance VOH High Level Output Voltage VCC = 2.7V, IO = – 10µA VCC = 2.7V, IO = – 200µA ● ● VOL Low Level Output Voltage VCC = 2.7V, IO = 400µA ● IOZ Hi-Z Output Leakage DOUT VOUT = 0V to VCC ● 2.0 2.40 2.25 UNITS V 5 pF 2.64 2.50 V V 0.13 0.4 V ±10 µA COZ Hi-Z Output Capacitance DOUT 15 pF ISOURCE Output Source Current VOUT = 0 –5 mA ISINK Output Sink Current VOUT = VCC 10 mA 3 LTC1401 WU TI I G CHARACTERISTICS (Note 5) SYMBOL PARAMETER fSAMPLE(MAX) Maximum Sampling Frequency tCONV Conversion Time tACQ Acquisition Time fCLK CLK Frequency tCLK CLK Pulse Width tWK(NAP) Time to Wake Up from Nap Mode t1 CLK Pulse Width to Return to Active Mode ● 60 t2 CONV↑ to CLK↑ Setup Time ● 100 ns t3 CONV↑ After Leading CLK↑ ● 0 ns t4 CONV Pulse Width ● 50 ns t5 Time from CLK↑ to Sample Mode t6 Aperture Delay of Sample-and-Hold Jitter < 50ps t7 Minimum Delay Between Conversion (Note 6) ● 350 550 ns t8 Delay Time, CLK↑ to DOUT Valid CLOAD = 20pF ● 60 120 ns t9 Delay Time, CLK↑ to DOUT Hi-Z CLOAD = 20pF ● 60 120 ns t10 Time from Previous Data Remains Valid After CLK↑ CLOAD = 20pF ● The ● denotes specifications which apply over the full operating temperature range; all other limits and typicals apply to TA = 25°C. Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: All voltage values are with respect to GND. Note 3: When these pin voltages are taken below GND or above VCC, they will be clamped by internal diodes. This product can handle input currents greater than 40mA without latch-up if the pin is driven below GND or above VCC. Note 4: When these pin voltages are taken below GND, they will be clamped by internal diodes. This product can handle input currents greater than 40mA without latch-up if the pin is driven below GND. These pins are not clamped to VCC. 4 CONDITIONS MIN ● fCLK = 3.2MHz TYP MAX 200 kHz 4.1 ● 315 (Note 6) ● 0.1 ● 60 15 µs ns 3.2 MHz ns 350 (Note 8) UNITS ns ns 80 ns 45 ns 50 ns Note 5: VCC = 3V, fSAMPLE = 200kHz, tr = tf = 5ns unless otherwise specified. Note 6: Guaranteed by design, not subject to test. Note 7: Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band. Note 8: The rising edge of CONV starts a conversion. If CONV returns low at a bit decision point during the conversion, it can create small errors. For best performance, ensure that CONV returns low either within 120ns after the conversion starts (i.e., before the first bit decision) or after the 14 clock cycles. (Figure 13 Timing Diagram). LTC1401 U W TYPICAL PERFORMANCE CHARACTERISTICS Differential Nonlinearity vs Output Code Integral Nonlinearity vs Output Code 1.0 1.0 fSAMPLE = 200kHz SIGNAL/(NOISE + DISTORTION)(dB) 0.5 INL ERROR (LSBs) DNL ERROR (LSBs) 80 fSAMPLE = 200kHz 0.5 0 –0.5 0 –0.5 –1.0 –1.0 512 1024 1536 2048 2560 3072 3584 4096 CODE 0 0 40 30 20 TA = 25°C fSAMPLE = 200kHz 0 –10 3500 –30 3000 –40 –50 –60 1500 –70 1000 –80 500 0 10 100 INPUT FREQUENCY (kHz) 10 1000 Supply Current vs Temperature 1.20 1.15 1.10 1.05 1.00 0.95 fSAMPLE = 200kHz fIN = 49.853kHz VCC (VRIPPLE = 1mV) –10 –20 fSAMPLE = 200kHz 10 –30 –40 –50 –60 –70 –80 –5 –4 –3 –2 –1 0 LOAD CURRENT (mA) 1 2 LTC1401 • TPC07 VIN = 3.6V 8 6 4 VIN = 3V VIN = 2.7V 2 –90 –100 0.90 10k 12 SUPPLY CURRENT (mA) 1.25 100 1k SOURCE RESISTANCE (Ω) LTC1401 • TPC06 0 POWER SUPPLY FEEDTHROUGH (dB) REFERENCE VOLTAGE (V) 2500 LTC1401 • TPC05 1.40 1000 2000 Power Supply Feedthrough vs Ripple Frequency 1.30 100 INPUT FREQUENCY (kHz) TA = 25°C 4000 –20 –90 1000 TA = 25°C VIN = –60dB 10 4500 Reference Voltage vs Load Current –7 –6 20 Acquisition Time vs Source Impedance TA = 25°C fSAMPLE = 200kHz LTC1401 • TPC04 1.35 30 LTC1401 • TPC03 tACQ (ns) SPURIOUS-FREE DYNAMIC RANGE (dB) SIGNAL-TO-NOISE RATIO (dB) 50 100 INPUT FREQUENCY (kHz) 40 10 0 60 VIN = –20dB 50 Peak Harmonic or Spurious Noise vs Input Frequency 80 10 60 LTC1401 • TPC02 Signal-to-Noise Ratio (Without Harmonics) vs Input Frequency 70 TA = 25°C fSAMPLE = 200kHz VIN = 0dB 70 0 512 1024 1536 2048 2560 3072 3584 4096 CODE LTC1401 • TPC01 10 S/(N + D) vs Input Frequency and Amplitude 1 10 100 RIPPLE FREQUENCY (kHz) 1000 LTC1401 • TPC08 0 –50 –25 50 25 75 0 TEMPERATURE (˚C) 100 125 LTC1401 • TPC09 5 LTC1401 U U U PIN FUNCTIONS CLK (Pin 6): Clock. This clock synchronizes the serial data transfer. A minimum CLK pulse of 60ns signals the ADC to wake up from Nap or Sleep mode. VCC (Pin 1): Positive Supply, 3V. Bypass to GND (10µF tantalum in parallel with 0.1µF ceramic). AIN (Pin 2): Analog Input. 0V to 2.048V. CONV (Pin 7): Conversion Start Signal. This active high signal starts a conversion on its rising edge. Keeping CLK low and pulsing CONV two/four times will put the ADC into Nap/Sleep mode. VREF (Pin 3): 1.2V Reference Output. Bypass to GND (10µF tantalum in parallel with 0.1µF ceramic). GND (Pin 4): Ground. GND should be tied directly to an analog ground plane. SHDN (Pin 8): Shutdown Input. Pull this pin Low to put the ADC in Shutdown mode and save power (REFRDY will go Low). The device will draw 4.5µA in this mode. DOUT (Pin 5): The A/D conversion result is shifted out from this pin. W FUNCTIONAL BLOCK DIAGRA U ZEROING SWITCH U CSAMPLE VCC AIN GND SHDN VREF 1.20V REF 12-BIT CAPACITIVE DAC COMP CLK CONV 12 CONTROL LOGIC SUCCESSIVE APPROXIMATION REGISTER/PARALLEL TO SERIAL CONVERTER DOUT LTC1401 • BD01 TEST CIRCUITS 3V 3k DOUT DOUT 3k Hi-Z TO VOH VOL TO VOH VOH TO Hi-Z CLOAD CLOAD Hi-Z TO VOL VOH TO VOL VOL TO Hi-Z LTC1401 • TC01 6 LTC1401 U W U U APPLICATIONS INFORMATION The LTC1401 uses a successive approximation algorithm and an internal sample-and-hold circuit to convert an analog signal to a 12-bit serial output based on a precision internal reference. The control logic provides an easy interface to microprocessors and DSPs through serial 3-wire connections. A rising edge on the CONV input starts a conversion. At the start of a conversion the successive approximation register (SAR) is reset. Once a conversion cycle has begun, it cannot be restarted. During conversion, the internal 12-bit capacitive DAC output is sequenced by the SAR from the most significant bit (MSB) to the least significant bit (LSB). Referring to Figure 1, the AIN input connects to the sample-and-hold capacitor during the acquire phase and the comparator offset is nulled by the feedback switch. In this acquire phase, it typically takes 315ns for the sample-and-hold capacitor to acquire the analog signal. During the convert phase, the comparator feedback switch opens, putting the comparator into the compare mode. The input switches CSAMPLE to ground, injecting the analog input charge onto the summing junction. This input charge is successively compared with the binary-weighted charges supplied by the capacitive DAC. Bit decisions are made by the high speed comparator. At the end of a conversion, the DAC output balances the AIN input charge. The SAR contents (a 12-bit data word) which represent the input voltage, are presented through the serial pin DOUT. Dynamic Performance The LTC1401 has excellent high speed sampling capability. FFT (Fast Fourier Transform) test techniques are used to test the ADC’s frequency response, distortion and noise at the rated throughput. By applying a low distortion sine wave and analyzing the digital output using an FFT algorithm, the ADC’s spectral content can be examined for frequencies outside the fundamental. Figure 2a shows a typical LTC1401 FFT plot. 0 fSAMPLE = 200kHz fIN = 49.853516kHz SINAD = 68.5dB THD = –72.4dB VCC = 3V TA = 25°C –10 –20 –30 AMPLITUDE (dB) Conversion Details –40 –50 – 60 –70 –80 –90 –100 –110 –120 0 10 20 30 40 50 60 70 80 90 100 FREQUENCY (kHz) LTC1401 • F02a Figure 2a. LTC1401 Nonaveraged, 4096 Point FFT Plot with 50kHz Input Frequency SAMPLE S1 SAMPLE CSAMPLE HOLD Signal-to-Noise Ratio – AIN + DAC COMP CDAC VDAC S A R DOUT LTC1401 • F01 Figure 1. AIN Input The signal-to-noise plus distortion ratio [S/(N+D)] is the ratio between the RMS amplitude of the fundamental input frequency to the RMS amplitude of all other frequency components at the A/D output. The output is band limited to frequencies from DC to half the sampling frequency. Figure 2a shows a typical spectral content with a 200kHz sampling rate and a 50kHz input. The dynamic performance is excellent for input frequencies up to the Nyquist limit of 100kHz as shown in Figure 2b. 7 LTC1401 U W U U APPLICATIONS INFORMATION 0 –20 –30 –40 AMPLITUDE (dB) Total Harmonic Distortion fSAMPLE = 200kHz fIN = 99.072266kHz SINAD = 65dB THD = –66dB VCC = 3V TA = 25°C –10 –50 Total harmonic distortion (THD) is the ratio of the RMS sum of all harmonics of the input signal to the fundamental itself. The out-of-band harmonics alias into the frequency band between DC and half of the sampling frequency. THD is expressed as: –60 –70 –80 –90 –100 THD = 20log –110 √V22 + V32 + ...Vn2 V1 –120 0 10 20 30 40 50 60 70 80 90 100 FREQUENCY (kHz) LTC1400 • F02b Figure 2b. LTC1401 Nonaveraged, 4096 Point FFT Plot with 100kHz Input Frequency Where V1 is the RMS amplitude of the fundamental frequency and V2 through Vn are the amplitudes of the second through nth harmonics. THD vs input frequency is shown in Figure 4. The LTC1401 has good distortion performance up to the Nyquist frequency and beyond. The effective number of bits (ENOBs) is a measurement of the effective resolution of an ADC and is directly related to the S/(N + D) by the equation: S /(N + D) – 1.76 N= 6.02 12 74 11 68 10 62 9 56 8 50 7 6 5 4 3 2 1 TA = 25°C fSAMPLE = 200kHz 0 10k 100k INPUT FREQUENCY (Hz) 1M LTC1401 • F03 Figure 3. Effective Bits and Signal-to-Noise + Distortion vs Input Frequency 8 0 –10 TA = 25°C fSAMPLE = 200kHz –20 –30 –40 –50 2ND HARMONIC –60 THD –70 3RD HARMONIC –80 –90 –100 10k 100k INPUT FREQUENCY (Hz) 1M LTC1401 • F04 SIGNAL/(NOISE + DISTORTION) (dB) EFFECTIVE NUMBER OF BITS where N is the effective number of bits of resolution and S/(N + D) is expressed in dB. Figure 3 shows ENOBs vs Input Frequency. AMPLITUDE (dB BELOW THE FUNDAMENTAL) Effective Number of Bits Figure 4. Distortion vs Input Frequency Intermodulation Distortion If the ADC input signal consists of more than one spectral component, the ADC transfer function nonlinearity can produce intermodulation distortion (IMD) in addition to THD. IMD is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency. If two pure sine waves of frequencies fa and fb are applied to the ADC input, nonlinearities in the ADC transfer function can create distortion products at sum and differ- LTC1401 U U W U APPLICATIONS INFORMATION ence frequencies of mfa ±nfb, where m and n = 0, 1, 2, 3, etc. For example, the 2nd order IMD terms include (fa + fb) and (fa – fb) while 3rd order IMD terms includes (2fa + fb), (2fa – fb), (fa + 2fb) and (fa – 2fb). If the two input sine waves are equal in magnitude, the value (in decibels) of the 2nd order IMD products can be expressed by the following formula. IMD( fa ± fb) = 20log Amplitude at (fa ± fb) Amplitude at fa Figure 5 shows the IMD performance at a 50kHz input. 0 fSAMPLE = 200kHz fa = 49.853kHz fb = 53.076kHz TA = 25°C fa –10 –20 AMPLITUDE (dB) –30 –40 –50 2fa – fb – 60 2fb + fa 3fb –70 –80 fb 2fa + fb 2fa 3fa fa + fb 2fb 2fb – fa fb – fa The analog input of the LTC1401 is easy to drive. It draws only one small current spike while charging the sampleand-hold capacitor at the end of a conversion. During conversion, the analog input draws only a small leakage current. The only requirement is that the amplifier driving the analog input must settle after the small current spike before the next conversion starts. Any op amp that settles in 315ns to small load current transients will allow maximum speed operation. If a slower op amp is used, more settling time can be provided by increasing the time between conversions. Suitable devices capable of driving the ADC’s AIN input include the LT ® 1498 and the LT1630 op amps. The following list is a summary of the op amps that are suitable for driving the LTC1401, more detailed information is available in the Linear Technology databooks and the LinearViewTM CD-ROM. LT1215/LT1216: Dual and quad 23MHz, 50V/µs single supply op amps. Single 5V to ±15V supplies, 6.6mA specifications, 90ns settling to 0.5LSB. –90 –100 –110 –120 0 Driving the Analog Input 10 20 30 40 50 60 70 80 90 100 FREQUENCY (kHz) LTC1401 • F05 Figure 5. Intermodulation Distortion Plot Peak Harmonic or Spurious Noise The peak harmonic or spurious noise is the largest spectral component excluding the input signal and DC. This value is expressed in decibels relative to the RMS value of a full-scale input signal. Full Power and Full Linear Bandwidth The full power bandwidth is the input frequency at which the amplitude of the reconstructed fundamental is reduced by 3dB for a full-scale input signal. The full linear bandwidth is the input frequency at which the S/(N+D) has dropped to 68dB (11 effective bits). LT1229/LT1230: Dual and quad 100MHz current feedback amplifiers. ±2V to ±15V supplies, 6mA supply current each amplifier. Low noise. Good AC specs. LT1498/LT1499: Dual or quad 10MHz, 6V/µs, single 2.2V to ±15V supplies, 1.7mA supply current per amplifier, input/output swings rail-to-rail. Excellent AC and DC specs. LT1630: Dual or quad 30MHz, 10V/µs, single 2.7V to ±15V supplies, 3.5mA supply current per amplifier, input/output swings rail-to-rail. Good AC and DC specs. Internal Reference The LTC1401 has an on-chip, temperature compensated, curvature corrected, bandgap reference, which is factory trimmed to 1.20V. It is internally connected to the DAC and LinearView is a trademark of Linear Technology Corporation. 9 LTC1401 U W U U APPLICATIONS INFORMATION is available at Pin 3 to provide up to 1mA current to an external load. For minimum code transition noise, the reference output should be decoupled with a capacitor to filter wideband noise from the reference (10uF tantalum in parallel with a 0.1uF ceramic is recommended). The VREF pin can be driven with a DAC or other means to provide input span adjustment. The VREF pin must be driven to at least 1.25V to prevent conflict with the internal reference. The reference should not be driven to more than 3V. UNIPOLAR OPERATION AND ADJUSTMENT Figure 8 shows the ideal input/output characteristics for the LTC1401. The code transitions occur midway between successive integer LSB values (i.e., 0.5LSB, 1.5LSB, 2.5LSB, ... FS – 1.5LSB ). The output code is natural binary with 1LSB = 2.048/4096 = 0.5mV. 1LSB = FS = 2.048 4096 4096 111...111 111...110 111...101 OUTPUT CODE Figure 6 shows an LT1360 op amp driving the reference pin. Figure 7 shows a typical reference (LT1634-1.25) connected to the LTC1401. This will provide improved drift (equal to the maximum 25ppm/°C of the LT16341.25) and a 2.1338V full scale. 111...100 UNIPOLAR ZERO 000...011 000...010 INPUT RANGE 1.707 • VREF(OUT) + VREF(OUT) ≥ 1.25V 3V 000...001 AIN VCC 000...000 LTC1401 VREF LT1360 – 0V 1 LSB FS – 1LSB INPUT VOLTAGE (V) LTC1401 • F08 Figure 8. LTC1401 Unipolar Transfer Characteristics 3Ω 10µF Unipolar Offset and Full-Scale Error Adjustments GND LTC1401 • F06 Figure 6. Driving the VREF with the LT1360 Op Amp 3V INPUT RANGE 1.707 • VREF (= 2.1338V) AIN VCC 10V LTC1401 VIN VREF VOUT LT1634-1.25 3Ω 10µF GND GND LTC1401 • F07 Figure 7. Supplying a 2.5V Reference Voltage to the LTC1401 with the LT1634-1.25 10 In applications where absolute accuracy is important, the offset and full-scale errors can be adjusted to zero. Offset error must be adjusted before full-scale error. Figure 9a shows the extra components required for full scale error adjustment. If both offset and full-scale adjustments are needed, the circuit in Figure 9b can be used. For zero offset error, apply 0.25mV (i.e., 0.5LSB) at the input and adjust the offset trim until the LTC1401 output code flickers between 0000 0000 0000 and 0000 0000 0001. For zero full-scale error, apply an analog input of 2.04725V ( FS – 1.5LSB or last code transition ) at the input and adjust R5 until the LTC1401 output code flickers between 1111 1111 1110 and 1111 1111 1111. LTC1401 U U W U APPLICATIONS INFORMATION optimum performance, a 10µF surface mount AVX capacitor in parallel with a 0.1µF ceramic is recommended for the VCC and VREF pins. The capacitors must be located as close to the pins as possible. The traces connecting the pins and the bypass capacitors must be kept short and should be made as wide as possible. R1 50Ω + VIN A1 – AIN R4 100Ω R2 10k LTC1401 R3 10k FULL-SCALE ADJUST GND ADDITIONAL PINS OMITTED FOR CLARITY ±20LSB TRIM RANGE LTC1401 • F09a Figure 9a. LTC1401 Full-Scale Adjust Circuit ANALOG INPUT 0V TO 2.048V R1 10k + 10k R2 10k 3V AIN A1 – R9 20Ω R4 100k LTC1401 R5 4.3k FULL-SCALE ADJUST R3 100k R6 400Ω R7 100k 3V R8 10k OFFSET ADJUST Input signal leads to AIN and signal return leads from GND (Pin 4) should be kept as short as possible to minimize noise coupling. In applications where this is not possible, a shielded cable between the analog input signal and the ADC is recommended. Also, any potential difference in grounds between the analog signal and the ADC appears as an error voltage in series with the analog input signal. Attention should be paid to reducing the ground circuit impedance as much as possible. Figure 10 shows the recommended system ground connections. All analog circuitry grounds should be terminated at the LTC1401 GND pin. The ground return to the power supply from Pin 4 should be low impedance for noise free operation. Digital circuitry grounds must be connected to the digital supply common. ANALOG SUPPLY GND DIGITAL SUPPLY 3V GND 3V LTC1401 • F09b Figure 9b. LTC1401 Offset and Full-Scale Adjust Circuit + + BOARD LAYOUT AND BYPASSING Wire wrap boards are not recommended for high resolution or high speed A/D converters. To obtain the best performance from the LTC1401, a printed circuit board is required. Layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. In particular, care should be taken not to run any digital traces alongside an analog signal trace or underneath the ADC. The analog input should be screened by GND. High quality tantalum and ceramic bypass capacitors should be used at the VCC and VREF pins as shown in the Typical Application on the first page of this datasheet. For GND VCC LTC1401 GND VCC DIGITAL CIRCUITRY LTC1401 • F10 Figure 10. Power Supply Connection Power-Down Mode Upon power up, the LTC1401 is initialized to the active state and is ready for conversion. However, the chip can be easily placed into Nap or Sleep mode by exercising the right combination of CLK and CONV signals. In Nap mode, all power is off except the internal reference which remains active and provides 1.20V output voltage to the other 11 LTC1401 U W U U APPLICATIONS INFORMATION circuitry. In this mode, the ADC draws only 1.5mW of power instead of 15mW (for minimum power, the logic inputs must be within 500mV of the supply rails). The wake-up time from Nap mode to active mode is 350ns. In Sleep mode, power consumption is reduced to 19.5µW by cutting off the supply to the comparator and reference. Figure 11 illustrates power-down methods for the LTC1401. The chip enters Nap mode by keeping the CLK signal low and pulsing the CONV signal twice. For Sleep mode operation, CONV signal should be pulsed four times while CLK is kept low. NAP and SLEEP modes are activated on the falling edge of the CONV pulse. By pulling SHDN low, the LTC1401 enters Shutdown mode and power consumption drops to 13.5µW. Once SHDN goes high, the LTC1401 returns to active mode or the LTC1401 returns to active mode by pulsing the CLK signal if the device has entered Nap/Sleep mode. During the transistion from Sleep mode to active mode, the VREF voltage ramp-up time is a function of its loading conditions. With a 10µF bypass capacitor, the wake-up time from Sleep mode is typically 3ms. A REFRDY signal is activated once the reference has settled and is ready for an A/D conversion. This REFRDY bit is sent to the DOUT pin as the first bit followed by the 12-bit data word (refer to Figure 12). DIGITAL INTERFACE The digital interface requires only three digital lines. CLK and CONV are both inputs, and the DOUT output provides the conversion result in serial form. Figures 12 and 13 show the digital timing waveform of the LTC1401 during the Analog to Digital Conversion. The CONV rising edge starts the conversion. Once initiated, it can not be restarted until the conversion is completed. If the time from the CONV signal to the CLK rising edge is less than t2, the digital output will be delayed by one clock cycle. The digital output data is updated on the rising edge of the CLK line. The digital output data consists of a REFRDY bit followed by the valid 12-bit data word. DOUT data should be captured by the receiving system on the rising CLK edge. Data remains valid for a minimum time of t10 after the rising CLK edge to allow capture to occur. CLK t1 t1 CONV NAP SLEEP VREF REFRDY LTC1401 • F11 NOTE: NAP AND SLEEP ARE INTERNAL SIGNALS. REFRDY APPEARS AS THE FIRST BIT IN THE DOUT WORD. Figure 11. Nap Mode and Sleep Mode Waveforms 12 LTC1401 U U W U APPLICATIONS INFORMATION t2 t7 t3 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 16 1 2 CLK t4 t5 CONV t6 INTERNAL S/H STATUS tACQ SAMPLE HOLD SAMPLE HOLD t8 Hi-Z DOUT REFRDY D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Hi-Z REFRDY REFRDY BIT + 12-BIT DATA WORD tCONV tSAMPLE LT1401 • F12 Figure 12. ADC Digital Timing Waveform CLK CLK VIH VIH t8 t9 t 10 90% VOH D OUT D OUT VOL 10% LTC1401 • F13 Figure 13. CLK to DOUT Delay 13 LTC1401 U TYPICAL APPLICATIONS Interface to the TMS320C50’s TDM Serial Port (Frame Sync is Generated from TFSX) 5V 3V 1 + UNIPOLAR INPUT 0.1µF 2 3 SHDN VCC AIN QC TMS320C50 8 10µF CLR LD 2.5MHz EXTERNAL CLOCK CLK LTC1401 VREF CONV DOUT CLK A B C D TCLKX TCLKR TFSX TFSR 6 7 5 P T 74HC161 CLKOUT 20MHz TDR GND + 0.1µF 10µF 4 LTC1401 • TA04a Logic Analyzer Waveforms Show 6.4µs Throughput Rate (Input Voltage = 0.765V, Output Code = 0101 1111 1010 = 153010) 1401 TA5b Data from the LTC1401 Loaded into the TMS320C50’s TRCV Register X RDY D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X 1401 TA4c Data Stored in the TMS320C50’s Memory (in Right Justified Format) 0 0 0 RDY D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 1401 TA4d 14 LTC1401 U TYPICAL APPLICATIONS TMS320C50 Code for Circuit THIS PROGRAM DEMONSTRATES THE LTC1401 INTERFACE TO THE TMS320C50. FRAME SYNC PULSE IS GENERATED FROM TFSX. DATA SHIFT CLOCK IS DERIVED FROM CLKOUT. *Initialization* .mmregs ;- - Initialized data memory to zero .ds 0F00h DATA0 .word 0 DATA1 .word 0 DATA2 .word 0 DATA3 .word 0 DATA4 .word 0 DATA5 .word 0 ;- - Set up the ISR vector .ps 080Ah rint : B RECEIVE xint : B TRANSMIT trnt : B TREC txnt : B TTRANX ;- - Setup the reset vector .ps 0A00h .entry START: ; Defines global symbolic names ; Initialize data to zero ; Begin sample data location ;. ; Location of data ;. ;. ; End sample data location ; Serial ports interrupts ; 0A; ; 0C; ; 0E; ; 10; *TMS320C50 Initialization* SETC INTM ; Temporarily disable all interrupts LDP #0 ; Set data page pointer to zero OPL #0834h, PMST ; Set up the PMST status and control register LACC #0 SAMM CWSR ; Set software wait state to 0 SAMM PDWSR ; *Configure Serial Port* SPLK #0028h, TSPC ; Set TDM Serial Port ; TDM = 0 Stand Alone mode ; DLB = 0 Not loop back ; FO = 0 16 Bits ; FSM = 1 Burst Mode ; MCM = 0 CLKR is generated externally ; TXM = 1 FSX as output pin ; Put serial port into reset ; (XRST = RRST = 0) SPLK #00E8h, TSPC ; Take Serial Port out of reset ; (XRST = RRST = 1) SPLK #0FFFFh, IFR ; Clear all the pending interrupts *Start Serial Communication* SACL TDXR ; Generate frame sync pulse SPLK #040h, IMR ; Turn on TRNT receiver interrupt CLRC INTM ; Enable interrupt CLRC SXM ; For Unipolar input, set for right shift ; with no sign extension MAR *AR7 ; Load the auxiliary register pointer with seven LAR AR7, #0F00h ; Load the auxiliary register seven with #0F00h ; as the begin address for data storage WAIT: NOP ; Wait for a receive interrupt NOP ; NOP ; SACL TDXR ; !! Regenerate the frame sync pulse B WAIT ; ; - - - - - - - end of main program - - - - - - - - - - ; *Receiver Interrupt Service Routine* TREC: LAMM TRCV ; Load the data received from LTC1401 SFR ; Shift right two times SFR ; AND #1FFFh, 0 ; ANDed with #1FFFh ; For converting the data to right ; justified format ; SACL *+, 0 ; Write to data memory pointed by AR7 and ; Increase the memory address by one LACC AR7 ; SUB #0F05h,0 ; Compare to end sample address #0F05h BCND END_TRCV, GEQ ; If the end sample address has exceeded jump to END_TRCV ; SPLK #040h, IMR ; Else re-enable the TRNT receive interrupt RETE ; Return to main program and enable interrupt *After Obtained the Data from LTC1401, Program Jump to END_TRCV* END_TRCV: SPLK #002h, IMR ; Enable INT2 for program to halt CLRC INTM SUCCESS: B SUCCESS *Fill the unused interrupt with RETE, to avoid program get “lost”* TTRANX: RETE RECEIVE: RETE TRANSMIT: RETE INT2: B halt ; Halts the running CPU 15 LTC1401 U TYPICAL APPLICATIONS LTC1401 Interface to the ADSP2181’s SPORT0 (Frame Sync is Generated from RFS) 3V 8 1 + 10µF UNIPOLAR INPUT 0.1µF 2 3 VCC CLK LTC1401 AIN CONV VREF + 10µF ADSP2181 SHDN DOUT 6 SCLKO 7 RFS 5 DR0 GND 0.1µF LTC1401 • TA05a Logic Analyzer Waveforms Show 4.8µs Throughput Rate (Input Voltage = 1.604V, Output Code = 1100 1000 1000 = 320810) 1401 TA04b Data from the LTC1401 (Normal Mode) X RDY D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X LTC1401 • TA05c Data Stored in the ADSP2181’s Memory (Normal Mode, SLEN = D) 0 0 0 RDY D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 LTC1401 • TA05d 16 LTC1401 U TYPICAL APPLICATIONS ADSP2181 Code for Circuit THIS PROGRAM DEMONSTRATES THE LTC1401 INTERFACE TO THE ADSP-2181. FRAME SYNC PULSE IS GENERATED FROM RFS. DATA SHIFT CLOCK IS INTERNALLY GENERATED. /*Section 1: Initialization*/ .module/ram/abs = 0 adspltc; /*define the program module*/ jump start; /*jump over interrupt vectors*/ nop; nop; nop; rti; rti; rti; rti; /*code vectors here upon IRQ2 int*/ rti; rti; rti; rti; /*code vectors here upon IRQL1 int*/ rti; rti; rti; rti; /*code vectors here upon IRQL0 int*/ rti; rti; rti; rti; /*code vectors here upon SPORT0 TX int*/ ax0 = rx0; /*Section 5*/ dm (0x2000) = ax0; /*begin of SPORT0 receive interrupt*/ rti; /* */ /* */ /*end of SPORT0 receive interrupt*/ rti; rti; rti; rti; /*code vectors here upon /IRQE int*/ rti; rti; rti; rti; /*code vectors here upon BDMA interrupt*/ rti; rti; rti; rti; /*code vectors here upon SPORT1 TX (IRQ1) int*/ rti; rti; rti; rti; /*code vectors here upon SPORT1 RX (IRQ0) int*/ rti; rti; rti; rti; /*code vectors here upon TIMER int*/ /*code vectors here upon POWER DOWN int*/ rti; rti; rti; rti; /*Section 2: Configure SPORT0*/ start: /*to configure SPORT0 control reg*/ /*SPORT0 address = 0x3FF6*/ /*RFS is used for frame sync generation*/ /*RFS is internal, TFS is not used*/ /*bit 0-3 = Slen*/ /*F = 15 = 1111*/ /*E = 14 = 1110*/ /*D = 13 = 1101*/ /*bit 4,5 data type right justified zero filled MSB*/ /*bit 6 INVRFS = 0*/ /*bit 7 INVTFS = 0*/ /*bit 8 IRFS=1 receive internal frame sync*/ /*bit 9,10,11 are for TFS (don’t care)*/ /*bit 12 RFSW=0 receive is normal mode*/ /*bit 13 RTFS=1 receive is framed mode*/ /*bit 14 ISCLK = 1 clock is internal*/ /*bit 15 multichannel mode = 0*/ ax0 = 0x6F0D; dm (0x3FF6) =ax0; /*Section 3: configure CLKDIV and RFSDIV, setup interrupts*/ /*to configure CLKDIV reg*/ ax0= 4; dm(0x3FF5) =ax0; /*set the serial clock divide modulus reg SCLKDIV*/ /*the input clock frequency = 16.67MHz*/ /*CLKOUT frequency = 2x = 33MHz*/ /*SCLK= 1/2*CLKOUT*1/(SCLKDIV+1)*/ /*for SCLKDIV = 4, SCLK = 33/10 = 3.3MHz*/ /*to Configure RFSDIV*/ ax0 = 15; /*set the RFSDIV reg = 15*/ /*=> the frame sync pulse for every 16 SCLK*/ /*if frame sync pulse in every 15 SCLK, ax0=14*/ dm(0x3FF4) =ax0; /*to setup interrupt*/ ifc= 0x0066; /*clear any extraneous SPORT interrupts*/ icntl= 0; /*IRQXB = level sensitivity*/ /*disable nesting interrupt*/ imask= 0x0020; /*bit 0 = timer int = 0*/ /*bit 1 = SPORT1 or IRQ0B int = 0*/ /*bit 2 = SPORT1 or IRQ1B int = 0*/ /*bit 3 = BDMA int = 0*/ /*bit 4 = IRQEB int = 0*/ /*bit 5 = SPORT0 receive int = 1*/ /*bit 6 = SPORT0 transmit int = 0*/ /*bit 7 = IRQ2B int = 0*/ /*enable SPORT0 receive interrupt*/ /*Section 4: Configure System Control Register and Start Communication*/ /*to configure system control reg*/ ax0 = dm(0x3FFF); /*read the system control reg*/ ay0 = 0xFFF0; ar = ax0 AND ay0; /*set wait state to zero*/ ay0 = 0x1000; ar = ar OR ay0; /*bit 12 = 1, enable SPORT0*/ dm(0x3FFF) = ar; /*frame sync pulse regenerated automatically*/ cntr = 5000; do waitloop until ce; nop; nop; nop; nop; nop; nop; waitloop: nop; rts; .endmod; 17 LTC1401 U TYPICAL APPLICATIONS Quick Look Circuit for Converting Data to Parallel Format 3V 1 V CC + 10µF SHDN 8 5V CONV 0.1µF LTC1401 1.20V REFERENCE OUTPUT ANALOG INPUT (0V TO 2.048V) 2 CONV AIN 3 V REF + 10µF 0.1µF 4 GND CLK DOUT 7 12 SRCLR 15 1 2 3 4 5 6 7 9 SRCLR 15 1 2 3 4 5 6 7 9 QA QB 11 QC SRCK 74HC595 QD 14 QE SER QF 13 QG G QH QH' 6 5 3-WIRE SERIAL INTERFACE LINK 12 CLK RCK QA QB 11 QC SRCK 74HC595 QD 14 QE SER QF 13 QG G QH QH' RCK D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 REFRDY LTC1401 • TA03 18 LTC1401 U PACKAGE DESCRIPTION Dimensions in inches (millimeters) unless otherwise noted. S8 Package 8-Lead Plastic Small Outline (Narrow 0.150) (LTC DWG # 05-08-1610) 0.189 – 0.197* (4.801 – 5.004) 8 7 6 5 0.150 – 0.157** (3.810 – 3.988) 0.228 – 0.244 (5.791 – 6.197) 1 0.010 – 0.020 × 45° (0.254 – 0.508) 0.008 – 0.010 (0.203 – 0.254) 0.053 – 0.069 (1.346 – 1.752) 0°– 8° TYP 0.016 – 0.050 0.406 – 1.270 0.014 – 0.019 (0.355 – 0.483) 2 3 4 0.004 – 0.010 (0.101 – 0.254) 0.050 (1.270) TYP *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. SO8 0996 19 LTC1401 U TYPICAL APPLICATIONS Interface to the TMS320C50’s TDM Serial Port (Frame Sync is Generated from TFSX) 5V 3V 1 + UNIPOLAR INPUT 0.1µF 10µF CLR LD 2.5MHz EXTERNAL CLOCK 2 3 SHDN VCC AIN QC TMS320C50 8 LTC1401 VREF 7 CONV 5 DOUT CLK A B C D TCLKX TCLKR TFSX TFSR 6 CLK P T 74HC161 CLKOUT 20MHz TDR GND + 0.1µF 10µF 4 LTC1401 • TA04a LTC1401 Interface to the ADSP2181’s SPORT0 (Frame Sync is Generated from RFS) 3V 8 1 + 10µF 0.1µF UNIPOLAR INPUT 2 3 SHDN VCC LTC1401 AIN CONV VREF + 10µF ADSP2181 CLK DOUT 6 SCLKO 7 RFS 5 DR0 GND 0.1µF LTC1401 • TA05a RELATED PARTS 12-Bit Parallel Output ADCs PART NUMBER DESCRIPTION COMMENTS LTC1273/LTC1275/LTC1276 Complete 5V Sampling 12-Bit ADCs with 70dB SINAD at Niquist Lower Power and Cost Effective for fSAMPLE ≤ 300ksps LTC1274/LTC1277 Low Power 12-Bit ADCs with Nap and Sleep Mode Shutdown Lowest Power (10mW) fSAMPLE ≤ 100ksps LTC1278/LTC1279 High Speed Sampling 12-Bit ADCs with Shutdown Cost Effective 12-Bit ADCs with Convert Start Input Best for 300ksps < fSAMPLE ≤ 600ksps LTC1282 Complete 3V 12-Bit ADCs with 12mW Power Dissipation Fully Specified for 3V Powered Applications, fSAMPLE ≤ 140ksps LTC1409 Low Power 12-Bit, 800ksps Sampling ADC Best Dynamic Performance fSAMPLE ≤ 800ksps, 80mW Dissipation LTC1410 12-Bit, 1.25Msps Sampling ADC with Shutdown Best Dynamic Performance, THD = – 84dB and SINAD = 71dB at Nyquist 12-Bit Serial Output ADCs PART NUMBER VCC SAMPLE RATE POWER DISSIPATION LTC1285/LTC1288 LTC1286/LTC1298 DESCRIPTION 3V 7.5/6.6ksps 0.48mW 3V, One or Two Input, Micropower, SO-8 5V 12.5/11.1ksps 1.25mV One or Two Input, Micropower, SO-8 LTC1290 5/±5V 50ksps 30mW 8 Input, Full-Duplex Serial I/O LTC1296 5/±5V 46.5ksps 30mW 8 Input, Half-Duplex Serial I/O, Power Shutdown Output LTC1400 5/±5V 400ksps 75mW Complete 12-Bit, 400ksps, SO-8 ADC with Shutdown LTC1404 5/±5V 600ksps 75mW Complete 12-Bit, 600ksps, SO-8 ADC with Shutdown 20 Linear Technology Corporation 1401f LT/TP 0598 4K • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408)432-1900 ● FAX: (408) 434-0507 ● www.linear-tech.com LINEAR TECHNOLOGY CORPORATION 1998