RENESAS M306V7FGFP

M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
REJ03B0094-0100Z
Rev.1.00
May 18, 2004
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
1. DESCRIPTION
The M306V7MG/MH/MJ/MJA-XXXFP and M306V7FG/FH/FJ/FJAFP are single-chip microcomputers using the high-performance silicon gate CMOS process using a M16C/60 Series CPU core and are packaged
in a 100-pin plastic molded QFP. These single-chip microcomputers operate using sophisticated instructions featuring a high level of instruction efficiency. With 1M bytes of address space, they are capable of
executing instructions at high speed. They also feature a built-in OSD display function and data slicer,
making them ideal for closed caption and ID1 for 525p.
1.1 Features
• Memory size ........................................ Refer to Figure 1.5.1 ROM development
<RAM> 10K bytes to 16K bytes
<OSD ROM> 60K bytes
<OSD RAM> 2.2K bytes
• Shortest instruction execution time ...... 62.5 ns (f(XIN)=16 MHz)
• Power source voltage .......................... VCCE (5V system I/O power supply) 4.75 V to 5.25V
VCCI (internal logic power supply)
3.15 V to 3.45V
• Power consumption ............................. 415mW
• Interrupts .............................................. 22 internal and 3 external interrupt sources, 4 software
interrupt sources; 7 levels
• Multifunction 16-bit timer ...................... 2 output timers + 3 input timers + 3 timers
• Serial I/O .............................................. 4 units
UART/clock synchronous: 2
Multi-master I2C-BUS interface 0 (2 systems): 1
Multi-master I2C-BUS interface 1 (1 system): 1
• DMAC .................................................. 2 channels (trigger: 23 sources)
• A-D converter ....................................... 8 bits ✕ 6 channels
• D-A converter ....................................... 8 bits ✕ 2 channels
• Data slicer ............................................ 2 circuits (closed caption and video ID for 525p are available)
• HSYNC counter ..................................... 1 circuit (2 systems)
• OSD function ....................................... 1 circuit
• Watchdog timer .................................... 1 circuit
• Programmable I/O ............................... 76 lines
• Memory expansion .............................. Available
• Chip select output ................................ 4 lines
• Clock generating circuit ....................... 3 built-in clock generation circuits
1.2 Applications
TV with a closed caption and ID1
Rev.1.00
May 18, 2004
page 1 of 296
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
------Table of Contents-----1. DESCRIPTION .............................................. 1
1.1 Features ................................................... 1
1.2 Applications ............................................. 1
1.3 Pin Configuration ..................................... 3
1.4 Block Diagram ......................................... 4
1.5 Performance Outline ................................ 5
2. OPERATION OF FUNCTIONAL BLOCKS .... 9
2.1 Memory .................................................... 9
2.2 Central Processing Unit (CPU) .............. 15
2.3 Reset ..................................................... 18
2.4 Processor Mode ..................................... 23
2.5 Clock Generating Circuit ........................ 36
2.6 Protection ............................................... 46
2.7 Interrupts ................................................ 47
2.8 Watchdog Timer .................................... 68
2.9 DMAC .................................................... 70
2.10 Timer .................................................... 80
2.11 Serial I/O ............................................ 100
2.12 A-D Converter .................................... 146
2.13 D-A Converter .................................... 161
2.14 Data Slicer ......................................... 163
2.15 HSYNC Counter ................................ 176
2.16 OSD Functions .................................. 177
2.16.1 Triple Layer OSD ........................ 183
2.16.2 Display Position .......................... 185
2.16.3 Dot Size ...................................... 189
2.16.4 Clock for OSD ............................. 190
2.16.5 Field Determination Display ........ 193
2.16.6 Memory for OSD ......................... 195
2.16.7 Character Color .......................... 205
2.16.8 Character Background Color ...... 205
2.16.9 OUT1, OUT2 Signals .................. 210
2.16.10 Attribute .................................... 211
2.16.11 Automatic Solid Space Function .... 216
2.16.12 Particular OSD Mode Block ...... 217
2.16.13 Multiline Display ........................ 219
2.16.14 SPRITE OSD Function ............. 220
2.16.15 Window Function ...................... 223
2.16.16 Blank Function .......................... 224
2.16.17 Raster Coloring Function .......... 227
2.16.18 Scan Mode ................................ 229
Rev.1.00
May 18, 2004
page 2 of 296
2.16.19 R, G, B Signal Output Control ... 229
2.16.20 OSD Reserved Register ........... 230
2.17 Programmable I/O Ports .................... 231
3. USAGE PRECAUTION .............................. 246
3.1 Timer A (timer mode) ............................... 246
3.2 Timer A (event counter mode) ................. 246
3.3 Timer A (one-shot timer mode) ................ 246
3.4 Timer A (pulse width modulation mode) .. 246
3.5 Timer B (timer mode, event counter mode) ... 247
3.6 Timer B (pulse period, pulse width
measurement mode) ................................ 247
3.7 A-D Converter .......................................... 247
3.8 Stop Mode and Wait Mode ...................... 247
3.9 Interrupts .................................................. 248
3.10 About Flash memory version and mask ROM
............................................................... 249
4. ITEMS TO BE SUBMITTED WHEN
ORDERING MASKED ROM VERSION ..... 250
5. ELECTRICAL CHARACTERISTICS .......... 251
5.1. Absolute Maximum Ratings ................ 251
5.2 Recommended Operating Conditions .. 252
5.3 Electrical Characteristics ..................... 253
5.4 A-D Conversion Characteristics ........... 254
5.5 D-A Conversion Characteristics ........... 254
5.6 Analog R, G, B Output Characteristics 254
5.7 Timing Requirements ........................... 256
5.8 Switching Characteristics ..................... 258
5.9 Measurement Circuit ............................ 259
5.10 Timing Diagram ................................. 260
6. PACKAGE OUTLINE ................................. 264
7. Flash Memory ............................................ 265
7.1 Description ........................................... 265
7.2 CPU Rewrite Mode .............................. 267
7.3 Parallel I/O Mode ................................. 279
7.4 Standard Serial I/O Mode .................... 280
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
1.3 Pin Configuration
Figure 1.3.1 shows the pin configuration (top view).
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
P10/D8
P11/D9
P12/D10
P13/D11
P14/D12
P15/D13
P16/D14
P17/D15
P20/A0
P21/A1
P22/A2
P23/A3
P24/A4
P25/A5
P26/A6
P27/A7
VsYNC
P30/A8
HsYNC
P31/A9
P32/A10
P33/A11
P34/A12
P35/A13
P36/A14
P37/A15
P40/A16
P41/A17
P42/A18
P43/A19
PIN CONFIGURATION (top view)
81
50
82
83
84
85
86
87
49
48
47
46
45
44
88
89
90
91
92
93
43
42
41
40
39
38
M306V7MG/MH/MJ/MJA-XXXFP
M306V7FG/FH/FJ/FJAFP
94
95
96
97
98
99
100
37
36
35
34
33
32
31
P44/CS0
P45/CS1
P46/CS2
P47/CS3
P50/WRL/WR
P51/WRH/BHE
P52/RD
P53/BCLK
P54/HLDA
P55/HOLD
P56/ALE
P57/RDY/CLKOUT
P60/CTS0/RTS0
P61/CLK0
P62/RxD0
P63/TXD0
B/DIGB1
G/DIGG1
R/DIGR1
P67/SDA2*
VHOLD1
HLF1
* P94/DA1/SCL3/RXD2
* P93/DA0/SDA3/TXD2
P92/TB2IN/DIGR0
P91/TB1IN
P90/TB0IN
BYTE
CNVss
P87/XCIN/DIGG0
P86/XCOUT/DIGB0
RESET
XOUT
VSS
XIN
VCCI
OSC1/OSCHLF
OSC2
P83 /INT1
P82/INT0
OUT1
OUT2
P77/HC1
P76/TA3 OUT
P75/HC0
P74/TA2 OUT
P73/CTS2, RTS2
* P72/SCL2/CLK2
* P71/SCL1/RXD2
* P70/SDA1/TXD2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
P07/D7
P06/D6
P05/D5
P04/D4
P03/D3
P02/D2
P01/D1
P00/D0
P107/AN5/DIGR2
P106/AN4/DIGG2
P105/AN3/DIGB2
P104/AN2
P103/AN1
P102/AN0
VHOLD2
HLF2
CVIN2
TVSETB
VCCE
CVIN1
* : VCCE voltage support pin
Package: 100P6S-A
Figure 1.3.1 Pin configuration (top view)
Rev.1.00
May 18, 2004
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M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
1.4 Block Diagram
Figure 1.4.1 is a block diagram.
8
I/O ports
Port P0
8
Port P1
8
Port P2
8
Port P3
Port P4
UART0/clock synchronous SI/O
Data slicer0
Data slicer1
Multi-master I2C-bus
interface 0
HSYNC counter
Registers
Multi-master I2C-bus
interface 1
(2 channels)
INTB
RA M
(Note 2)
Stack pointer
ISP
USP
FLG
Multiplier
Note 1. ROM capacity changes with kinds.
Note 2. RAM capacity changes with kinds.
Figure 1.4.1 Block diagram
Rev.1.00
May 18, 2004
page 4 of 296
6
SB
PC
Vector table
Port P10
D-A converter
(8 bits X 2 channels)
ROM
(Note 1)
5
DMAC
Program counter
Memory
Port P9
(15 bits)
R0H
R0L
R0H
R0L
R1H
R1L
R1H
R1L
R2
R2
R3
R3
A0
A0
A1
A1
FB
FB
4
UART2/clock synchronous SI/O
Port P6
Port P8
OSD
5
8
XIN–XOUT
M16C/60 series16-bit CPU core
Watchdog timer
Port P5
System clock generator
A-D converter
Timer
Timer TA0 (16 bits)
Timer TA1 (16 bits)
Timer TA2 (16 bits)
Timer TA3 (16 bits)
Timer TA4 (16 bits)
Timer TB0 (16 bits)
Timer TB1 (16 bits)
Timer TB2 (16 bits)
8
Port P7
Internal peripheral functions
8
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
1.5 Performance Outline
Table 1.5.1 is a performance outline.
Table 1.5.1 Performance outline
Item
Number of basic instructions
Shortest instruction execution time
Memory
ROM
size
RAM
OSD ROM
OSD RAM
I/O port
P0 to P10
Multifunction
TA0, TA1, TA2, TA3, TA4
timer
TB0, TB1, TB2
Serial I/O
91 instructions
62.5 ns(f(XIN)=16 MHz)
Refer to Figure 1.5.1 ROM development
10K bytes to 16K bytes
60K bytes
2.2K bytes
8 bits ✕ 7, 6 bits ✕ 1, 5 bits ✕ 2, 4 bits ✕ 1
16 bits ✕ 5
16 bits ✕ 3
1 unit: UART or clock synchronous
1 unit: UART or clock synchronous
1 unit (2 channels)
1 unit (1 channel)
A-D converter
8 bits ✕ 6 channels
D-A converter
8 bits ✕ 2 channels
DMAC
2 channels (trigger: 23 sources)
OSD function
Triple layer, 890 kinds of fonts, 42 characters ✕ 16 lines
Data slicer
Data slicer0
16-bit ✕ 2, or data buffer of 16-bit and 20-bit
Data slicer1
16-bit ✕ 2, or data buffer of 16-bit and 20-bit
HSYNC counter
8 bits ✕ 2 channels
Watchdog timer
15 bits ✕ 1 (with prescaler)
Interrupt
22 internal and 3 external sources, 4 software sources, 7 levels
Clock generating circuit
3 built-in clock generation circuits
Power source voltage VCCE(5V system I/O power supply) 4.75 V to 5.25V
VCCI(internal logic power supply)
3.15 V to 3.45V
Power consumption
415mW
I/O
I/O withstand voltage
3.3 V (only P67, P70, P71, P72, P93 and P94 : 5V )
characteristics Output current
5 mA
Memory expansion
Available
Operating ambient temperature
–20 o C to 70 o C
Device configuration
CMOS high performance silicon gate
Package
100-pin plastic molded QFP
Rev.1.00
UART0
UART2
Multi-master I2C-BUS interface 0
Multi-master I2C-BUS interface 1
Performance
May 18, 2004
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M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
Currently supported products are listed below.
ROM size(byte)
512K
M306V7MJ-XXXFP
M306V7MJA-XXXFP
M306V7FJFP
M306V7FJAFP
384K
M306V7MH-XXXFP
M306V7FHFP
256K
M306V7MG-XXXFP
M306V7FGFP
Mask ROM version
Frash memory version
Figure 1.5.1 ROM development
Table 1.5.2 List of supported products
Type No
ROM capacity
M306V7MG-XXXFP
256K bytes
M306V7MH-XXXFP
384K bytes
M306V7MJ-XXXFP
Remarks
10K bytes
Mask ROM version
16K bytes
M306V7FGFP
256K bytes
M306V7FHFP
384K bytes
512K bytes
M306V7FJAFP
Type No.
Package type
512K bytes
M306V7MJA-XXXFP
M306V7FJFP
RAM capacity
M30 6V 7 M G A
100P6S-A
10K bytes
Flash Memory version
16K bytes
- XXX FP
Package type:
FP: Package 100P6S-A
ROM No.
Omitted for Flash Memory version
Specification:
A: RAM expanded version (16K bytes)
ROM capacity:
G: 256K bytes
H: 384K bytes
J : 512K bytes
Memory type:
M: Mask ROM version
F: Flash Memory version
Shows specification, etc
(The value itself has no specific meaning)
M16C/6V Group
M16C Family
Figure 1.5.2 Type No., memory size, and package
Rev.1.00
May 18, 2004
page 6 of 296
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
Table 1.5.3 Pin description (1)
Pin name
Signal name
I/O type
VCCE, V CCI,
VSS
Power supply
input
CNVSS
CNVSS
Input
This pin switches between processor modes. Connect it to the
VSS pin when operating in single-chip or memory expansion mode.
Connect it to the V CCI pin when in microprocessor mode.
RESET
Reset input
Input
A “L” on this input resets the microcomputer.
These pins are provided for the main clock generating circuit.Connect
a ceramic resonator or crystal between the XIN and the XOUT pins. To
use an externally derived clock, input it to the X IN pin and leave the
XOUT pin open.
Function
Supply 4.75V to 5.25V to the VCCE pin. Supply 3.15V to 3.45V to the
VCCI pin. Supply 0V to the VSS pin.
XIN
Clock input
Input
XOUT
Clock output
Output
BYTE
External data
bus width
select input
Input
This pin selects the width of an external data bus. A 16-bit width is
selected when this input is “L”; an 8-bit width is selected when this
input is “H”. This input must be fixed to either “H” or “L.” When
operating in single-chip mode,connect this pin to V SS.
P00 to P07
I/O port P0
Input/output
This is an 8-bit CMOS I/O port. It has an input/output port direction
register that allows the user to set each pin for input or output
individually. When set for input in single-chip mode, the user can specify
in units of four bits via software whether or not they are tied to a pull-up
resistor. In memory expansion and microprocessor modes, the user
cannot specify that.
Input/output
These pins input and output data (D0–D7).
Input/output
This is an 8-bit I/O port equivalent to P0.
Input/output
These pins input and output data (D8–D15).
Input/output
This is an 8-bit I/O port equivalent to P0.
Output
These pins output 8 low-order address bits (A0–A7).
Input/output
This is an 8-bit I/O port equivalent to P0.
Output
These pins output 8 middle-order address bits (A8–A15).
Input/output
This is an 8-bit I/O port equivalent to P0.
Output
Output
These pins output CS0–CS3 signals and A16–A19. CS 0–CS3 are chip
select signals used to specify an access space. A 16–A19 are 4 highorder address bits.
D0 to D7
P10 to P17
I/O port P1
D8 to D15
P20 to P27
I/O port P2
A0 to A7
P30 to P37
I/O port P3
A8 to A15
P40 to P47
I/O port P4
CS0 to CS3,
A16 to A19
P50 to P57
I/O port P5
WRL / WR,
WRH / BHE,
RD,
BCLK,
HLDA,
HOLD,
ALE,
RDY
Rev.1.00
May 18, 2004
Input/output
This is an 8-bit I/O port equivalent to P0. In single-chip mode, P5 7 in
this port outputs a divide-by-8 or divide-by-32 clock of XIN or a clock of
the same frequency as XCIN as selected by software.
Output
Output
Output
Output
Output
Input
Output
Input
Output WRL, WRH (WR and BHE), RD, BCLK, HLDA, and ALE
signals. WRL and WRH, and BHE and WR can be switched using
software control.
■ WRL, WRH, and RD selected
With a 16-bit external data bus, data is written to even addresses
when the WRL signal is “L” and to the odd addresses when the WRH
signal is “L”. Data is read when RD is “L”.
■ WR, BHE, and RD selected
Data is written when WR is “L”. Data is read when RD is “L”. Odd
addresses are accessed when BHE is “L”. Use this mode when using
an 8-bit external data bus.
While the input level at the HOLD pin is “L”, the microcomputer is
placed in the hold state. While in the hold state, HLDA outputs a “L”
level. While the input level of the RDY pin is “L”, the microcomputer is in
the ready state. ALE output is indefinite.
page 7 of 296
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
Table 1.5.4 Pin description (continued) (2)
Pin name
Signal name
I/O type
Function
P60 to P6 3,
P67
I/O port P6
Input/output
This is an 5-bit I/O port equivalent to P0. When set for input in singlechip, microprocessor and memory expansion modes, the user can
specify in units of four bits via software whether or not they are tied to a
pull-up resistor. Pins in this port also function as UART0 and multimaster I2C-BUS interface 0 I/O pins as selected by software.
P70 to P77
I/O port P7
Input/output
P82, P83,
P86, P87
I/O port P8
Input/output
P90 to P94
I/O port P9
Input/output
P102 to P107
I/O port P10
Input/output
Hsync
Synchronous
Input
signal input for
OSD
This is an 8-bit I/O port equivalent to P6 (P70 and P71 are N-channel
open-drain output). Pins in this port also function as timers A2 and A3,
UART2, multi-master I2C-BUS interface 0, or HSYNC counter I/O pins as
selected by software.
P82, P83, P86 and P87 are I/O ports with the same functions as P6.
Using software, P82 and P83 can be made to function as the I/O pins for
the input pins for external interrupts. P86 and P87 can be set using
software to function as the I/O pins for a sub-clock generation circuit,
G0 and B0 output pins of digital RGB output. In this case, connect a
quartz oscillator between P86 (XCOUT pin) and P87 (XCIN pin).
This is an 5-bit I/O port equivalent to P6. Pins in this port also function
as Timer B0 to B2 input pins, D-A converter output pins, or multi-master
2
I C-BUS interface 1 I/O pins, RXD2, and TXD2 pins. P92 can be set
using software to function as the R0 outout pin of digital RGB output.
This is an 6-bit I/O port equivalent to P6. Pins in this port also function
as A-D converter input pins. P10 5 to P107 can be set using software to
function as the B2, G2, and R2 outout pins of digital RGB output.
This is horizontal synchronous signal pin for OSD.
Vsync
Synchronous
Input
signal input for
OSD
This is vertical synchronous signal pin for OSD.
R, G, B
OSD output
Output
These are OSD output pins (Digital/analog outputs selectable).
OUT1, OUT2
OSD output
Output
These are OSD output pins (digital output).
OSC1/
OSCHLF
Clock for
OSD
Input
OSD clock input or filter pin.
OSC2
Clock for OSD Output
CVIN1
I/O for data
slicer
CVIN2
VHOLD1/
VHOLD2
HLF1/HLF2
TVSETB
Rev.1.00
Test input
May 18, 2004
This is an OSD clock output pin.
Input
Input composite video signal through a capacitor.
Input
Connect a capacitor between VHOLD and Vss.
Input/output
Connect a filter using of a capacitor and a resistor
between HLF and Vss.
Input
This is a test input pin. Fix it to “L.”
page 8 of 296
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
2. OPERATION OF FUNCTIONAL BLOCKS
This microcomputer accommodates certain units in a single chip. These units include ROM and RAM to
store instructions and data and the central processing unit (CPU) to execute arithmetic/logic operations.
Also included are peripheral units such as timers, serial I/O, D-A converter, DMAC, OSD circuit, data slicer,
A-D converter, and I/O ports.
The following explains each unit.
2.1 Memory
Figure 2.1.1 is a memory map. The address space extends the 1M bytes from address 0000016 to
FFFFF16. From FFFFF16 down is ROM. For example, when M306V7MG-XXXFP is used, there is 256K
bytes of internal ROM from C000016 to FFFFF16. The vector table for fixed interrupts such as the reset
mapped to FFFDC16 to FFFFF16. The starting address of the interrupt routine is stored here. The address
of the vector table for timer interrupts, etc., can be set as desired using the internal register (INTB). See the
section on interrupts for details.
10K bytes of internal RAM is mapped to the space from 02C0016 to 053FF16. In addition to storing data, the
RAM also stores the stack used when calling subroutines and when interrupts are generated.
The SFR area is mapped to 0000016 to 003FF16. This area accommodates the control registers for peripheral devices such as I/O ports, A-D converter, serial I/O, and timers, etc. Figures 2.1.2 to 2.1.5 are location
of peripheral unit control registers. Any part of the SFR area that is not occupied is reserved and cannot be
used for other purposes.
The special page vector table is mapped to FFE0016 to FFFDB16. If the starting addresses of subroutines
or the destination addresses of jumps are stored here, subroutine call instructions and jump instructions
can be used as 2-byte instructions, reducing the number of program steps.
In memory expansion mode and microprocessor mode, a part of the spaces are reserved and cannot be
used. The following spaces cannot be used. For example, area shown below cannot be used in M306V7
MG-XXXFP.
• The space between 0140016 and 02BFF16 (in memory expansion and microprocessor modes)
• The space between 0540016 and 07FFF16 (in memory expansion and microprocessor modes)
• The space between 6000016 and BFFFF16 (in memory expansion mode)
Rev.1.00
May 18, 2004
page 9 of 296
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
0000016
SFR area
0040016
OSD RAM area
0140016
Internal reserved
area (See note 1)
02C0016
Internal RAM area
FFE0016
0540016
Internal reserved
area (See note 1)
YYYYY16
Special page
vector table
External area
4000016
OSD ROM area
(See note 2)
FFFDC16
Undefined instruction
6000016
Internal reserved
area (See note 3)
XXXXX16
Internal ROM area
FFFFF16
FFFFF16
Overflow
BRK instruction
Address match
Single step
Watchdog timer
DBC
Reset
Notes 1:During memory expansion and microprocessor modes, cannot be used.
2:Read-out from CPU is possible only for the time of the CPU rewriting mode of Flash memory version.
3:During memory expansion mode, cannot be used.
ROM size
address XXXXX16
RAM size
address YYYYY16
256K bytes
address C000016
10K bytes
address 0540016
384K bytes
address A000016
16K bytes
address 06C0016
512K bytes
address 8000016
Figure 2.1.1 Memory map
Rev.1.00
May 18, 2004
page 10 of 296
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
000016
004016
000116
004116
000216
004216
004316
000316
000416
000516
000616
000716
000816
Processor mode register 0 (PM0)
Processor mode register 1 (PM1)
System clock control register 0 (CM0)
System clock control register 1 (CM1)
Chip select control register (CSR)
Address match interrupt enable register (AIER)
Protect register (PRCR)
004416
OSD1 interrupt control register (OSD1IC)
004516
Data slicer 1 interrupt control register (DS1IC)
004616
Interrupt control reserved register 1 (RE1IC)
Interrupt control reserved register 2 (RE2IC)
OSD2 interrupt control register (OSD2IC)
004716
004816
004916
Multi-master I2C-BUS interface 1 interrupt control register (IIC1IC)
004A16
Bus collision detection interrupt control register (BCNIC)
000B16
004B16
000C16
004C16
DMA0 interrupt control register (DM0IC)
DMA1 interrupt control register (DM1IC)
000916
000A16
000D16
000E16
000F16
Watchdog timer start register (WDTS)
Watchdog timer control register (WDC)
Multi-master I2C-BUS interface 0 interrupt control register (IIC0IC)
004E16
A-D conversion interrupt control register (ADIC)
004F16
UART2 transmit interrupt control register (S2TIC)
UART2 receive interrupt control register (S2RIC)
UART0 transmit interrupt control register (S0TIC)
UART0 receive interrupt control register (S0RIC)
Data slicer 0 interrupt control register (DS0IC)
VSYNC interrupt control register (VSYNCIC)
005016
001016
001116
004D16
Address match interrupt register 0 (RMAD0)
005116
001216
005216
001316
005316
005416
001416
001516
Address match interrupt register 1 (RMAD1)
005516
001616
005616
001716
005716
001816
005816
001916
005916
001A16
005A16
001B16
005B16
001C16
005C16
001D16
005D16
001E16
005E16
001F16
005F16
006016
002016
002116
Timer A0 interrupt control register (TA0IC)
Timer A1 interrupt control register (TA1IC)
Timer A2 interrupt control register (TA2IC)
Timer A3 interrupt control register (TA3IC)
Timer A4 interrupt control register (TA4IC)
Timer B0 interrupt control register (TB0IC)
Timer B1 interrupt control register (TB1IC)
Timer B2 interrupt control register (TB2IC)
INT0 interrupt control register (INT0IC)
INT1 interrupt control register (INT1IC)
Interrupt control reserved register 3 (RE3IC)
DMA0 source pointer (SAR0)
002216
002316
002416
002516
DMA0 destination pointer (DAR0)
002616
002716
002816
002916
DMA0 transfer counter (TCR0)
002A16
002B16
002C16
DMA0 control register (DM0CON)
002D16
002E16
002F16
003016
003116
DMA1 source pointer (SAR1)
003216
003316
003416
003516
DMA1 destination pointer (DAR1)
003616
003716
003816
003916
DMA1 transfer counter (TCR1)
003A16
003B16
003C16
DMA1 control register (DM1CON)
003D16
003E16
01FF16
003F16
Figure 2.1.2 Location of peripheral unit control registers (1)
Rev.1.00
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M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
020016
020116
020216
020316
020416
020516
020616
020716
020816
020916
020A16
020B16
020C16
020D16
020E16
020F16
021016
0211 16
021216
021316
021416
021516
021616
021716
021816
021916
021A16
021B16
021C16
021D16
021E16
021F16
022016
022116
022216
022316
022416
022516
022616
022716
022816
022916
022A16
022B16
022C16
022D16
022E16
022F16
023016
023116
023216
023316
023416
023516
023616
023716
023816
023916
023A16
023B16
023C16
023D16
023E16
023F16
SPRITE OSD control register (SC)
OSD control register 1 (OC1)
OSD control register 2 (OC2)
Horizontal position register (HP)
Clock control register 1 (CS)
I/O polarity control register (PC)
OSD control register 3 (OC3)
Raster color register (RSC)
OSD reserved register 5 (OR5)
Clock control register 2 (CG)
Top border control register (TBR)
Bottom border control register (BBR)
Block control register 1 (BC1)
Block control register 2 (BC2)
Block control register 3 (BC3)
Block control register 4 (BC4)
Block control register 5 (BC5)
Block control register 6 (BC6)
Block control register 7 (BC7)
Block control register 8 (BC8)
Block control register 9 (BC9)
Block control register 10 (BC10)
Block control register 11(BC11)
Block control register 12 (BC12)
Block control register 13 (BC13)
Block control register 14 (BC14)
Block control register 15 (BC15)
Block control register 16 (BC16)
Vertical position register 1 (VP1)
Vertical position register 2 (VP2)
024016
024116
Color palette register 1 (CR1)
024216
024316
Color palette register 2 (CR2)
024416
024516
Color palette register 3 (CR3)
024616
024716
Color palette register 4 (CR4)
024816
024916
Color palette register 5 (CR5)
024A16
024B16
Color palette register 6 (CR6)
024C16
024D16
Color palette register 7 (CR7)
024E16
024F16
025016
025116
Color palette register 9 (CR9)
Color palette register 10 (CR10)
025216
025316
Color palette register 11 (CR11)
025416
025516
Color palette register 12 (CR12)
025616
025716
Color palette register 13 (CR13)
025816
025916
Color palette register 14 (CR14)
025A16
025B16
Color palette register 15 (CR15)
025C16
025D16
OSD reserved register 1 (OR1)
025E16
025F16
026016
026116
026216
026316
026416
026516
OSD control register 4 (OC4)
Data slicer 0 control register 1 (DSC01)
Data slicer 0 control register 2 (DSC02)
Caption data register 01 (CD01)
Caption data register 02 (CD02)
Vertical position register 7 (VP7)
026F16
Caption position register 0 (CPS0)
Slice standard voltage selection register 0 (SBV0)
Data slicer 0 reserved register 1 (DR01)
Clock run-in detect register 0 (CRD0)
Data clock position register 0 (DPS0)
ID1 control register 0 (IDC0)
Standard clock detection register 0 (BCD0)
CRCC data register 0 (CRC0)
Test reserved register 0 (IDT0)
Reserved register (RSV0)
Vertical position register 8 (VP8)
027016
027116
Left border control register (LBR)
Vertical position register 3 (VP3)
026616
026716
026816
Vertical position register 4 (VP4)
026916
Vertical position register 5 (VP5)
026B16
Vertical position register 6 (VP6)
026D16
026A16
026C16
026E16
027216
Vertical position register 9 (VP9)
027316
027416
Vertical position register 10 (VP10)
027516
Right border control register (RBR)
SPRITE vertical position register 1 (VS1)
027616
Vertical position register 11 (VP11)
027716
027816
Vertical position register 12 (VP12)
027916
027A16
Vertical position register 13 (VP13)
027B16
027C16
Vertical position register 14 (VP14)
027D16
027E16
Vertical position register 15 (VP15)
027F16
028016
Vertical position register 16 (VP16)
028116
028216
029E
029F
SPRITE vertical position register 2 (VS2)
SPRITE horizontal position register (HS)
OSD reserved register 4 (OR4)
OSD reserved register 3 (OR3)
OSD reserved register 2 (OR2)
Peripheral mode register (PM)
HSYNC counter register (HC)
HSYNC counter latch
Internal oscillation controlregister 1 (DIV0)
Internal oscillation controlregister 2 (DIV1)
Internal oscillation controlregister 3 (VCO)
R0T reserved register (R0TRSV1)
R0T reserved register (R0TRSV2)
02DF16
Figure 2.1.3 Location of peripheral unit control registers (2)
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M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
02E016
02E116
02E216
02E316
02E416
02E516
02E616
I2C0 data shift register (IIC0S0)
I2C0 address register (IIC0S0D)
I2C0 status register (IIC0S1)
I2C0 control register (IIC0S1D)
I2C0 clock control register (IIC0S2)
I2C0 port selection register (IIC0S2D)
I2C0 transmit buffer register (IIC0S0S)
02E916
02EA16
02EB16
02EC16
02ED16
02EE16
030016
030116
030216
030316
030416
030516
030616
030716
030816
030916
030A16
030B16
030C16
030D16
030E16
030F16
I2C1 data shift register (IIC1S0)
I2C1 address register (IIC1S0D)
I2C1 status register (IIC1S1)
I2C1 control register (IIC1S1D)
I2C1 clock control register (IIC1S2)
I2C1 port selection register (IIC1S2D)
I2C1 transmit buffer register (IIC1S0S)
Data slicer 1 control register 1 (DSC11)
Data slicer 1 control register 2 (DSC12)
Caption data register 11 (CD11)
Caption data register 12 (CD12)
Caption position register 1 (CPS1)
Slice standard voltage selection register 1 (SBV1)
Data slicer 1 reserved register 1 (DR11)
Clock run-in detection register 1 (CRD1)
Data clock position register 1 (DPS1)
ID1 control register 1 (IDC1)
Standard clock detection register 1 (BCD1)
CRCC data register (CRC1)
Test reserved register 1 (IDT1)
Reserved register (RSV1)
031016
031116
031216
031316
FM control 3 reserved register (FMRU3)
FM control 2 reserved register (FMRU2)
Flash USER control register (FMRU)
031416
031516
031616
031716
031816
031916
031C16
038116
038216
038316
038416
038616
038816
038916
038A16
038B16
038C16
038D16
038E16
038F16
039016
039116
039216
039316
039416
039516
039616
039716
039816
039916
039A16
039B16
039C16
039D16
031D16
Timer A0 register (TA0)
Timer A1 register (TA1)
Timer A2 register (TA2)
Timer A3 register (TA3)
Timer A4 register (TA4)
Timer B0 register (TB0)
Timer B1 register (TB1)
Timer B2 register (TB2)
Timer A0 mode register (TA0MR)
Timer A1 mode register (TA1MR)
Timer A2 mode register (TA2MR)
Timer A3 mode register (TA3MR)
Timer A4 mode register (TA4MR)
Timer B0 mode register (TB0MR)
Timer B1 mode register (TB1MR)
Timer B2 mode register (TB2MR)
039E16
039F16
03A016
03A116
03A216
03A316
FO control 3 reserved register (FMRD3)
FO control 2 reserved register (FMRD2)
Flash OSD control register (FMRD)
Flash memory change register (FMSEL)
ID1 reserved register 0 (IRSV0)
ID1 reserved register 1 (IRSV1)
Count start flag (TABSR)
Clock prescaler reset flag (CPSRF)
One-shot start flag (ONSF)
Trigger select register (TRGSR)
Up-down flag (UDF)
038516
038716
02E716
02E816
038016
03A416
03A516
03A616
03A716
UART0 transmit/receive mode register (U0MR)
UART0 bit rate generator (U0BRG)
UART0 transmit buffer register (U0TB)
UART0 transmit/receive control register 0 (U0C0)
UART0 transmit/receive control register 1 (U0C1)
UART0 receive buffer register (U0RB)
03A816
03A916
03AA16
03AB16
03AC16
035E16
035F16
Interrupt request cause select register (IFSR)
036016
03AD16
03AE16
03AF16
Reserved register (RUS0S4)
Reserved register (RUS0S3)
Reserved register (RUS0S2)
Reserved register (RUS0S1)
03B016
03B116
03B216
03B316
037316
037416
037516
037616
037716
037816
037916
037A16
037B16
037C16
037D16
037E16
037F16
Reserved register (RUS2S4)
Reserved register (RUS2S3)
Reserved register (RUS2S2)
UART2 special mode register (U2SMR)
03B416
UART2 transmit/receive mode register (U2MR)
UART2 bit rate generator (U2BRG)
03B816
03B516
03B616
03B716
03BA16
UART2 transmit buffer register (U2TB)
UART2 transmit/receive control register 0 (U2C0)
UART2 transmit/receive control register 1 (U2C1)
UART2 receive buffer register (U2RB)
DMA0 request cause select register (DM0SL)
03B916
DMA1 request cause select register (DM1SL)
03BB16
03BC16
03BD16
03BE16
03BF16
Note: Flash USER control register (FMRU), Flash OSD control register (FMRD) and Flash memory chage register (FMSEL)
are only for M306V7FGFP.
Figure 2.1.4 Location of peripheral unit control registers (3)
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03C016
03C116
03C216
03C316
03C416
A-D register 0 (AD0)
03C516
03C616
A-D register 1 (AD1)
03C716
03C816
A-D register 2 (AD2)
03C916
03CA16
A-D register 3 (AD3)
03CB16
03CC16
A-D register 4 (AD4)
03CD16
03CE16
A-D register 5 (AD5)
03CF16
03D016
03D116
03D216
03D316
03D416
A-D control register 2 (ADCON2)
03D516
03D616
03D716
03D816
A-D control register 0 (ADCON0)
A-D control register 1 (ADCON1)
D-A register 0 (DA0)
03D916
03DA16
D-A register 1 (DA1)
03DB16
03DC16
D-A control register (DACON)
03DD16
03DE16
03DF16
03E016
03E116
03E216
03E316
03E416
03E516
03E616
03E716
03E816
03E916
03EA16
03EB16
03EC16
03ED16
03EE16
03EF16
03F016
03F116
03F216
03F316
03F416
Port P0 register(P0)
Port P1 register (P1)
Port P0 direction register (PD0)
Port P1 direction register (PD1)
Port P2 register (P2)
Port P3 register (P3)
Port P2 direction register (PD2)
Port P3 direction register (PD3)
Port P4 register (P4)
Port P5 register (P5)
Port P4 direction register (PD4)
Port P5 direction register (PD5)
Port P6 register (P6)
Port P7 register (P7)
Port P6 direction register (PD6)
Port P7 direction register (PD7)
Port P8 register (P8)
Port P9 register (P9)
Port P8 direction register (PD8)
Port P9 direction register (PD9)
Port P10 register (P10)
03F516
03F616
Port P10 direction register (PD10)
03F716
03F816
03F916
03FA16
03FB16
03FC16
03FD16
03FE16
03FF16
Pull-up control register 0 (PUR0)
Pull-up control register 1 (PUR1)
Pull-up control register 2 (PUR2)
Port control register (PCR)
Figure 2.1.5 Location of peripheral unit control registers (4)
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2.2 Central Processing Unit (CPU)
The CPU has a total of 13 registers shown in Figure 2.2.1. Seven of these registers (R0, R1, R2, R3, A0,
A1, and FB) come in two sets; therefore, these have two register banks.
b15
R0(Note)
b8 b7
b15
R1(Note)
b0
L
H
b8 b7
H
b19
b0
L
b0
PC
Program counter
Data
registers
b15
b0
b19
R2(Note)
INTB
b15
Interrupt table
register
L
b15
b0
b0
User stack pointer
USP
R3(Note)
b15
b15
b0
b0
Interrupt stack
pointer
ISP
A0(Note)
b15
b0
Address
registers
b15
b0
Static base
register
SB
A1(Note)
b15
b15
b0
Frame base
registers
FB(Note)
IPL
Note: These registers consist of two register banks.
Figure 2.2.1 Central processing unit register
Rev.1.00
b0
H
May 18, 2004
page 15 of 296
b0
FLG
Flag register
U I
O B S Z D C
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
2.2.1 Data Registers (R0, R0H, R0L, R1, R1H, R1L, R2, and R3)
Data registers (R0, R1, R2, and R3) are configured with 16 bits, and are used primarily for transfer and
arithmetic/logic operations.
Registers R0 and R1 each can be used as separate 8-bit data registers, high-order bits as (R0H/R1H),
and low-order bits as (R0L/R1L). In some instructions, registers R2 and R0, as well as R3 and R1 can
use as 32-bit data registers (R2R0/R3R1).
2.2.2 Address Registers (A0 and A1)
Address registers (A0 and A1) are configured with 16 bits, and have functions equivalent to those of data
registers. These registers can also be used for address register indirect addressing and address register
relative addressing.
In some instructions, registers A1 and A0 can be combined for use as a 32-bit address register (A1A0).
2.2.3 Frame Base Register (FB)
Frame base register (FB) is configured with 16 bits, and is used for FB relative addressing.
2.2.4 Program Counter (PC)
Program counter (PC) is configured with 20 bits, indicating the address of an instruction to be executed.
2.2.5 Interrupt Table Register (INTB)
Interrupt table register (INTB) is configured with 20 bits, indicating the start address of an interrupt vector
table.
2.2.6 Stack Pointer (USP/ISP)
Stack pointer comes in two types: user stack pointer (USP) and interrupt stack pointer (ISP), each configured with 16 bits.
Your desired type of stack pointer (USP or ISP) can be selected by a stack pointer select flag (U flag).
This flag is located at the position of bit 7 in the flag register (FLG).
2.2.7 Static Base Register (SB)
Static base register (SB) is configured with 16 bits, and is used for SB relative addressing.
2.2.8 Flag Register (FLG)
Flag register (FLG) is configured with 11 bits, each bit is used as a flag. Figure 2.2.2 shows the flag
register (FLG). The following explains the function of each flag:
• Bit 0: Carry flag (C flag)
This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit.
• Bit 1: Debug flag (D flag)
This flag enables a single-step interrupt.
When this flag is “1”, a single-step interrupt is generated after instruction execution. This flag is
cleared to “0” when the interrupt is acknowledged.
• Bit 2: Zero flag (Z flag)
This flag is set to “1” when an arithmetic operation resulted in 0; otherwise, cleared to “0”.
• Bit 3: Sign flag (S flag)
This flag is set to “1” when an arithmetic operation resulted in a negative value; otherwise, cleared to “0”.
• Bit 4: Register bank select flag (B flag)
This flag chooses a register bank. Register bank 0 is selected when this flag is “0” ; register bank 1 is
selected when this flag is “1”.
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M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
• Bit 5: Overflow flag (O flag)
This flag is set to “1” when an arithmetic operation resulted in overflow; otherwise, cleared to “0”.
• Bit 6: Interrupt enable flag (I flag)
This flag enables a maskable interrupt.
An interrupt is disabled when this flag is “0”, and is enabled when this flag is “1”. This flag is cleared to
“0” when the interrupt is acknowledged.
• Bit 7: Stack pointer select flag (U flag)
Interrupt stack pointer (ISP) is selected when this flag is “0” ; user stack pointer (USP) is selected
when this flag is “1”.
This flag is cleared to “0” when a hardware interrupt is acknowledged or an INT instruction of software
interrupt Nos. 0 to 31 is executed.
• Bits 8 to 11: Reserved area
• Bits 12 to 14: Processor interrupt priority level (IPL)
Processor interrupt priority level (IPL) is configured with three bits, for specification of up to eight
processor interrupt priority levels from level 0 to level 7.
If a requested interrupt has priority greater than the processor interrupt priority level (IPL), the interrupt
is enabled.
• Bit 15: Reserved area
The C, Z, S, and O flags are changed when instructions are executed. See the software manual for
details.
b15
b0
IPL
U
I O B S Z D C
Flag register (FLG)
Carry flag
Debug flag
Zero flag
Sign flag
Register bank select flag
Overflow flag
Interrupt enable flag
Stack pointer select flag
Reserved area
Processor interrupt priority level
Reserved area
Figure 2.2.2 Flag register (FLG)
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M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
2.3 Reset
There are two kinds of resets; hardware and software. In both cases, operation is the same after the reset.
(See “Software Reset” for details of software resets.) This section explains on hardware resets.
When the supply voltage is in the range where operation is guaranteed, a reset is effected by holding the
reset pin level “L” (0.2VCC max.) for at least 20 cycles. When the reset pin level is then returned to the “H”
level while main clock is stable, the reset status is cancelled and program execution resumes from the
address in the reset vector table.
Figure 2.3.1 shows the example reset circuit. Figure 2.3.2 shows the reset sequence.
5.0V
VCCE
3.3V
VCCI
VCCE
RESET
VCCI
4.0V
2.64V
0V
3.3V
RESET
0.66V
0V
Example when VCCI = 3.3V, VCCE = 5.0V
Figure 2.3.1 Example reset circuit
2.3.1 Software Reset
Writing “1” to bit 3 of the processor mode register 0 (address 000416) applies a (software) reset to the
microcomputer. A software reset has almost the same effect as a hardware reset. The contents of internal
RAM are preserved.
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M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
XIN
More than 20 cycles are needed
Microprocessor
mode BYTE = “H”
RESET
BCLK
24cycles
BCLK
Content of reset vector
FFFFC 16
Address
FFFFD 16
FFFFE16
RD
WR
CS0
Microprocessor
mode BYTE = “L”
Content of reset vector
FFFFC 16
Address
FFFFE 16
RD
WR
CS0
Single chip
mode
FFFFC 16
FFFFE16
Address
Figure 2.3.2 Reset sequence
Rev.1.00
May 18, 2004
Content of reset vector
page 19 of 296
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
____________
2.3.2 Pin Status When RESET Pin Level is “L”
____________
Table 2.3.1 shows the statuses of the other pins while the RESET pin level is “L”. Figures 2.3.3 and 2.3.4
show the internal status of the microcomputer immediately after the reset is cancelled.
____________
Table 2.3.1 Pin status when RESET pin level is “L”
Status
Pin name
CNV SS = VCC
CNV SS = VSS
BYTE = V SS
BYTE = V CC
P0
Input port (floating)
Data input (floating)
Data input (floating)
P1
Input port (floating)
Data input (floating)
Input port (floating)
P2, P3, P4 0 to P4 3
Input port (floating)
Address output (undefined)
Address output (undefined)
P44
Input port (floating)
CS0 output (“H” level is output)
CS0 output (“H” level is output)
P45 to P4 7
Input port (floating)
Input port (floating)
(pull-up resistor is on)
Input port (floating)
(pull-up resistor is on)
P50
Input port (floating)
WR output (“H” level is output)
WR output (“H” level is output)
P51
Input port (floating)
BHE output (undefined)
BHE output (undefined)
P52
Input port (floating)
RD output (“H” level is output)
RD output (“H” level is output)
P53
Input port (floating)
BCLK output
BCLK output
P54
Input port (floating)
HLDA output (The output value
depends on the input to the
HOLD pin)
HLDA output (The output value
depends on the input to the
HOLD pin)
P55
Input port (floating)
HOLD input (floating)
HOLD input (floating)
P56
Input port (floating)
ALE output (“L” level is output)
ALE output (“L” level is output)
P57
Input port (floating)
RDY input (floating)
RDY input (floating)
P60 to P6 3, P67,P7,
P82, P83,P86, P87,
P9, P10 2 to P10 7
Input port (floating)
Input port (floating)
Input port (floating)
R, G, B, OUT1,
OUT2
Output port
CVIN1, VHOLD1,HLF1 Input/output port
CVIN2, VHOLD2,HLF2
OSC1/OSCHLF
Input port
OSC2
Output port
HSYNC , VSYNC
Input port
Rev.1.00
May 18, 2004
page 20 of 296
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
Processor mode register 0 (Note)
(000416)···
0016
Timer B0 interrupt control register
(005A16)···
? 0 0 0
Timer B1 interrupt control register
(005B16)···
? 0 0 0
4816
Timer B2 interrupt control register
(005C16)···
? 0 0 0
Processor mode register 1
(000516)··· 0 0 0 0 0
System clock control register 0
(000616)···
0 0
System clock control register 1
(000716)···
2016
INT0 interrupt control register
(005D16)···
0 0 ? 0 0 0
Chip select control register
(000816)···
0116
INT1 interrupt control register
(005E16)···
0 0 ? 0 0 0
Address match interrupt
enable register
(000916)···
0 0
SPRITE OSD control register
(020116)···
0 0 0 0 0
Protect register
(000A16)···
0 0 0
OSD control register 1
(020216)···
0016
Watchdog timer control register
(000F16)··· 0 0 0 ? ? ? ? ?
OSD control register 2
(020316)···
0016
(001016)···
0016
Horizontal position register
(020416)···
0016
(0011 16)···
0016
Clock control register
(020516)···
0016
Address match interrupt register 0
(001216)···
Address match interrupt register 1
0 0 0 0
I/O polarity control register
(020616)···
8016
(001416)···
0016
OSD control register 3
(020716)···
0016
(001516)···
0016
Raster color register
(020816)···
0016
(001616)···
0 0 0 0
(020916)···
0016
DMA0 control register
(002C16)··· 0 0 0 0 0 ? 0 0
OSD reserved register 5
(020A16)···
0016
DMA1 control register
(003C16)··· 0 0 0 0 0 ? 0 0
OSD reserved register 6
(020B16)···
0016
OSD1 interrupt control register
OSD reserved register 1
(025D16)···
0016
(004416)···
? 0 0 0
Data slicer 1 interrupt control register (004516)···
? 0 0 0
OSD2 interrupt control register
(004816)···
? 0 0 0
Multi-master I2C-BUS interface 1
interrupt control register
Bus collision detection interrupt
control register
DMA0 interrupt control register
(004916)···
0 0 ? 0 0 0
(004A16)···
? 0 0 0
Caption position register 0
(026616)··· 0 0 ? 0 0 0 0 0
(004B16)···
? 0 0 0
(026716)···
0016
(026816)···
0016
DMA1 interrupt control register
Multi-master I2C-BUS interface 0
interrupt control register
A-D conversion interrupt
control register
UART2 transmit interrupt
control register
UART2 receive interrupt
control register
UART0 transmit interrupt
control register
UART0 receive interrupt
control register
OSD control register 4
(025F16)···
Data slicer 0 control register 1
(026016)···
Data slicer 0 control register 2
(026116)··· ? 0 ? 0 ? ? 0 ?
0 0
0016
(004C16)···
? 0 0 0
Slice standard voltade selection
register
Data slicer 0 reserved register 1
(004D16)···
? 0 0 0
Clock run-in detect register 0
(026916)··· 0 0 0 0 0 ? ? ?
(004E16)···
? 0 0 0
Data clock position register 0
(026A16)···
(004F16)···
? 0 0 0
ID1 control register 0
(026B16)···
(005016)···
? 0 0 0
Standard clock detection
register 0
(026C16)··· ? ? ? ? ? ? ? ?
(005116)···
? 0 0 0
CRCC data register 0
(026D16)··· 0 0 ? ? ? ? ? ?
(005216)···
? 0 0 0
Test reserved register 0
(026E16)···
Reserved register
(026F16)···
Left border control register
(027016)···
Data slicer 0 interrupt control register (005316)···
? 0 0 0
VSYNC interrupt control register
(005416)···
? 0 0 0
Timer A0 interrupt control register
(005516)···
? 0 0 0
Timer A1 interrupt control register
(005616)···
? 0 0 0
Timer A2 interrupt control register
(005716)···
? 0 0 0
? ? 0 0 0 0 1
0016
0016
0
0116
0 0 0
(027116)···
Timer A3 interrupt control register
(005816)···
? 0 0 0
Timer A4 interrupt control register
(005916)···
? 0 0 0
Right border control register
(027216)···
(027316)···
0 0 0
OSD reserved register 4
(027A16)···
0 0 0 0 0 0 0
OSD reserved register 3
(027B16)···
0016
OSD reserved register 2
(027C16)···
0016
Peripheral mode register
(027D16)··· 0
0 0 0 0 0
HSYNC counter register
(027E16)···
0 0
X : Nothing is mapped to this bit
? : Undefined
The content of other registers and RAM is undefined when the microcomputer is reset. The initial values
must therefore be set.
Note: When the VCC level is applied to the CNVSS pin, it is 0316 at a reset.
Figure 2.3.3 Device’s internal status after a reset is cleared (1)
Rev.1.00
May 18, 2004
page 21 of 296
0016
0 0
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
Internal oscillation control register 1
(02E116)···
0016
Timer A0 mode register
(039616)···
0016
Internal oscillation control register 2
(02E116)···
0016
Timer A1 mode register
(039716)···
0016
Internal oscillation control register 3
(02E116)···
0016
Timer A2 mode register
(039816)···
0016
ROT reserved register 1
(029E16)··· ? ? ? ? ? ? ? 0
Timer A3 mode register
(039916)···
0016
ROT reserved register 2
(029F16)···
0
Timer A4 mode register
(039A16)···
0016
I2C0 address register
(02E116)···
0016
Timer B0 mode register
(039B16)··· 0 0 ?
0 0 0 0
I2C0 status register
(02E216)··· 0 0 0 1 0 0 0 ?
Timer B1 mode register
(039C16)··· 0 0 ?
0 0 0 0
I2C0 control register
(02E316)···
0016
Timer B2 mode register
(039D16)··· 0 0 ?
I2C0
(02E416)···
0016
UART0 transmit/receive mode register
(03A016)···
0016
UART0 transmit/receive control register 0
(03A416)···
0816
clock control register
0
0 0 0 0
I2C0 port selection register
(02E516)··· 0 0 ? 0 0 0 0 0
I2C1 address register
(02E916)···
UART0 transmit/receive control register 1
(03A516)···
0216
I2C1 status register
(02EA16)··· 0 0 0 1 0 0 0 ?
Reserved register
(03AC16)···
0016
I2C1 control register
(02EB16)···
0016
Reserved register
(03AD16)···
0016
I2C1 clock control register
(02EC16)···
0016
Reserved register
(03AE16)···
0016
I2C1 port selection register
(02ED16)··· 0 0 ? 0 0 0 0 0
Reserved register
(03AF16)···
0016
Data slicer 1 control register 1
(030016)···
Data slicer 1 control register 2
(030116)··· ? 0 ? 0 ? ? 0 ?
Caption position register 1
(030616)··· 0 0 ? 0 0 0 0 0
0016
0016
Slice standard voltage selection register
(030716)···
0016
Data slicer 1 reserved register 1
(030816)···
0016
Clock run-in detect register 1
(030916)··· 0 0 0 0 0 ? ? ?
Data clock position register 1
(030A16)···
(030B16)···
(030C16)··· ? ? ? ? ? ? ? ?
(030D16)··· 0 0 ? ? ? ? ? ?
(030E16)···
Reserved register
(030F16)···
FM Control 3 reserved register
(0311 16)···
0016
0
0
? ?
(031216)···
FM Control 2 reserved register
(031316)···
Flash USER control register
? 0
0
? ?
(031616)···
FO Control 2 reserved register
0
? 0 0 0 0 0 1
(031516)···
FO Control 3 reserved register
0
? 0
Flash OSD control register
(031716)···
? 0 0 0 0 0 1
Flash memory change register
(031816)···
0 0 0 0 0 0 0
(031C16)···
ID1 Reserved register 0
(031D16)···
ID1 Reserved register 1
0016
0016
A-D control register 2
(03D416)··· 0 0 0 0 ? ? ? 0
A-D control register 0
(03D616)··· 0 0 0 0 0 ? ? ?
A-D control register 1
(03D716)···
D-A control register
(03DC16)···
0016
Port P0 direction register
(03E216)···
0016
Port P1 direction register
(03E316)···
0016
Port P2 direction register
(03E616)···
0016
Port P3 direction register
(03E716)···
0016
Port P4 direction register
(03EA16)···
0016
Port P5 direction register
(03EB16)···
0016
Port P6 direction register
(03EE16)···
0016
Port P7 direction register
(03EF16)···
0016
Port P8 direction register
(03F216)··· 0 0
0 0 0 0 0
Port P9 direction register
(03F316)···
0016
Port P10 direction register
(03F616)···
0016
Pull-up control register 0
(03FC16)···
0016
Pull-up control register 1(Note)
(03FD16)···
0016
Pull-up control register 2
(03FE16)···
0016
Port control register
(03FF16)···
0016
0016
ID1 control register 1
Test reserved register 1
(03B816)···
(03BA16)···
? ? 0 0 0 0 1
Standard clock detection register 1
CRCC data register 1
DMA0 request cause select register
DMA1 request cause select register
0016
0016
0016
Interrupt request cause select register
(035F16)···
0016
Reserved register
(037416)···
0016
Data registers (R0/R1/R2/R3)
000016
Reserved register
(037516)···
0016
Address registers (A0/A1)
000016
Reserved register
(037616)···
0016
Frame base register (FB)
000016
0000016
UART2 special mode register
(037716)···
0016
Interrupt table register (INTB)
UART2 transmit/receive mode register
(037816)···
0016
User stack pointer (USP)
000016
UART2 transmit/receive control register 0
(037C16)···
0816
Interrupt stack pointer (ISP)
000016
UART2 transmit/receive control register 1
(037D16)···
0216
Static base register (SB)
000016
Count start flag
(038016)···
0016
Flag register (FLG)
000016
Clock prescaler reset flag
(038116)··· 0
One-shot start flag
(038216)··· 0 0
0 0 0 0 0
Trigger select register
(038316)···
0016
Up-down flag
(038416)···
0016
x : Nothing is mapped to this bit
? : Undefined
The content of other registers and RAM is undefined when the microcomputer is reset. The initial values
must therefore be set.
Notes1: When the VCC level is applied to the CNVSS pin, it is 0216 at a reset.
2: Flash USER control register (FMRU), Flash OSD control register (FMRD) and Flash memory
chage register (FMSEL) are only for Flash version.
Figure 2.3.4 Device’s internal status after a reset is cleared (2)
Rev.1.00
May 18, 2004
page 22 of 296
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
2.4 Processor Mode
2.4.1 Types of Processor Mode
One of three processor modes can be selected: single-chip mode, memory expansion mode, and microprocessor mode. The functions of some pins, the memory map, and the access space differ according to
the selected processor mode.
(1) Single-chip mode
In single-chip mode, only internal memory space (SFR, OSD RAM, internal RAM, and internal ROM)
can be accessed. Ports P0 to P10 can be used as programmable I/O ports or as I/O ports for the
internal peripheral functions.
(2) Memory expansion mode
In memory expansion mode, external memory can be accessed in addition to the internal memory
space (SFR, OSD RAM, internal RAM, and internal ROM).
In this mode, some of the pins function as the address bus, the data bus, and as control signals. The
number of pins assigned to these functions depends on the bus and register settings. (See “2.4.3 Bus
Settings” for details.)
(3) Microprocessor mode
In microprocessor mode, the SFR, OSD RAM, internal RAM, and external memory space can be
accessed. The internal ROM area cannot be accessed.
In this mode, some of the pins function as the address bus, the data bus, and as control signals. The
number of pins assigned to these functions depends on the bus and register settings. (See “2.4.3 Bus
Settings” for details.)
2.4.2 Setting Processor Modes
The processor mode is set using the CNVSS pin and the processor mode bits (bits 1 and 0 at address
000416). Do not set the processor mode bits to “102”.
Regardless of the level of the CNVSS pin, changing the processor mode bits selects the mode. Therefore,
never change the processor mode bits when changing the contents of other bits. Also do not attempt to
shift to or from the microprocessor mode within the program stored in the internal ROM area.
(1) Applying VSS to CNVSS pin
The microcomputer begins operation in single-chip mode after being reset. Memory expansion mode
is selected by writing “012” to the processor mode is selected bits.
(2) Applying VCC to CNVSS pin
The microcomputer starts to operate in microprocessor mode after being reset.
Figures 2.4.1 and 2.4.2 show the processor mode register 0 and 1.
Figure 2.4.3 shows the memory maps applicable for each of the modes.
Rev.1.00
May 18, 2004
page 23 of 296
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
Processor mode register 0 (Note 1)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
PM0
Address
000416
When reset
0016 (Note 2)
0 0
Bit symbol
Bit name
Function
Processor mode bit
b1 b0
PM02
R/W mode select bit
0 : RD,BHE,WR
1 : RD,WRH,WRL
PM03
Software reset bit
PM00
PM01
R W
0 0: Single-chip mode
0 1: Memory expansion mode
1 0: Inhibited
1 1: Microprocessor mode
The device is reset when this bit is set
to “1”. The value of this bit is “0” when
read.
PM04
PM05
Reserved bit
Must always be set to “0”
PM06
Port P40 to P43 function
select bit (Note 3)
0 : Address output
1 : Port function
(Address is not output)
PM07
BCLK output disable bit
0 : BCLK is output
1 : BCLK is not output
(Pin is left floating)
Notes 1: Set bit 1 of the protect register (address 000A16) to “1” when writing new
values to this register.
2: If the VCC voltage is applied to the CNVSS, the value of this register when
reset is 0316. (PM00 and PM01 both are set to “1”.)
3: Valid in microprocessor and memory expansion modes.
Figure 2.4.1 Processor mode register 0
Rev.1.00
May 18, 2004
page 24 of 296
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
Processor mode register 1 (Note 1)
b7
b6
b5
b4
0 0 0 0
b3
0
b2
b1
Symbol
PM1
b0
0 0
Bit symbol
Address
000516
Bit name
When reset
00000X002
Function
Reserved bit
Must always be set to “0”
Reserved bit (Note 2)
Must always be set to “0”
R W
Nothing is assigned.
In an attempt to write to this bit, write “0.” The value, if read, turns out to be
indeterminate.
Reserved bits
Must always be set to “0”
Reserved bit
Must always be set to “0”
Notes 1: Set bit 1 of the protect register (address 000A16) to “1” when writing new
values to this register.
2: As this bit becomes “0” at reset, must always be set to “1” after reset
release.
Figure 2.4.2 Processor mode register 1
Rev.1.00
May 18, 2004
page 25 of 296
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
Single-chip mode
Memory expansion mode
Microprocessor mode
SFR area
SFR area
SFR area
OSD RAM
OSD RAM
OSD RAM
Internal
reserved area
Internal
reserved area
Internal
reserved area
Internal
RAM area
Internal RAM
area
Internal RAM
area
Internal
reserved area
Internal
reserved area
Internal
reserved area
Not used
External area
External area
0000016
0040016
0140016
02C0016
0540016
YYYYY16
4000016
OSD ROM
(Note1)
OSD ROM
(Note1)
OSD ROM
(Note1)
6000016
Internal
reserved area
Internal
reserved area
External area
XXXXX16
Internal
ROM area
Internal
ROM area
FFFFF16
External area : Accessing this area allows you to
access a device connected external
to the microcomputer.
Note1 : Read-out from CPU is possible only for the time of CPU rewriting mode of Flash version.
ROM size
address XXXXX16
RAM size
address YYYYY16
256K bytes
address C000016
10K bytes
address 0540016
384K bytes
address A000016
16K bytes
address 06C0016
512K bytes
address 8000016
Figure 2.4.3 Memory maps in each processor mode
Rev.1.00
May 18, 2004
page 26 of 296
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
2.4.3 Bus Settings
The BYTE pin and bits 4 to 6 of the processor mode register 0 (address 000416) are used to change the
bus settings.
Table 2.4.1 shows the factors used to change the bus settings.
Table 2.4.1 Factors for switching bus settings
Bus setting
Switching external address bus width
Switching external data bus width
Switching factor
Bit 6 of processor mode register 0
BYTE pin
(1) Selecting external address bus width
The address bus width for external output in the 1M bytes of address space can be set to 16 bits (64K
bytes address space) or 20 bits (1M bytes address space). When bit 6 of the processor mode register
0 is set to “1”, the external address bus width is set to 16 bits, and P2 and P3 become part of the
address bus. P40 to P43 can be used as programmable I/O ports. When bit 6 of processor mode
register 0 is set to “0”, the external address bus width is set to 20 bits, and P2, P3, and P40 to P43
become part of the address bus.
(2) Selecting external data bus width
The external data bus width can be set to 8 or 16 bits. When the BYTE pin is “L”, the bus width is set
to 16 bits; when “H”, it is set to 8 bits. (The internal bus width is permanently set to 16 bits.)
While operating, fix the BYTE pin either to “H” or to “L.”
(3) Bus format
The bus format is separate bus .
• Separate bus
In this mode, the data and address are input and output separately. The data bus can be set using the
BYTE pin to be 8 or 16 bits. When the BYTE pin is “H”, the data bus is set to 8 bits and P0 functions as
the data bus and P1 as a programmable I/O port. When the BYTE pin is “L”, the data bus is set to 16
bits and P0 and P1 are both used for the data bus.
Rev.1.00
May 18, 2004
page 27 of 296
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
Table 2.4.2 Pin functions for each processor mode
Single-chip
mode
Processor mode
Data bus width
BYTE pin level
Memory expansion mode/microprocessor modes
8 bits
= “H”
16 bits
= “L”
P00 to P07
I/O port
Data bus
Data bus
P10 to P17
I/O port
I/O port
Data bus
P 20
I/O port
Address bus
Address bus
P21 to P27
I/O port
Address bus
Address bus
P 30
I/O port
Address bus
Address bus
P31 to P37
I/O port
Address bus
Address bus
P40 to P43
Port P40 to P43
function select bit = 1
I/O port
I/O port
I/O port
P40 to P43
Port P40 to P43
function select bit = 0
I/O port
Address bus
Address bus
P44 to P47
I/O port
P50 to P53
I/O port
P54
I/O port
HLDA
HLDA
P 55
I/O port
HOLD
HOLD
P 56
I/O port
ALE
ALE
P 57
I/O port
RDY
RDY
Rev.1.00
May 18, 2004
page 28 of 296
CS (chip select) or programmable I/O port
(For details, refer to “2.4.4 Bus control”)
Outputs RD, WRL, WRH, and BCLK or RD, BHE, WR, and BCLK
(For details, refer to “2.4.4 Bus control”)
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
2.4.4 Bus Control
The following explains the signals required for accessing external devices. The signals required for accessing the external devices are valid when the processor mode is set to memory expansion mode and
microprocessor mode.
(1) Address bus/data bus
The address bus consists of the 20 pins A0 to A19 for accessing the 1M bytes of address space.
The data bus consists of the pins for data I/O. When the BYTE pin is “H”, the 8 ports D0 to D7 function
as the data bus. When BYTE is “L”, the 16 ports D0 to D15 function as the data bus.
When a change is made from single-chip mode to memory expansion mode, the value of the address
bus is undefined until external memory is accessed.
(2) Chip select signal
The chip select signal is output using the same pins as P44 to P47. Bits 0 to 3 of the chip select control
register (address 000816) set each pin to function as a port or to output the chip select signal. The chip
select control register is valid in memory expansion mode and microprocessor mode. In single-chip
mode, P44 to P47 function as programmable I/O ports regardless of the value in the chip select control
register.
_______
In microprocessor mode, only CS0 outputs the chip select signal after the reset state has been can_______
_______
celled. CS1 to CS3 function as input ports. Figure 2.4.4 shows the chip select control register.
The chip select signal can be used to split the external area into as many as four blocks. Table 2.4.3
shows the external memory areas specified using the chip select signal.
Table 2.4.3 External areas specified by the chip select signals
Chip select
Rev.1.00
Memory expansion mode
18000 16 to 3FFFF 16 (160K)
CS0
CS1
CS2
CS3
10000 16 to 17FFF 16 (32K)
0C000 16 to 0FFFF 16 (16K)
08000 16 to 0BFFF 16 (16K)
May 18, 2004
page 29 of 296
Specified address range
Microprocessor mode
1800016 to 3FFFF 16 (160K), 60000 16 to FFFFF 16 (640K)
10000 16 to 17FFF 16 (32K)
0C000 16 to 0FFFF 16 (16K)
08000 16 to 0BFFF 16 (16K)
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
Chip select control register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
CSR
Address
0008 16
Bit name
Bit symbol
CS0
CS0 output enable bit
CS1
CS1 output enable bit
CS2
CS2 output enable bit
CS3
CS3 output enable bit
CS0W
CS0 wait bit
CS1W
CS1 wait bit
CS2W
CS2 wait bit
CS3W
CS3 wait bit
When reset
0116
Function
R W
0 : Chip select output disabled
(Normal port pin)
1 : Chip select output enabled
0 : Wait state inserted
1 : No wait state
Figure 2.4.4 Chip select control register
(3) Read/write signals
With a 16-bit data bus (BYTE pin =“L”), bit 2 of the processor mode register 0 (address 000416) select
_____ ________
______
_____ ________
_________
the combinations of RD, BHE, and WR signals or RD, WRL, and WRH signals. With an 8-bit data bus
_____ ______
_______
(BYTE pin = “H”), use the combination of RD, WR, and BHE signals. (Set bit 2 of the processor mode
register 0 (address 000416) to “0”.) Tables 2.4.4 and 2.4.5 show the operation of these signals.
_____ ______
________
After a reset has been cancelled, the combination of RD, WR, and BHE signals is automatically selected.
_____ _________
_________
When switching to the RD, WRL, and WRH combination, do not write to external memory until bit 2 of
the processor mode register 0 (address 000416) has been set (Note).
Note: Before attempting to change the contents of the processor mode register 0, set bit 1 of the
protect register (address 000A16) to “1”.
_____
________
_________
Table 2.4.4 Operation of RD, WRL, and WRH signals
Data bus width
16-bit
(BYTE = “L”)
RD
L
H
H
H
WRL
H
L
H
L
_____
______
Status of external data bus
WRH
H
H
L
L
Read data
Write 1 byte of data to even address
Write 1 byte of data to odd address
Write data to both even and odd addresses
________
Table 2.4.5 Operation of RD, WR, and BHE signals
Data bus width
16-bit
(BYTE = “L”)
8-bit
(BYTE = “H”)
Rev.1.00
May 18, 2004
RD
H
L
H
L
H
L
H
L
WR
L
H
L
H
L
H
L
H
page 30 of 296
BHE
L
L
H
H
L
L
Not used
Not used
A0
H
H
L
L
L
L
H/L
H/L
Status of external data bus
Write 1 byte of data to odd address
Read 1 byte of data from odd address
Write 1 byte of data to even address
Read 1 byte of data from even address
Write data to both even and odd addresses
Read data from both even and odd addresses
Write 1 byte of data
Read 1 byte of data
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
(4) ALE signal
ALE output is indefinite.
Note: The output is flouting when reading.
Rev.1.00
May 18, 2004
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M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
________
(5) RDY signal
________
RDY signal facilitates access of external devices that require a long time for access. As shown in
________
Figure 2.4.6, if an “L” is being input to the RDY pin at the BCLK falling edge, the bus turns to the wait
________
state. If an “H” is being input to the RDY pin at the BCLK falling edge, the bus cancels the wait state.
Table 2.4.6 shows the microcomputer state in the wait state. Figure 2.4.5 shows the example of the
_____
________
RD signal being extended using the RDY signal.
________
The RDY signal is valid when accessing the external area during the bus cycle in which bits 4 to 7 of
________
the chip select control register (address 000816) are set to “0.” The RDY signal is invalid when setting
________
“1” to all bits 4 to 7 of the chip select control register (address 000816), but the RDY pin should be
treated as properly as in non-using.
Table 2.4.6 Microcomputer status in ready state (Note)
Item
Status
Oscillation
On
___
_____
________
R/W signal, address bus, data bus, CS
Maintain status when RDY signal received
__________
ALE signal, HLDA, programmable I/O ports
Internal peripheral circuits
On
________
Note: The RDY signal cannot be received immediately prior to a software wait.
In an instance of separate bus
BCLK
RD
CSi
(i=0 to 3)
RDY
tsu(RDY - BCLK)
Accept timing of RDY signal
: Wait using RDY signal
: Wait using software
_____
________
Figure 2.4.5 Example of RD signal extended by RDY signal
Rev.1.00
May 18, 2004
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M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
(6) Hold signal
The hold signal is used to transfer the bus privileges from the CPU to the external circuits. Inputting “L”
__________
to the HOLD pin places the microcomputer in the hold state at the end of the current bus access. This
__________
__________
status is maintained and “L” is output from the HLDA pin as long as “L” is input to the HOLD pin. Table
2.4.7 shows the microcomputer status in the hold state.
__________
Bus-using priorities are given to HOLD, DMAC, and CPU in order of decreasing precedence.
__________
HOLD > DMAC > CPU
Figure 2.4.6 Bus-using priorities
Table 2.4.7 Microcomputer status in hold state
Item
Status
Oscillation
ON
___
_____
_______
R/W signal, address bus, data bus, CS, BHE
Programmable I/O ports
P0, P1, P2, P3, P4, P5
P6, P7, P8, P9, P10
Floating
Floating
Maintains status when hold signal is received
__________
HLDA
Internal peripheral circuits
ALE signal
Output “L”
ON (but watchdog timer stops)
Undefined
(7) External bus status when internal area is accessed
Table 2.4.8 shows the external bus status when the internal area is accessed.
Table 2.4.8 External bus status when the internal area is accessed
Item
SFR accessed
Internal ROM/RAM accessed
Address bus
Address output
Maintain status before accessed
address of external area
Data bus
When read
Floating
Floating
When write
Output data
Indefinite
RD, WR, WRL, WRH
RD, WR, WRL, WRH output
Indefinite
BHE
BHE output
Maintain status before accessed
status of external area
CS
Output "H"
Output "H"
ALE
Indefinite
Indefinite
(8) BCLK output
The output of the internal clock φ can be selected using bit 7 of the processor mode register 0 (address
000416) (Note). The output is floating when bit 7 is set to “1”.
Note: Before attempting to change the contents of the processor mode register 0, set bit 1 of the
protect register (address 000A16) to “1”.
Rev.1.00
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M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
(9) Software wait
A software wait can be inserted by setting the bits 4 to 7 of the chip select control register (address
000816).
Software waits can be set independently for each of the 4 areas selected using the chip select signal.
_______
_______
Bits 4 to 7 of the chip select control register correspond to chip selects CS0 to CS3. When one of these
bits is set to “1”, the bus cycle is executed in one BCLK cycle. When set to “0”, the bus cycle is
executed in two BCLK cycles. These bits default to “0” after the microcomputer has been reset. These
bits default to “0” after the microcomputer has been reset.
The SFR area and the OSD RAM area are always accessed in two BCLK cycles regardless of the
setting of these control bits.
Table 2.4.9 shows the software wait and bus cycles. Figure 2.4.7 shows example bus timing when
using software waits.
Note: Before attempting to change the contents of the processor mode register 1, set bit 1 of the
protect register (address 000A16) to “1”.
Table 2.4.9 Software waits and bus cycles
Area
SFR/
OSD RAM
Internal
ROM/RAM
External
memory
area
Rev.1.00
May 18, 2004
Bits 4 to 7 of chip select
control register
Bus cycle
Invalid
2 BCLK cycles
Invalid
1 BCLK cycle
1
1 BCLK cycle
0
2 BCLK cycles
page 34 of 296
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
< Separate bus (no wait) >
Bus cycle
BCLK
Write signal
Read signal
Output
Data bus
Address bus
Address
Input
Address
Chip select
< Separate bus (with wait) >
Bus cycle
BCLK
Write signal
Read signal
Data bus
Address bus
Address
Chip select
Figure 2.4.7 Typical bus timings using software wait
Rev.1.00
May 18, 2004
page 35 of 296
Input
Output
Address
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
2.5 Clock Generating Circuit
The clock generating circuit contains 2 oscillator circuits that supply the operating clock sources to the CPU
and internal peripheral units and 1 oscillator circuit that supplies the operating clock source to OSD.
Table 2.5.1. Clock oscillation circuits
Main clock oscillation circuit
Use of clock
Sub-clock oscillation circuit
• CPU’s operating clock
• CPU’s operating clock
source
• Internal peripheral units’
source
• Timer A/B’s count clock
operating clock source
OSD oscillation circuit
• OSD’s operating clock
source
source
Usable oscillator
•Ceramic resonator
(or quartz-crystal oscillator)
•Quartz-crystal oscillator
•Ceramic resonator
(or quartz-crystal oscillator)
•LC oscillator (Note)
Pins to connect
XIN, XOUT
XIN, XOUT
OSC1, OSC2
oscillator
Oscillation stop/restart
Available
Available
function
Oscillator status
Oscillating
Stopped
immediately after reset
Other
Externally derived clock can be input
Note: The OSD clock can be selected between an external resonator and an internal oscillator circuit. For
details, see a description of the Clock Control Register (address 020516).
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M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
2.5.1 Example of Oscillator Circuit
Figure 2.5.1 shows some examples of the main clock circuit, one using an oscillator connected to the
circuit, and the other one using an externally derived clock for input. Figure 2.5.2 shows some examples
of sub-clock circuits, one using an oscillator connected to the circuit, and the other one using an externally
derived clock for input. Circuit constants in Figures 2.5.1 and 2.5.2 vary with each oscillator used. Use
the values recommended by the manufacturer of your oscillator.
Microcomputer
Microcomputer
(Built-in feedback resistor)
(Built-in feedback resistor)
XIN
XIN
XOUT
XOUT
Open
(Note)
Rd
Externally derived clock
C IN
COUT
Vcc
Vss
Note: Insert a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive
capacity setting. Use the value recommended by the maker of the oscillator.
When the oscillation drive capacity is set to low, check that oscillation is stable. When being specified to connect a
feedback resistor externally by the manufacture, connect a feedback resistor between pins XIN and XOUT.
Figure 2.5.1 Examples of main clock
Microcomputer
Microcomputer
(Built-in feedback resistor)
(Built-in feedback resistor)
XCIN
XCOUT
XCIN
XCOUT
Open
(Note)
RCd
Externally derived clock
CCIN
CCOUT
Vcc
Vss
Note 1. Insert a damping resistor if required. The resistance will vary depending on the oscillator. Use the value
recommended by the maker of the oscillator.
When being specified to connect a feedback resistor externally by the manufacture, connect a feedback resistor
between pins XCIN and XCOUT.
2. Since the waveform and amplitude of sub clock tend to be influenced of substrate capacity etc.
Surely, request the oscillation characteristic investigation by the real board from oscillation maker, and use the
oscillation circuit constant recommended.
Figure 2.5.2 Examples of sub-clock
Rev.1.00
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M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
2.5.2 OSD Oscillation Circuit
The OSD clock oscillation circuit can be chosen to be an external oscillator circuit comprised of an LC
oscillator or a ceramic resonator (or a quartz-crystal oscillator) connected between the OSC1 and OSC2
pins, or an internal oscillator circuit with a filter connected to the OSC1 pin. Which of LC oscillator or a
ceramic resonator (or a quartz-crystal oscillator) is selected by setting bits 0, 1 and 2 of the clock control
register (address 020516).
Microcomputer
OSC1
Microcomputer
OSC2
OSC1
L
C1
OPEN
1KΩ
C2
OSC2
2pF
0.015µF
Note: When mounting a resistor and capacitors,
use the shortest possible wiring to prevent leakage.
Connecting an internal oscillator circuit
Connecting an external oscillator circuit
Figure 2.5.3 OSD clock connection example
2.5.3 Clock Control
Figure 2.5.4 shows the block diagram of the clock generating circuit.
XCIN
XCOUT
fC32
1/32
f1
CM04
f1SIO2
fAD
fC
f8SIO2
f8
Sub clock
f32SIO2
CM10 “1”
Write signal
f32
S Q
XIN
XOUT
b
R
a
c
d
Divider
RESET
CM07=0
BCLK
Software reset
fC
CM07=1
Main clock
CM02
CM05
Interrupt request
level judgment
output
S Q
WAIT instruction
R
c
b
a
1/2
1/2
1/2
1/2
1/2
CM06=0
CM17,CM16=11
CM06=1
CM06=0
CM17,CM16=10
d
CM06=0
CM17,CM16=01
CM06=0
CM17,CM16=00
CM0i : Bit i at address 000616
CM1i : Bit i at address 000716
WDCi : Bit i at address 000F16
Figure 2.5.4 Clock generating circuit
Rev.1.00
May 18, 2004
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Details of divider
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
The following paragraphs describes the clocks generated by the clock generating circuit.
(1) Main clock
The main clock is generated by the main clock oscillation circuit. After a reset, the clock is divided by
8 to the BCLK. The clock can be stopped using the main clock stop bit (bit 5 at address 000616).
Stopping the clock, after switching the operating clock source of CPU to the sub-clock, reduces the
power dissipation.
After the oscillation of the main clock oscillation circuit has stabilized, the drive capacity of the main
clock oscillation circuit can be reduced using the XIN-XOUT drive capacity select bit (bit 5 at address
000716). Reducing the drive capacity of the main clock oscillation circuit reduces the power dissipation. This bit changes to “1” when shifting from high-speed/medium-speed mode to stop mode and at
a reset. When shifting from low-speed/low power dissipation mode to stop mode, the value before
stop mode is retained.
(2) Sub-clock
The sub-clock is generated by the sub clock oscillation circuit. No sub clock is generated after a reset.
After oscillation is started using the port Xc select bit (bit 4 at address 000616), the sub-clock can be
selected as the BCLK by using the system clock select bit (bit 7 at address 000616). However, be sure
that the sub-clock oscillation has fully stabilized before switching.
(3) BCLK
The internal clock φ is the clock that drives the CPU, and is fc or the clock derived by dividing the main
clock by 1, 2, 4, 8, or 16. The BCLK is derived by dividing the main clock by 8 after a reset. The BCLK
signal can be output from pin BCLK by the BCLK output disable bit (bit 7 at address 000416) in the
memory expansion and the microprocessor modes.
The main clock division select bit 0 (bit 6 at address 000616) changes to “1” when shifting from highspeed/medium-speed to stop mode and at reset. When sifting from low-speed/low power dissipation
mode to stop mode, the value before stop mode is retained.
(4) Peripheral function clock (f1, f8, f32, f1SIO2, f8SIO2, f32SIO2, fAD)
The clock for the peripheral devices is derived by dividing the main clock by 1, 8 or 32. The peripheral
function clock is stopped by stopping the main clock or by setting the WAIT peripheral function clock
stop bit (bit 2 at 000616) to “1” and then executing a WAIT instruction.
(5) fC32
This clock is derived by dividing the sub-clock by 32. It is used for the timer A and timer B counts.
(6) fC
This clock has the same frequency as the sub-clock. It is used for the BCLK and for the watchdog
timer.
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M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
Figures 2.5.5 and 2.5.6 shows the system clock control registers 0 and 1.
System clock control register 0 (Note 1)
b7
b6
b5
b4
b3
b2
b1
b0
1
Symbol
CM0
Address
000616
Bit symbol
CM00
CM01
When reset
4816
Bit name
Function
Clock output function
select bit
(Valid only in single-chip
mode)
CM02
WAIT peripheral function
clock stop bit
CM03
Reserved bit
RW
b1 b0
0 0 : I/O port P57
0 1 : fC output
1 0 : f8 output
1 1 : f32 output
0 : Do not stop peripheral function clock in wait mode
1 : Stop peripheral function clock in wait mode (Note 7)
Must always be set to “1”
Port XC select bit
0 : I/O port
1 : XCIN-XCOUT generation
CM05
Main clock (XIN-XOUT)
stop bit (Notes 2, 3, 4)
0 : On
1 : Off
CM06
Main clock division select
bit 0 (Note 6)
0 : CM16 and CM17 valid
1 : Division by 8 mode
CM07
System clock select bit
(Note 5)
0 : XIN, XOUT
1 : XCIN, XCOUT
CM04
Notes 1: Set bit 0 of the protect register (address 000A16) to “1” before writing to this register.
2: When entering power saving mode, main clock stops using this . When returning from stop mode and
operating with XIN, set this bit to “0.” When main clock oscillation is operating by itself, set system clock select
bit (CM07) to “1” before setting this bit to “1”.
3: When inputting external clock, only clock oscillation buffer is stopped and clock input is acceptable.
4: If this bit is set to “1,” XOUT turns “H.” The built-in feedback resistor remains being connected, so XIN turns
pulled up to XOUT (“H”) via the feedback resistor.
5: Set port Xc select bit (CM04) to “1” and stabilize the sub-clock oscillating before setting to this bit from “0” to
“1.” Do not write to both bits at the same time. And also, set the main clock stop bit (CM05) to “0” and stabilize
the main clock oscillating before setting this bit from “1” to “0.”
6: This bit changes to “1” when shifting from high-speed/medium-speed mode to stop mode and at a reset. When
shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained.
7: fC32 is not included. When operating in low-speed or low power dissipation mode, do not set this bit to "1".
Figures 2.5.5 System clock control register 0
System clock control register 1 (Note 1)
b7
b6
b5
b4
b3
b2
0
0
0 0
b1
b0
Symbol
CM1
Address
000716
Bit symbol
CM10
When reset
2016
Bit name
All clock stop control bit
(Note 4)
Reserved bits
Function
RW
0 : Clock on
1 : All clocks off (stop mode)
Must always be set to “0”
CM15
XIN-XOUT drive capacity
select bit (Note 2)
0 : LOW
1 : HIGH
CM16
Main clock division
select bit 1 (Note 3)
0 0 : No division mode
0 1 : Division by 2 mode
1 0 : Division by 4 mode
1 1 : Division by 16 mode
b7 b6
CM17
Notes 1: Set bit 0 of the protect register (address 000A16) to “1” before writing to this register.
2: This bit changes to “1” when shifting from high-speed/medium-speed mode to stop mode and at a
reset. When shifting from low-speed/low power dissipation mode to stop mode, the value before stop
mode is retained.
3: Can be selected when bit 6 of the system clock control register 0 (address 000616) is “0.”
If “1”, division mode is fixed at 8.
4: If this bit is set to “1,” XOUT turns “H,” and the built-in feedback resistor is cut off. XCIN and XCOUT turn
high-impedance state.
Figure 2.5.6 System clock control register 1
Rev.1.00
May 18, 2004
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M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
2.5.4 Clock Output
In single-chip mode, the clock output function select bits (bits 0 and 1 at address 000616) enable f8, f32, or
fc to be output from the P57/CLKOUT pin. When the WAIT peripheral function clock stop bit (bit 2 at
address 000616) is set to “1,” the output of f8 and f32 stops when a WAIT instruction is executed.
2.5.5 Stop Mode
Writing “1” to the all-clock stop control bit (bit 0 at address 000716) stops all oscillation and the microcomputer enters stop mode. In stop mode, the content of the internal RAM is retained provided that VCC
remains above 3.0V.
Because the oscillation, BCLK, f1 to f32, f1SIO2 to f32SIO2, fC, fC32, and fAD stops in stop mode, peripheral
functions such as the A-D converter and watchdog timer do not function. However, timer B operates
provided that the event counter mode is set to an external pulse, and UARTi (i = 0, 2) functions provided
an external clock is selected. Table 2.5.2 shows the status of the ports in stop mode.
Stop mode is cancelled by a hardware reset or an interrupt. If an interrupt is to be used to cancel stop
mode, that interrupt must first have been enabled. If returning by an interrupt, that interrupt routine is
executed.
When shifting from high-speed/medium-speed mode to stop mode and at a reset, the main clock division
select bit 0 (bit 6 at address 000616) is set to “1.” When shifting from low-speed/low power dissipation
mode to stop mode, the value before stop mode is retained.
Table 2.5.2 Port status during stop mode
Pin
Memory expansion mode
Microprocessor mode
_______
_______
Address bus, data bus, CS0 to CS3
_____
Single-chip mode
Retains status before stop mode
______ ________ ________ _________
RD, WR, BHE, WRL, WRH
“H”
__________
HLDA, BCLK
ALE
Port
CLKOUT
When fc selected
When f8, f32 selected
Rev.1.00
May 18, 2004
page 41 of 296
“H”
Unfixed
Retains status before stop mode Retains status before stop mode
Valid only in single-chip mode “H”
Valid only in single-chip mode Retains status before stop mode
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
2.5.6 Wait Mode
When a WAIT instruction is executed, the BCLK stops and the microcomputer enters the wait mode. In
this mode, oscillation continues but the BCLK and watchdog timer stop. Writing “1” to the WAIT peripheral
function clock stop bit and executing a WAIT instruction stops the clock being supplied to the internal
peripheral functions, allowing power dissipation to be reduced. However, peripheral function clock fC32
does not stop so that the peripherals using fC32 do not contribute to the power saving. When the MCU
runing in low-speed or low power dissipation mode, do not enter WAIT mode with this bit set to “1”.
Table 2.5.3 shows the status of the ports in wait mode.
Wait mode is cancelled by a hardware reset or an interrupt. If an interrupt is used to cancel wait mode, the
microcomputer restarts from the interrupt routine using as BCLK, the clock that had been selected when
the WAIT instruction was executed.
Table 2.5.3 Port status during wait mode
Pin
Memory expansion mode
Microprocessor mode
_______
_______
Address bus, data bus, CS0 to CS3
_____
Single-chip mode
Retains status before wait mode
______ ________ ________ _________
RD, WR, BHE, WRL, WRH
“H”
__________
HLDA,BCLK
ALE
Port
CLKOUT
Rev.1.00
“H”
Unfixed
Retains status before wait mode
When fC selected
Valid only in single-chip mode
When f8, f32 selected Valid only in single-chip mode
May 18, 2004
page 42 of 296
Retains status before wait mode
Does not stop
Does not stop when the WAIT
peripheral function clock stop
bit is “0”.
When the WAIT peripheral
function clock stop bit is “1”,
the status immediately prior
to entering wait mode is maintained.
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
2.5.7 Status Transition of BCLK
Power dissipation can be reduced and low-voltage operation achieved by changing the count source for
BCLK. Table 2.5.4 shows the operating modes corresponding to the settings of system clock control
registers 0 and 1.
After a reset, operation defaults to division by 8 mode. When shifting to stop mode, the main clock division
select bit 0 (bit 6 at address 000616) is set to “1”. The following shows the operational modes of internal
clock φ.
(1) Division by 2 mode
The main clock is divided by 2 to obtain the BCLK.
(2) Division by 4 mode
The main clock is divided by 4 to obtain the BCLK.
(3) Division by 8 mode
The main clock is divided by 8 to obtain the BCLK. Note that oscillation of the main clock must have
stabilized before transferring from this mode to another mode.
(4) Division by 16 mode
The main clock is divided by 16 to obtain the BCLK.
(5) No-division mode
The main clock is used as the BCLK.
(6) Low-speed mode
fC is used as the BCLK. Note that oscillation of both the main and sub clocks must have stabilized
before transferring from this mode to another or vice versa. At least 2 to 3 seconds are required after
the sub clock starts. Therefore, the program must be written to wait until this clock has stabilized
immediately after powering up and after stop mode is cancelled.
(7) Low power dissipation mode
fC is the BCLK and the main clock is stopped.
Note: When switching the count source for BCLK between XIN and XCIN, it needs that the oscillation of
the switched count source is sufficiently stable. Shift after taking the oscillation stabilizing time by
software.
Table 2.5.4 Operating modes dictated by settings of system clock control registers 0 and 1
CM17
CM16
CM07
CM06
CM05
CM04
Operating mode of BCLK
0
1
Invalid
1
0
Invalid
Invalid
Rev.1.00
1
0
Invalid
1
0
Invalid
Invalid
May 18, 2004
0
0
0
0
0
1
1
page 43 of 296
0
0
1
0
0
Invalid
Invalid
0
0
0
0
0
0
1
Invalid
Invalid
Invalid
Invalid
Invalid
1
1
Division by 2 mode
Division by 4 mode
Division by 8 mode
Division by 16 mode
No-division mode
Low-speed mode
Low power dissipation mode
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
2.5.8 Power Control
The following is a description of the three available power control modes:
Modes
Power control is available in three modes.
(1) Normal operation mode
■ High-speed mode
Divide-by-1 frequency of the main clock becomes the BCLK. The CPU operates with the internal
clock selected. Each peripheral function operates according to its assigned clock.
■ Medium-speed mode
Divide-by-2, divide-by-4, divide-by-8, or divide-by-16 frequency of the main clock becomes the
BCLK. The CPU operates according to the internal clock selected. Each peripheral function operates
according to its assigned clock.
■ Low-speed mode
fC becomes the BCLK. The CPU operates according to the fc clock. The fc clock is supplied by the
secondary clock. Each peripheral function operates according to its assigned clock.
■ Low power consumption mode
The main clock operating in low-speed mode is stopped. The CPU operates according to the fc
clock. The fc clock is supplied by the secondary clock. The only peripheral functions that operate are
those with the sub-clock selected as the count source.
(2) Wait mode
The CPU operation is stopped. The oscillators do not stop.
(3) Stop mode
All oscillators stop. The CPU and all built-in peripheral functions stop. This mode, among the three
modes listed here, is the most effective in decreasing power consumption.
Figure 2.5.7 is the state transition diagram of the above modes.
Rev.1.00
May 18, 2004
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M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
Transition of stop mode, wait mode
Reset
WAIT
instruction
CM10 = “1”
Medium-speed mode
(Divided-by-8 mode)
Stop mode
All oscillators stopped
Stop mode
Wait mode
Interrupt
Interrupt
Interrupt
WAIT
instruction
CPU operation stopped
High-speed/
medium-speed
mode
CM10 = “1”
Wait mode
Interrupt
All oscillators stopped
CPU operation stopped
WAIT
instruction
CM10 = “1”
Low-speed/
low power dissipation
mode
Stop mode
All oscillators stopped
Interrupt
Wait mode
Interrupt
Normal mode
CPU operation stopped
(See the figure below as for transition of normal mode)
Transition of normal mode
Main clock is oscillating
Sub-clock is stopped
Medium-speed mode (divided-by-8 mode)
CM06 = “1”
BCLK : f(XIN)/8
CM07 = “0”
CM06 = “1”
Main clock is oscillating
Sub-clock is oscillating
High-speed mode
CM04 = “0”
CM07 = “0”
CM06 = “1”
CM04 = “0”
(Note 1)
CM04 = “1”
(Notes 1, 3)
Main clock is oscillating
Sub-clock is oscillating
Low-speed mode
Medium-speed mode (divided-by-2)
BCLK : f(XIN)
CM07 = “0” CM06 = “0”
CM17 = “0” CM16 = “0”
BCLK : f(XIN)/2
CM07 = “0” CM06 = “0”
CM17 = “0” CM16 = “1”
Medium-speed mode (divided-by-4)
Medium-speed mode (divided-by-16)
BCLK : f(XIN)/4
CM07 = “0” CM06 = “0”
CM17 = “1” CM16 = “0”
BCLK : f(XIN)/16
CM07 = “0” CM06 = “0”
CM17 = “1” CM16 = “1”
CM07 = “0”
(Notes 1, 3)
Medium-speed mode (divided-by-8)
BCLK : f(XIN)/8
CM07 = “0”
CM06 = “1”
BCLK : f(XCIN)
CM07 = “1”
CM07 = “1”
(Note 2)
CM05 = “0”
CM04 = “0”
CM04 = “1”
Main clock is oscillating
Sub clock is stopped
CM06 = “0”
(Notes1, 3)
High-speed mode
Medium-speed mode (divided-by-2)
BCLK : f(XIN)
CM07 = “0” CM06 = “0”
CM17 = “0” CM16 = “0”
BCLK : f(XIN)/2
CM07 = “0” CM06 = “0”
CM17 = “0” CM16 = “1”
Medium-speed mode (divided-by-4)
Medium-speed mode (divided-by-16)
BCLK: f(XIN)/4
CM07 = “0” CM06 = “0”
CM17 = “1” CM16 = “0”
BCLK : f(XIN)/16
CM07 = “0” CM06 = “0”
CM17 = “1” CM16 = “1”
Low power dissipation mode
CM07 = “0”
CM06 = “0”
CM04 = “0”
(Notes 1, 3)
Figure 2.5.7 State transition diagram of Power control mode
Rev.1.00
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CM05 = “1”
Main clock is stopped
Sub-clock is oscillating
CM07 = “1”
CM05 = “1”
(Note 2)
BCLK : f(XCIN)
CM07 = “1”
Notes 1: Switch clocks after oscillation of main clock is
sufficiently stable.
2: Switch clocks after oscillation of sub-clock is
sufficiently stable.
3: Change CM06 after changing CM17 and
CM16.
4: Transit in accordance with arrows.
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
2.6 Protection
The protection function is provided so that the values in important registers cannot be changed in the event
that the program runs out of control. Figure 2.6.1 shows the protect register. The values in the processor
mode register 0 (address 000416), processor mode register 1 (address 000516), system clock control register 0 (address 000616), system clock control register 1 (address 000716) and port P9 direction register
(address 03F316) can only be changed when the respective bit in the protect register is set to “1”. Therefore, important outputs can be allocated to port P9.
If, after “1” (write-enabled) has been written to the port P9 direction register write-enable bit (bit 2 at address
000A16), a value is written to any address, the bit automatically reverts to “0” (write-inhibited). However, the
system clock control registers 0 and 1 write-enable bit (bit 0 at 000A16) and processor mode register 0 and
1 write-enable bit (bit 1 at 000A16) do not automatically return to “0” after a value has been written to an
address. The program must therefore be written to return these bits to “0”.
Protect register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
PRCR
Address
000A 16
When reset
XXXXX000 2
Bit symbol
Bit name
PRC0
Enables writing to system clock
control registers 0 and 1 (addresses
000616 and 0007 16)
PRC1
Enables writing to processor mode
0 : Write-inhibited
registers 0 and 1 (addresses 0004 16
1 : Write-enabled
and 0005 16)
PRC2
Enables writing to port P9 direction
register (address 03F3 16)
(Note)
Function
R W
0 : Write-inhibited
1 : Write-enabled
0 : Write-inhibited
1 : Write-enabled
Nothing is assigned.
In an attempt to write to these bits, write “0.” The value, if read, turns out to be
indeterminate.
Note: Writing a value to an address after “1” is written to this bit returns the bit
to “0.” Other bits do not automatically return to “0” and they must therefore
be reset by the program.
Figure 2.6.1 Protect register
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2.7 Interrupts
2.7.1 Type of Interrupts
Figure 2.7.1 lists the types of interrupts.










Hardware
Special
Peripheral I/O (Note)
















Interrupt
Software
Undefined instruction (UND instruction)
Overflow (INTO instruction)
BRK instruction
INT instruction
Reset
DBC
Watchdog timer
Single step
Address matched
________
Note: Peripheral I/O interrupts are generated by the peripheral functions built into the microcomputer system.
Figure 2.7.1 Classification of interrupts
• Maskable interrupt :
An interrupt which can be enabled (disabled) by the interrupt enable flag
(I flag) or whose interrupt priority can be changed by priority level.
• Non-maskable interrupt : An interrupt which cannot be enabled (disabled) by the interrupt enable flag
(I flag) or whose interrupt priority cannot be changed by priority level.
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2.7.2 Software Interrupts
A software interrupt occurs when executing certain instructions. Software interrupts are non-maskable
interrupts.
• Undefined instruction interrupt
An undefined instruction interrupt occurs when executing the UND instruction.
• Overflow interrupt
An overflow interrupt occurs when executing the INTO instruction with the overflow flag (O flag) set to
“1”. The following are instructions whose O flag changes by arithmetic:
ABS, ADC, ADCF, ADD, CMP, DIV, DIVU, DIVX, NEG, RMPA, SBB, SHA, SUB
• BRK interrupt
A BRK interrupt occurs when executing the BRK instruction.
• INT interrupt
An INT interrupt occurs when assiging one of software interrupt numbers 0 through 63 and executing
the INT instruction. Software interrupt numbers 0 through 31 are assigned to peripheral I/O interrupts,
so executing the INT instruction allows executing the same interrupt routine that a peripheral I/O
interrupt does.
The stack pointer (SP) used for the INT interrupt is dependent on which software interrupt number is
involved.
So far as software interrupt numbers 0 through 31 are concerned, the microcomputer saves the stack
pointer assignment flag (U flag) when it accepts an interrupt request. If change the U flag to “0” and
select the interrupt stack pointer (ISP), and then execute an interrupt sequence. When returning from
the interrupt routine, the U flag is returned to the state it was before the acceptance of interrupt request. So far as software numbers 32 through 63 are concerned, the stack pointer does not make a
shift.
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2.7.3 Hardware Interrupts
Hardware interrupts are classified into two types — special interrupts and peripheral I/O interrupts.
(1) Special interrupts
Special interrupts are non-maskable interrupts.
• Reset
____________
Reset occurs if an “L” is input to the RESET pin.
________
• DBC interrupt
This interrupt is exclusively for the debugger, do not use it in other circumstances.
• Watchdog timer interrupt
Generated by the watchdog timer.
• Single-step interrupt
This interrupt is exclusively for the debugger, do not use it in other circumstances. With the debug
flag (D flag) set to “1,” a single-step interrupt occurs after one instruction is executed.
• Address match interrupt
An address match interrupt occurs immediately before the instruction held in the address indicated
by the address match interrupt register is executed with the address match interrupt enable bit set to
“1.” If an address other than the first address of the instruction in the address match interrupt register
is set, no address match interrupt occurs.
(2) Peripheral I/O interrupts
A peripheral I/O interrupt is generated by one of built-in peripheral functions. Built-in peripheral functions are dependent on classes of products, so the interrupt factors too are dependent on classes of
products. The interrupt vector table is the same as the one for software interrupt numbers 0 through
31 the INT instruction uses. Peripheral I/O interrupts are maskable interrupts.
• Bus collision detection interrupt
This is an interrupt that the serial I/O bus collision detection generates.
• DMA0 interrupt, DMA1 interrupt
These are interrupts DMA generates.
• VSYNC interrupt
VSYNC interrupt occurs if a VSYNC edge is input.
• A-D conversion interrupt
This is an interrupt that the A-D converter generates.
• UART0 transmission, UART2 transmission interrupts
These are interrupts that the serial I/O transmission generates.
• UART0 reception, UART2 reception interrupts
These are interrupts that the serial I/O reception generates.
• Multi-master I2C-BUS interface 0 and multi-master I2C-BUS interface 1 interrupts
This is an interrupt that the serial I/O transmission/reception is completed, or a STOP condition is
detected.
• Timer A0 interrupt through timer A4 interrupt
These are interrupts that timer A generates
• Timer B0 interrupt through timer B2 interrupt
These are interrupts that timer B generates.
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M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
________
________
• INT0 interrupt and INT1 interrupt
______
______
An INT interrupt occurs if either a rising edge or a falling edge or a both edge is input to the INT pin.
• OSD1 interrupt and OSD2 interrupt
These are interrupts that OSD display is completed.
• Data slicer 0 interrupt and Data slicer 1 interrupt
These are interrupts that data slicer circuit requests.
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2.7.4 Interrupts and Interrupt Vector Tables
If an interrupt request is accepted, a program branches to the interrupt routine set in the interrupt vector
table. Set the first address of the interrupt routine in each vector table. Figure 2.7.2 shows the format for
specifying the address.
Two types of interrupt vector tables are available — fixed vector table in which addresses are fixed and
variable vector table in which addresses can be varied by the setting.
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
MSB
Vector address + 0
Vector address + 1
Vector address + 2
Vector address + 3
LSB
Low address
Mid address
0000
High address
0000
0000
Figure 2.7.2 Format for specifying interrupt vector addresses
(1) Fixed vector tables
The fixed vector table is a table in which addresses are fixed. The vector tables are located in an area
extending from FFFDC16 to FFFFF16. One vector table comprises four bytes. Set the first address of
interrupt routine in each vector table. Table 2.7.1 shows the interrupts assigned to the fixed vector
tables and addresses of vector tables.
Table 2.7.1 Interrupts assigned to the fixed vector tables and addresses of vector tables
Interrupt source
Undefined instruction
Vector table addresses
Address (L) to address (H)
FFFDC16 to FFFDF16
Overflow
BRK instruction
FFFE016 to FFFE316
FFFE416 to FFFE716
Address match
Single step (Note)
Watchdog timer
FFFE816 to FFFEB16
FFFEC16 to FFFEF16
FFFF016 to FFFF316
Remarks
Interrupt on UND instruction
Interrupt on INTO instruction
If the vector is filled with FF16, program execution starts from
the address shown by the vector in the variable vector table
There is an address-matching interrupt enable bit
Do not use
________
DBC (Note)
FFFF416 to FFFF716
Do not use
Reserved source
FFFF816 to FFFFB16
Do not use
Reset
FFFFC16 to FFFFF16
Note: Interrupts used for debugging purposes only.
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(2) Variable vector tables
The fixed vector table is a table in which addresses are fixed. The vector tables are located in an area
extending from FFFDC16 to FFFFF16. One vector table comprises four bytes. Set the first address of
interrupt routine in each vector table. Table 2.7.2 shows the interrupts assigned to the fixed vector
tables and addresses of vector tables.
Table 2.7.2 Interrupts assigned to the variable vector tables and addresses of vector tables
Software interrupt number
Vector table address
Interrupt source
Address (L) to address (H)
Software interrupt number 0
+0 to +3 (Note)
BRK instruction
Software interrupt number 4
+16 to +19 (Note)
OSD1
Software interrupt number 5
+20 to +23 (Note)
Data slicer 1
Software interrupt number 6
+24 to +27 (Note)
Reserved source
Software interrupt number 7
+28 to +31 (Note)
Reserved source
Software interrupt number 8
+32 to +35 (Note)
OSD2
Software interrupt number 9
+36 to +39 (Note)
Multi-master I2C-BUS interface 1
Software interrupt number 10
+40 to +43 (Note)
Bus collision detection
Software interrupt number 11
+44 to +47 (Note)
DMA0
Software interrupt number 12
+48 to +51 (Note)
DMA1
Software interrupt number 13
+52 to +55 (Note)
Multi-master I2C-BUS interface 0
Software interrupt number 14
+56 to +59 (Note)
A-D conversion
Software interrupt number 15
+60 to +63 (Note)
UART2 transmit
Software interrupt number 16
+64 to +67 (Note)
UART2 receive
Software interrupt number 17
+68 to +71 (Note)
UART0 transmit
Software interrupt number 18
+72 to +75 (Note)
UART0 receive
Software interrupt number 19
+76 to +79 (Note)
Data slicer0
Software interrupt number 20
+80 to +83 (Note)
VSYNC
Software interrupt number 21
+84 to +87 (Note)
Timer A0
Software interrupt number 22
+88 to +91 (Note)
Timer A1
Software interrupt number 23
+92 to +95 (Note)
Timer A2
Software interrupt number 24
+96 to +99 (Note)
Timer A3
Software interrupt number 25
+100 to +103 (Note)
Timer A4
Software interrupt number 26
+104 to +107 (Note)
Timer B0
Software interrupt number 27
+108 to +111 (Note)
Timer B1
Software interrupt number 28
+112 to +115 (Note)
Timer B2
Software interrupt number 29
+116 to +119 (Note)
INT0
Software interrupt number 30
+120 to +123 (Note)
INT1
Software interrupt number 31
+124 to +127 (Note)
Reserved source
Software interrupt number 32
+128 to +131 (Note)
to
Software interrupt number 63
to
+252 to +255 (Note)
Software interrupt
Note: Address relative to address in interrupt table register (INTB).
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Remarks
Cannot be masked I flag
Cannot be masked I flag
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
2.7.5 Interrupt Control
Descriptions are given here regarding how to enable or disable maskable interrupts and how to set the
priority to be accepted. What is described here does not apply to non-maskable interrupts.
Enable or disable a non-maskable interrupt using the interrupt enable flag (I flag), interrupt priority level
selection bit, or processor interrupt priority level (IPL). Whether an interrupt request is present or absent
is indicated by the interrupt request bit. The interrupt request bit and the interrupt priority level selection
bit are located in the interrupt control register of each interrupt. Also, the interrupt enable flag (I flag) and
the IPL are located in the flag register (FLG).
Figure 2.7.3 shows the interrupt control registers.
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M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
Symbol
OSDiIC(i = 1, 2)
DS1IC
BCNIC
DMiIC(i = 0, 1)
IIC0IC
ADIC
SiTIC(i = 0 , 2)
SiRIC(i = 0 , 2)
DS0IC
VSYNCIC
TAiIC(i = 0 to 4)
TBiIC(i = 0 to 2)
Interrupt control register
b7
b6
b5
b4
b3
b2
b1
b0
Bit symbol
ILVL0
Address
004416, 0048 16
0045 16
004A 16
004B 16, 004C 16
004D 16
004E 16
0051 16, 004F16
0052 16, 0050 16
0053 16
0054 16
0055 16 to 0059 16
005A16 to 005C 16
Bit name
Interrupt priority level
select bit
ILVL1
ILVL2
IR
Interrupt request bit
When reset
XXXX?000 2
XXXX?000 2
XXXX?000 2
XXXX?000 2
XXXX?000 2
XXXX?000 2
XXXX?000 2
XXXX?000 2
XXXX?000 2
XXXX?000 2
XXXX?000 2
XXXX?000 2
Function
R
W
b2 b1 b0
000:
001:
010:
011:
100:
101:
110:
111:
Level 0 (interrupt disabled)
Level 1
Level 2
Level 3
Level 4
Level 5
Level 6
Level 7
0 : Interrupt not requested
1 : Interrupt requested
(Note)
Nothing is assigned.
In an attempt to write to these bits, write “0.” The value, if read, turns out to
be indeterminate.
Notes 1: This bit can only be accessed for reset (= 0), but cannot be accessed for set (= 1).
2: To rewrite the interrupt control register, do so at a point that does not generate the
interrupt register for that register. For details, see the precautions for interrupts.
b7
b6
b5
b4
0
b3
b2
b1
b0
Symbol
INTiIC(i = 0, 1)
IIC1IC
Bit symbol
ILVL0
Address
005D 16, 005E16
0049 16
Bit name
Interrupt priority level
select bit
ILVL1
ILVL2
IR
POL
When reset
XX00?000 2
XX00?000 2
Interrupt request bit
Polarity select bit
(Note 2)
Reserved bit
Function
R
W
b2 b1 b0
0 0 0 : Level 0 (interrupt disabled)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
0: Interrupt not requested
1: Interrupt requested
(Note 1)
0 : Selects falling edge
1 : Selects rising edge
Must always be set to “0”
Nothing is assigned.
In an attempt to write to these bits, write “0.” The value, if read, turns out to
be indeterminate.
Notes 1: This bit can only be accessed for reset (= 0), but cannot be accessed for set (= 1).
2: Bit 4 at address 0049 16 is invalid. Must always be set to “0.”
3: To rewrite the interrupt control register, do so at a point that does not generate the
interrupt register for that register. For details, see the precautions for interrupts.
Figure 2.7.3 Interrupt control registers
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2.7.6 Interrupt Enable Flag (I flag)
The interrupt enable flag (I flag) controls the enabling and disabling of maskable interrupts. Setting this
flag to “1” enables all maskable interrupts; setting it to “0” disables all maskable interrupts. This flag is set
to “0” after reset.
2.7.7 Interrupt Request Bit
The interrupt request bit is set to "1" by hardware when an interrupt is requested. After the interrupt is
accepted and jumps to the corresponding interrupt vector, the request bit is set to "0" by hardware. The
interrupt request bit can also be set to "0" by software. (Do not set this bit to "1").
2.7.8 Interrupt Priority Level Select Bit and Processor Interrupt Priority Level (IPL)
Set the interrupt priority level using the interrupt priority level select bit, which is one of the component bits
of the interrupt control register. When an interrupt request occurs, the interrupt priority level is compared
with the IPL. The interrupt is enabled only when the priority level of the interrupt is higher than the IPL.
Therefore, setting the interrupt priority level to “0” disables the interrupt.
Table 2.7.3 shows the settings of interrupt priority levels and Table 2.7.4 shows the interrupt levels enabled, according to the consist of the IPL.
The following are conditions under which an interrupt is accepted:
· interrupt enable flag (I flag) = 1
· interrupt request bit = 1
· interrupt priority level > IPL
The interrupt enable flag (I flag), the interrupt request bit, the interrupt priority select bit, and the IPL are
independent, and they are not affected by one another.
Table 2.7.3 Settings of interrupt priority levels
Interrupt priority
level select bit
Interrupt priority
level
Priority
order
b2 b1 b0
Rev.1.00
Table 2.7.4 Interrupt levels enabled according
to the contents of the IPL
IPL
Enabled interrupt priority levels
IPL2 IPL1 IPL0
0
0
0
Level 0 (interrupt disabled)
0
0
0
Interrupt levels 1 and above are enabled
0
0
1
Level 1
0
0
1
Interrupt levels 2 and above are enabled
0
1
0
Level 2
0
1
0
Interrupt levels 3 and above are enabled
0
1
1
Level 3
0
1
1
Interrupt levels 4 and above are enabled
1
0
0
Level 4
1
0
0
Interrupt levels 5 and above are enabled
1
0
1
Level 5
1
0
1
Interrupt levels 6 and above are enabled
1
1
0
Level 6
1
1
0
Interrupt levels 7 and above are enabled
1
1
1
Level 7
1
1
1
All maskable interrupts are disabled
May 18, 2004
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Low
High
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
2.7.9 Rewrite Interrupt Control Register
To rewrite the interrupt control register, do so at a point that does not generate the interrupt request for
that register. If there is possibility of the interrupt request occur, rewrite the interrupt control register after
the interrupt is disabled. The program examples are described as follow:
Example 1:
INT_SWITCH1:
FCLR
I
AND.B #00h, 0055h
NOP
NOP
FSET
I
; Disable interrupts.
; Clear TA0IC int. priority level and int. request bit.
; Four NOP instructions are required when using HOLD function.
; Enable interrupts.
Example 2:
INT_SWITCH2:
FCLR
I
AND.B #00h, 0055h
MOV.W MEM, R0
FSET
I
; Disable interrupts.
; Clear TA0IC int. priority level and int. request bit.
; Dummy read.
; Enable interrupts.
Example 3:
INT_SWITCH3:
PUSHC FLG
FCLR
I
AND.B #00h, 0055h
POPC FLG
; Push Flag register onto stack
; Disable interrupts.
; Clear TA0IC int. priority level and int. request bit.
; Enable interrupts.
The reason why two NOP instructions (four when using the HOLD function) or dummy read are inserted
before FSET I in Examples 1 and 2 is to prevent the interrupt enable flag I from being set before the
interrupt control register is rewritten due to effects of the instruction queue.
When a instruction to rewrite the interrupt control register is executed but the interrupt is disabled, the
interrupt request bit is not set sometimes even if the interrupt request for that register has been generated. This will depend on the instruction. If this creates problems, use the below instructions to change
the register.
Instructions : AND, OR, BCLR, BSET
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2.7.10 Interrupt Sequence
An interrupt sequence — what are performed over a period from the instant an interrupt is accepted to the
instant the interrupt routine is executed — is described here.
If an interrupt occurs during execution of an instruction, the processor determines its priority when the
execution of the instruction is completed, and transfers control to the interrupt sequence from the next
cycle. If an interrupt occurs during execution of either the SMOVB, SMOVF, SSTR or RMPA instruction,
the processor temporarily suspends the instruction being executed, and transfers control to the interrupt
sequence.
In the interrupt sequence, the processor carries out the following in sequence given:
(1) CPU gets the interrupt information (the interrupt number and interrupt request level) by reading address 0000016.
(2) Saves the content of the flag register (FLG) as it was immediately before the start of interrupt sequence in the temporary register (Note) within the CPU.
(3) Sets the interrupt enable flag (I flag), the debug flag (D flag), and the stack pointer select flag (U flag)
to “0” (the U flag, however does not change if the INT instruction, in software interrupt numbers 32
through 63, is executed)
(4) Saves the content of the temporary register (Note 1) within the CPU in the stack area.
(5) Saves the content of the program counter (PC) in the stack area.
(6) Sets the interrupt priority level of the accepted instruction in the IPL.
After the interrupt sequence is completed, the processor resumes executing instructions from the first
address of the interrupt routine.
Note: This register cannot be utilized by the user.
2.7.11 Interrupt Response Time
'Interrupt response time' is the period between the instant an interrupt occurs and the instant the first
instruction within the interrupt routine has been executed. This time comprises the period from the
occurrence of an interrupt to the completion of the instruction under execution at that moment (a) and the
time required for executing the interrupt sequence (b). Figure 2.7.4 shows the interrupt response time.
Interrupt request generated
Interrupt request acknowledged
Time
Instruction
(a)
Interrupt sequence
(b)
Interrupt response time
Figure 2.7.4 Interrupt response time
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Instruction in
interrupt routine
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
Time (a) is dependent on the instruction under execution. Thirty cycles is the maximum required for the
DIVX instruction (without wait).
Time (b) is as shown in Table 2.7.5.
Table 2.7.5 Time required for executing the interrupt sequence
Interrupt vector address
Stack pointer (SP) value
16-Bit bus, without wait
8-Bit bus, without wait
Even
Even
18 cycles (Note 1)
20 cycles (Note 1)
Even
Odd
19 cycles (Note 1)
20 cycles (Note 1)
Odd (Note 2)
Even
19 cycles (Note 1)
20 cycles (Note 1)
Odd (Note 2)
Odd
20 cycles (Note 1)
20 cycles (Note 1)
________
Notes 1: Add 2 cycles in the case of a DBC interrupt; add 1 cycle in the case either of an address coincidence interrupt or of a single-step interrupt.
2: Locate an interrupt vector address in an even address, if possible.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
BCLK
Address bus
Data bus
Address
0000
Interrupt
information
R
Indeterminate
Indeterminate
SP-2
SP-4
SP-2
contents
SP-4
contents
vec
vec+2
vec
contents
PC
vec+2
contents
Indeterminate
W
The indeterminate segment is dependent on the queue buffer.
If the queue buffer is ready to take an instruction, a read cycle occurs.
Figure 2.7.5 Time required for executing the interrupt sequence
2.7.12 Variation of IPL when Interrupt Request is Accepted
If an interrupt request is accepted, the interrupt priority level of the accepted interrupt is set in the IPL.
If an interrupt request, that does not have an interrupt priority level, is accepted, one of the values shown
in Table 2.7.6 is set in the IPL.
Table 2.7.6 Relationship between interrupts without interrupt priority levels and IPL
Interrupt sources without priority levels
Value set in the IPL
Watchdog timer
7
Reset
0
Not changed
Other
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2.7.13 Saving Registers
In the interrupt sequence, only the contents of the flag register (FLG) and that of the program counter
(PC) are saved in the stack area.
First, the processor saves the four higher-order bits of the program counter, and 4 upper-order bits and 8
lower-order bits of the FLG register, 16 bits in total, in the stack area, then saves 16 lower-order bits of the
program counter. Figure 2.7.6 shows the state of the stack as it was before the acceptance of the interrupt request, and the state the stack after the acceptance of the interrupt request.
Save other necessary registers at the beginning of the interrupt routine using software. Using the
PUSHM instruction alone can save all the registers except the stack pointer (SP).
Address
MSB
Stack area
Address
MSB
LSB
Stack area
LSB
m–4
m–4
Program counter (PCL)
m–3
m–3
Program counter (PCM)
m–2
m–2
Flag register (FLGL)
m–1
m–1
m
Content of previous stack
m+1
Content of previous stack
Stack status before interrupt request
is acknowledged
[SP]
Stack pointer
value before
interrupt occurs
Flag register
(FLGH)
Program
counter (PCH)
m
Content of previous stack
m+1
Content of previous stack
Stack status after interrupt request
is acknowledged
Figure 2.7.6 State of stack before and after acceptance of interrupt request
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[SP]
New stack
pointer value
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
The operation of saving registers carried out in the interrupt sequence is dependent on whether the
content of the stack pointer, at the time of acceptance of an interrupt request, is even or odd. If the
content of the stack pointer (Note) is even, the content of the flag register (FLG) and the content of the
program counter (PC) are saved, 16 bits at a time. If odd, their contents are saved in two steps, 8 bits at
a time. Figure 2.7.7 shows the operation of the saving registers.
Note: Stack pointer indicated by U flag.
(1) Stack pointer (SP) contains even number
Address
Stack area
Sequence in which order
registers are saved
[SP] – 5 (Odd)
[SP] – 4 (Even)
Program counter (PCL)
[SP] – 3(Odd)
Program counter (PCM)
[SP] – 2 (Even)
Flag register (FLGL)
[SP] – 1(Odd)
[SP]
Flag register
(FLGH)
Program
counter (PCH)
(2) Saved simultaneously,
all 16 bits
(1) Saved simultaneously,
all 16 bits
(Even)
Finished saving registers
in two operations.
(2) Stack pointer (SP) contains odd number
Address
Stack area
Sequence in which order
registers are saved
[SP] – 5 (Even)
[SP] – 4(Odd)
Program counter (PCL)
(3)
[SP] – 3 (Even)
Program counter (PCM)
(4)
[SP] – 2(Odd)
Flag register (FLGL)
[SP] – 1 (Even)
[SP]
Flag register
(FLGH)
Program
counter (PCH)
Saved simultaneously,
all 8 bits
(1)
(2)
(Odd)
Finished saving registers
in four operations.
Note: [SP] denotes the initial value of the stack pointer (SP) when interrupt request is acknowledged.
After registers are saved, the SP content is [SP] minus 4.
Figure 2.7.7 Operation of saving registers
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2.7.14 Returning from an Interrupt Routine
Executing the REIT instruction at the end of an interrupt routine returns the contents of the flag register
(FLG) as it was immediately before the start of interrupt sequence and the contents of the program
counter (PC), both of which have been saved in the stack area. Then control returns to the program that
was being executed before the acceptance of the interrupt request, so that the suspended process resumes.
Return the other registers saved by software within the interrupt routine using the POPM or similar instruction before executing the REIT instruction.
2.7.15 Interrupt Priority
If there are two or more interrupt requests occurring at a point in time within a single sampling (checking
whether interrupt requests are made), the interrupt assigned a higher priority is accepted.
Assign an arbitrary priority to maskable interrupts (peripheral I/O interrupts) using the interrupt priority
level select bit. If the same interrupt priority level is assigned, however, the interrupt assigned a higher
hardware priority is accepted.
Priorities of the special interrupts, such as Reset (dealt with as an interrupt assigned the highest priority),
watchdog timer interrupt, etc. are regulated by hardware.
Figure 2.7.8 shows the priorities of hardware interrupts.
Software interrupts are not affected by the interrupt priority. If an instruction is executed, control branches
invariably to the interrupt routine.
2.7.16 Interrupt Priority Level Resolution Circuit
When two or more interrupts are generated simultaneously, this circuit selects the interrupt with the highest
priority level.
Figure 2.7.9 shows the circuit that judges the interrupt priority level.
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________
Reset > DBC > Watchdog timer > Peripheral I/O > Single step > Address match
Figure 2.7.8 Hardware interrupts priorities
Priority level of each interrupt
INT1
Level 0 (initial value)
High
Timer B2
Timer B0
Timer A3
Timer A1
OSD1
INT0
Timer B1
Timer A4
Timer A2
Data slicer 1
VSYNC
UART0 reception
UART2 reception
A-D conversion
Priority of peripheral I/O interrupts
(if priority levels are same)
DMA1
Bus collision detection
OSD2
Timer A0
Data slicer 0
UART0 transmission
UART2 transmission
Multi-master I2C-BUS interface 0
DMA0
Multi-master I2C-BUS interface 1
Low
Processor interrupt priority level (IPL)
Interrupt enable flag (I flag)
Address match
Watchdog timer
DBC
Reset
Figure 2.7.9 Maskable interrupts priorities (peripheral I/O interrupts)
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Interrupt request accepted
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
______
2.7.17 INT Interrupt
________
________
INT0 and INT1 are triggered by the edges of external inputs. The edge polarity is selected using the
polarity select bit.
As for external interrupt input, an interrupt can be generated both at the rising edge and at the falling edge
by setting “1” in the INTi interrupt polarity switching bit of the interrupt request cause select register
(035F16). To select both edges, set the polarity switching bit of the corresponding interrupt control register to ‘falling edge’ (“0”).
Figure 2.7.10 shows the Interrupt control reserved register, Figure 2.7.11 shows the Interrupt request
cause select register.
Interrupt control reserved register i
b7
b6
b5
0
0
0 0
b4
b3
b2
b1
b0
0 0
0
0
Symbol
REiIC (i = 1 to 3)
Address
004616, 004716, 005F16
Bit name
Bit symbol
When reset
Indeterminate
Function
R W
Must always be set to “0”
Reserved bits
Figure 2.7.10 Interrupt control reserved register i (i = 0 to 3)
Interrupt request cause select register
b7
b6
0
0 0 0
b5
b4
b3
b2
0 0
b1
b0
Symbol
IFSR
Address
035F16
Bit name
Bit symbol
INT0 interrupt polarity
switching bit
0 : One edge
1 : Two edges
IFSR1
INT1 interrupt polarity
switching bit
0 : One edge
1 : Two edges
Figure 2.7.11 Interrupt request cause select register
May 18, 2004
Function
IFSR0
Reserved bits
Rev.1.00
When reset
0016
page 63 of 296
Must always be set to “0”
R W
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
2.7.18 Address Match Interrupt
An address match interrupt is generated when the address match interrupt address register contents
match the program counter value. Two address match interrupts can be set, each of which can be
enabled and disabled by an address match interrupt enable bit. Address match interrupts are not affected by the interrupt enable flag (I flag) and processor interrupt priority level (IPL). The value of the
program counter (PC) for an address match interrupt varies depending on the instruction being executed.
Figures 2.7.12 and 2.7.13 show the address match interrupt-related registers.
Address match interrupt enable register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
AIER
Bit symbol
Address
0009 16
When reset
XXXXXX00 2
Bit name
Function
AIER0
Address match interrupt 0
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
AIER1
Address match interrupt 1
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
RW
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to
be indeterminated.
Figure 2.7.12 Address match interrupt enable register
Address match interrupt register i (i = 0, 1)
(b23)
b7
(b19)
b3
(b16)(b15)
b0 b7
(b8)
b0 b7
b0
Symbol
RMAD0
RMAD1
Address
001216 to 0010 16
001616 to 0014 16
Function
Address setting register for address match interrupt
When reset
X00000 16
X00000 16
Values that can be set R W
00000 16 to FFFFF 16
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to
be indeterminated.
Figure 2.7.13 Address match interrupt register i (i = 0, 1)
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2.7.19 Precautions for Interrupts
(1) Reading address 0000016
• When maskable interrupt is occurred, CPU read the interrupt information (the interrupt number and
interrupt request level) in the interrupt sequence.
The interrupt request bit of the certain interrupt written in address 0000016 will then be set to “0”.
Reading address 0000016 by software sets enabled highest priority interrupt source request bit to “0”.
Though the interrupt is generated, the interrupt routine may not be executed.
Do not read address 0000016 by software.
(2) Setting the stack pointer
• The value of the stack pointer immediately after reset is initialized to 000016. Accepting an interrupt
before setting a value in the stack pointer may become a factor of runaway. Be sure to set a value in
the stack pointer before accepting an interrupt.
(3) External interrupt
________
• Either an “L” level or an “H” level of at least 250 ns width is necessary for the signal input to pins INT0
_______
and INT1 regardless of the CPU operation clock.
_______
_______
•When the polarity of the INT0 and INT1 pins is changed, the interrupt request bit is sometimes set to
“1”. After changing the polarity, set the interrupt request bit to “0”. Figure 2.7.14 shows the procedure
______
for changing the INT interrupt generate factor.
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Clear the interrupt enable flag to “0”
(Disable interrupt)
Set the interrupt priority level to level 0
(Disable INTi interrupt)
Set the polarity select bit
Clear the interrupt request bit to “0”
Set the interrupt priority level to level 1 to 7
(Enable the accepting of INTi interrupt request)
Set the interrupt enable flag to “1”
(Enable interrupt)
______
Figure 2.7.14 Switching condition of INT interrupt request
(4) Rewrite interrupt control register
• To rewrite the interrupt control register, do so at a point that does not generate the interrupt request
for that register. If there is possibility of the interrupt request occur, rewrite the interrupt control register after the interrupt is disabled. The program examples are described as follow:
Example 1:
INT_SWITCH1:
FCLR
I
AND.B #00h, 0055h
NOP
NOP
FSET
I
; Disable interrupts.
; Clear TA0IC int. priority level and int. request bit.
; Four NOP instructions are required when using HOLD function.
; Enable interrupts.
Example 2:
INT_SWITCH2:
FCLR
I
AND.B #00h, 0055h
MOV.W MEM, R0
FSET
I
; Disable interrupts.
; Clear TA0IC int. priority level and int. request bit.
; Dummy read.
; Enable interrupts.
Example 3:
INT_SWITCH3:
PUSHC FLG
FCLR
I
AND.B #00h, 0055h
POPC FLG
; Push Flag register onto stack
; Disable interrupts.
; Clear TA0IC int. priority level and int. request bit.
; Enable interrupts.
The reason why two NOP instructions (four when using the HOLD function) or dummy read are inserted
before FSET I in Examples 1 and 2 is to prevent the interrupt enable flag I from being set before the
interrupt control register is rewritten due to effects of the instruction queue.
• When a instruction to rewrite the interrupt control register is executed but the interrupt is disabled, the
interrupt request bit is not set sometimes even if the interrupt request for that register has been
generated. This will depend on the instruction. If this creates problems, use the below instructions to
change the register.
Instructions : AND, OR, BCLR, BSET
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(5) Notes
When clearing interrupt request bit of interrupt control register, depending on the instruction to be
used, it interrupts and interrupt request bit may not be cleared. Use MOV command, when clear
interrupt request bit, and change interrupt control register. When change interrupt control register in
M16C/60 series and M16C/20 series, interrupt control register be sure to change in the part which
corresponding interrupt request does not generate, and change interrupt control register after changing interruption into a prohibition state.
The example of a program which clears interrupt request bit in M16C/60 series.
Example 1: The case where interrupt control register is rewritten with a immediate value
FCLR
I
; Interrupt is forbidden
MOV.B
#00H,0055H
; Timer A0 interrupt request bit clear
MOV.W MEM,R0
; Dummy read
FSET
I
; Interrupt is permitted
Example 2: The case where only interrupt request bit is cleared
FCLR
I
; Interrupt is forbidden
MOV.B
0055H,R0L
; Timer A0 interrupt control register read-out
AND.B
#0F7H,R0L
; Only timer A0 interruption request bit is clear
MOV.B
R0L,0055H
; Timer A0 interrupt control register writing
MOV.W MEM,R0
; Dummy read
FSET
I
; Interrupt is permitted
There is a dummy read in Example 1 and Example 2 for preventing the set of interrupt permission flag
(I flag) interrupting under the influence of command cue, and performing before the writing of interrupt
control register.
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2.8 Watchdog Timer
The watchdog timer has the function of detecting when the program is out of control. The watchdog timer is
a 15-bit counter which down-counts the clock derived by dividing the BCLK using the prescaler. A watchdog
timer interrupt is generated when an underflow occurs in the watchdog timer. When XIN is selected for the
BCLK, bit 7 of the watchdog timer control register (address 000F16) selects the prescaler division ratio (by
16 or by 128). When XCIN is selected as the BCLK , the prescaler is set for division by 2 regardless of bit 7
of the watchdog timer control register (address 000F16). Thus the watchdog timer’s period can be calculated as given below. The watchdog timer’s period is, however, subject to an error due to the pre-scaler.
With XIN chosen for BCLK
Watchdog timer period =
pre-scaler dividing ratio (16 or 128) ✕ watchdog timer count (32768)
BCLK
With XCIN chosen for BCLK
Watchdog timer period =
pre-scaler dividing ratio (2) ✕ watchdog timer count (32768)
BCLK
For example suppose that BCLK runs at 16 MHz and that 16 has been chosen for the dividing ratio of the
pre-scaler, then the watchdog timer’s period becomes approximately 32.8 ms.
The watchdog timer is initialized by writing to the watchdog timer start register (address 000E16) and when
a watchdog timer interrupt request is generated. The prescaler is initialized only when the microcomputer is
reset. After a reset is cancelled, the watchdog timer and prescaler are both stopped. The count is started by
writing to the watchdog timer start register (address 000E16).
Figure 2.8.1 shows the block diagram of the watchdog timer. Figure 2.8.2 shows the watchdog timer control
register and Figure 2.8.3 shows the watchdog timer start register.
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M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
Prescaler
“CM07 = 0”
“WDC7 = 0”
1/16
BCLK
“CM07 = 0”
“WDC7 = 1”
1/128
Watchdog timer
HOLD
Watchdog timer
interrupt request
“CM07 = 1”
1/2
Write to the watchdog timer
start register
(address 000E 16)
Set to
“7FFF 16 ”
RESET
Figure 2.8.1 Block diagram of watchdog timer
Watchdog timer control register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
WDC
0 0
Address
000F 16
When reset
000????? 2
Bit name
Bit symbol
Function
R W
High-order bit of watchdog timer
Reserved bits
Must always be set to “0”
WDC7
0 : Divided by 16
1 : Divided by 128
Prescaler select bit
Figure 2.8.2 Watchdog timer control register
Watchdog timer start register
b7
b0
Symbol
WDTS
Address
000E 16
When reset
Indeterminate
Function
The watchdog timer is initialized and starts counting after a write instruction to
this register. The watchdog timer value is always initialized to “7FFF 16”
regardless of whatever value is written.
Figure 2.8.3 Watchdog timer start register
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R W
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
2.9 DMAC
This microcomputer has two DMAC (direct memory access controller) channels that allow data to be sent to
memory without using the CPU. DMAC shares the same data bus with the CPU. The DMAC is given a
higher right of using the bus than the CPU, which leads to working the cycle stealing method. On this
account, the operation from the occurrence of DMA transfer request signal to the completion of 1-word (16bit) or 1-byte (8-bit) data transfer can be performed at high speed. Figure 2.9.1 shows the block diagram of
the DMAC. Table 2.9.1 shows the DMAC specifications. Figures 2.9.2 to 2.9.7 show the registers used by
the DMAC.
Address bus
DMA0 source pointer SAR0(20)
(addresses 0022 16 to 0020 16)
DMA0 destination pointer DAR0 (20)
(addresses 0026 16 to 0024 16)
DMA0 forward address pointer (20) (Note)
DMA0 transfer counter reload register TCR0 (16)
(addresses 0029 16, 0028 16)
DMA1 source pointer SAR1 (20)
(addresses 0032 16 to 0030 16)
DMA0 transfer counter TCR0 (16)
DMA1 destination pointer DAR1 (20)
DMA1 transfer counter reload register TCR1 (16)
DMA1 forward address pointer (20) (Note)
(addresses 0036 16 to 0034 16)
(addresses 0039 16, 0038 16)
DMA1 transfer counter TCR1 (16)
DMA latch high-order bits
DMA latch low-order bits
Data bus low-order bits
Data bus high-order bits
Note: Pointer is incremented by a DMA request.
Figure 2.9.1 Block diagram of DMAC
Either a write signal to the software DMA request bit or an interrupt request signal is used as a DMA transfer
request signal. But the DMA transfer is affected neither by the interrupt enable flag (I flag) nor by the
interrupt priority level. The DMA transfer doesn't affect any interrupts either.
If the DMAC is active (the DMA enable bit is set to 1), data transfer starts every time a DMA transfer request
signal occurs. If the cycle of the occurrences of DMA transfer request signals is higher than the DMA
transfer cycle, there can be instances in which the number of transfer requests doesn't agree with the
number of transfers. For details, see the description of the DMA request bit.
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Table 2.9.1 DMAC specifications
Item
No. of channels
Transfer memory space
Maximum No. of bytes transferred
Specification
2 (cycle steal method)
• From any address in the 1M bytes space to a fixed address
• From a fixed address to any address in the 1M bytes space
• From a fixed address to a fixed address
(Note that DMA-related registers [002016 to 003F16] cannot be accessed)
128K bytes (with 16-bit transfers) or 64K bytes (with 8-bit transfers)
________
Falling edge or both edge of pin INT0
_______
Falling edge of pin INT1
Timer A0 to timer A4 interrupt requests
Timer B0 to timer B2 interrupt requests
UART0 transmission and reception interrupt requests
UART2 transmission and reception interrupt requests
Multi-master I2C-BUS interface 0 interrupt request
Multi-master I2C-BUS interface 1 interrupt request
A-D conversion interrupt request
OSD1 and OSD2 interrupt requests
Data slicer 0 interrupt request (Note2)
VSYNC interrupt request
Software triggers
Channel priority
DMA0 takes precedence if DMA0 and DMA1 requests are generated simultaneously
Transfer unit
8 bits or 16 bits
Transfer address direction
forward/fixed (forward direction cannot be specified for both source and
destination simultaneously)
Transfer mode
• Single transfer mode
After the transfer counter underflows, the DMA enable bit turns to “0”, and the
DMAC turns inactive
• Repeat transfer mode
After the transfer counter underflows, the value of the transfer counter reload
register is reloaded to the transfer counter.
The DMAC remains active unless a “0” is written to the DMA enable bit.
DMA interrupt request generation timing When an underflow occurs in the transfer counter
Active
When the DMA enable bit is set to “1”, the DMAC is active.
When the DMAC is active, data transfer starts every time a DMA transfer request
signal occurs.
Inactive
• When the DMA enable bit is set to “0”, the DMAC is inactive.
• After the transfer counter underflows in single transfer mode
Forward address pointer and
At the time of starting data transfer immediately after turning the DMAC active,
reload timing for transfer counter
the value of one of source pointer and destination pointer - the one specified for
the forward direction - is reloaded to the forward direction address pointer, and
the value of the transfer counter reload register is reloaded to the transfer counter.
Writing to register
Registers specified for forward direction transfer are always write enabled.
Registers specified for fixed address transfer are write-enabled when the DMA enable bit is “0”.
Reading the register
Can be read at any time.
However, when the DMA enable bit is “1”, reading the register set up as the
forward register is the same as reading the value of the forward address pointer.
DMA request factors (Note)
Note1: DMA transfer is not effective to any interrupt. DMA transfer is affected neither by the interrupt enable
flag (I flag) nor by the interrupt priority level.
2: No DMA request sources for data slicer 1 are available.
3: The factor which can be chosen changes with channels.
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DMA0 request cause select register
b7
b6
b5
b4
b3
b2
b1
Symbol
DM0SL
b0
Bit symbol
DSEL0
Address
03B8 16
When reset
0016
Function
Bit name
DMA request cause
select bit
DSEL1
DSEL2
DSEL3
b3 b2 b1 b0
0 0 0 0 : Falling edge of INT 0 pin
0 0 0 1 : Software trigger
0 0 1 0 : Timer A0
0 0 1 1 : Timer A1
0 1 0 0 : Timer A2
0 1 0 1 : Timer A3
0 1 1 0 : Timer A4 (DMS = 0)
/two edges of INT 0 pin (DMS=1)
0 1 1 1 : Timer B0 (DMS = 0)
/OSD1 (DMS=1)
1 0 0 0 : Timer B1 (DMS = 0)
/OSD2 (DMS=1)
1 0 0 1 : Timer B2 (DMS = 0)
/Multi-master I 2C-BUS interface 0
(DMS=1)
1 0 1 0 : UART0 transmit
1 0 1 1 : UART0 receive
1 1 0 0 : UART2 transmit
1 1 0 1 : UART2 receive
1 1 1 0 : A-D conversion
1 1 1 1 : Data slicer
Nothing is assigned.
In an attempt to write to these bits, write “0.”
The value, if read, turns out to be “0.”
DMS
DMA request cause
expansion bit
0 : Normal
1 : Expanded cause
DSR
Software DMA
request bit
If software trigger is selected, a
DMA request is generated by
setting this bit to “1” (When read,
the value of this bit is always “0”)
Figure 2.9.2 DMA0 request cause select register
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W
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
DMA1 request cause select register
b7
b6
b5
b4
b3
b2
b1
Symbol
DM1SL
b0
Address
03BA 16
Function
Bit name
Bit symbol
DSEL0
When reset
0016
R
W
b3 b2 b1 b0
DMA request cause
select bit
0 0 0 0 : Falling edge of INT 1 pin
0 0 0 1 : Software trigger
0 0 1 0 : Timer A0
0 0 1 1 : Timer A1
0 1 0 0 : Timer A2
0 1 0 1 : Timer A3 (DMS = 0)
/OSD1 (DMS = 1)
0 1 1 0 : Timer A4 (DMS = 0)
/OSD2 (DMS = 1)
0 1 1 1 : Timer B0
/Multi-master I 2C-BUS interface 1
(DMS = 1)
1 0 0 0 : Timer B1
1 0 0 1 : Timer B2
1 0 1 0 : UART0 transmit
1 0 1 1 : UART0 receive
1 1 0 0 : UART2 transmit
1 1 0 1 : UART2 receive
1 1 1 0 : A-D conversion
1 1 1 1 : V SYNC
DSEL1
DSEL2
DSEL3
Nothing is assigned.
In an attempt to write to these bits, write “0.”
The value, if read, turns out to be “0.”
DMS
DMA request
cause expansion bit
DSR
Software DMA
request bit
0 : Normal
1 : Expanded cause
If software trigger is selected, a
DMA request is generated by
setting this bit to “1” (When read,
the value of this bit is always “0”)
Figure 2.9.3 DMA1 request cause select register
DMAi control register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
DMiCON(i=0,1)
Address
002C16, 003C16
When reset
00000?002
Bit symbol
Bit name
DMBIT
Transfer unit bit select bit
0 : 16 bits
1 : 8 bits
DMASL
Repeat transfer mode
select bit
0 : Single transfer
1 : Repeat transfer
DMAS
DMA request bit (Note 1)
0 : DMA not requested
1 : DMA requested
DMA enable bit
0 : Disabled
1 : Enabled
DSD
Source address direction
select bit (Note 3)
0 : Fixed
1 : Forward
DAD
Destination address
0 : Fixed
direction select bit (Note 3) 1 : Forward
DMAE
Function
R
W
(Note 2)
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0.”
Notes 1: DMA request can be cleared by resetting the bit.
2:This bit can only be set to “0.”
3:Source address direction select bit and destination address direction select bit
cannot be set to “1” simultaneously.
Figure 2.9.4 DMAi control register (i = 0, 1)
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DMAi source pointer (i = 0, 1)
(b23)
b7
(b19)
b3
(b16)(b15)
b0 b7
(b8)
b0 b7
b0
Symbol
SAR0
SAR1
Address
002216 to 0020 16
003216 to 0030 16
When reset
Indeterminate
Indeterminate
Transfer count
specification
Function
• Source pointer
Stores the source address
R W
00000 16 to FFFFF 16
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0.”
Figure 2.9.5 DMAi source pointer (i = 0, 1)
DMAi destination pointer (i = 0, 1)
(b23)
b7
(b19)
b3
(b16) (b15)
b0 b7
(b8)
b0 b7
b0
Symbol
DAR0
DAR1
Address
002616 to 0024 16
003616 to 0034 16
When reset
Indeterminate
Indeterminate
Transfer count
specification
Function
• Destination pointer
Stores the destination address
R W
00000 16 to FFFFF 16
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0.”
Figure 2.9.6 DMAi destination pointer (i = 0, 1)
DMAi transfer counter (i = 0, 1)
(b15)
b7
(b8)
b0 b7
b0
Symbol
TCR0
TCR1
Address
002916, 0028 16
003916, 0038 16
Function
• Transfer counter
Set a value one less than the transfer count
Figure 2.9.7 DMAi transfer counter (i = 0, 1)
Rev.1.00
May 18, 2004
page 74 of 296
When reset
Indeterminate
Indeterminate
Transfer count
specification
0000 16 to FFFF 16
R W
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
2.9.1 Transfer Cycle
The transfer cycle consists of the bus cycle in which data is read from memory or from the SFR area
(source read) and the bus cycle in which the data is written to memory or to the SFR area (destination
write). The number of read and write bus cycles depends on the source and destination addresses. In
memory expansion mode and microprocessor mode, the number of read and write bus cycles also depends on the level of the BYTE pin. Also, the bus cycle itself is longer when software waits are inserted.
(1) Effect of source and destination addresses
When 16-bit data is transferred on a 16-bit data bus, and the source and destination both start at odd
addresses, there are one more source read cycle and destination write cycle than when the source
and destination both start at even addresses.
(2) Effect of BYTE pin level
When transferring 16-bit data over an 8-bit data bus (BYTE pin = “H”) in memory expansion mode and
microprocessor mode, the 16 bits of data are sent in two 8-bit blocks. Therefore, two bus cycles are
required for reading the data and two are required for writing the data. Also, in contrast to when the
CPU accesses internal memory, when the DMAC accesses internal memory (internal ROM, internal
RAM, and SFR), these areas are accessed using the data size selected by the BYTE pin.
(3) Effect of software wait
When the SFR area, the OSD RAM area, or a memory area with a software wait is accessed, the
number of cycles is increased for the wait by 1 bus cycle. The length of the cycle is determined by
BCLK.
Figure 2.9.8 shows the example of the transfer cycles for a source read. For convenience, the destination
write cycle is shown as one cycle and the source read cycles for the different conditions are shown. In
reality, the destination write cycle is subject to the same conditions as the source read cycle, with the
transfer cycle changing accordingly. When calculating the transfer cycle, remember to apply the respective conditions to both the destination write cycle and the source read cycle. For example (2) in Figure 47,
if data is being transferred in 16-bit units on an 8-bit bus, two bus cycles are required for both the source
read cycle and the destination write cycle.
Rev.1.00
May 18, 2004
page 75 of 296
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
(1) 8-bit transfers
16-bit transfers from even address and the source address is even.
BCLK
Address
bus
CPU use
Source
Destination
Dummy
cycle
CPU use
RD signal
WR signal
Data
bus
CPU use
Source
Destination
Dummy
cycle
CPU use
(2) 16-bit transfers and the source address is odd
Transferring 16-bit data on an 8-bit data bus (In this case, there are also two destination write cycles).
BCLK
Address
bus
CPU use
Source
Source + 1 Destination
Dummy
cycle
CPU use
RD signal
WR signal
Data
bus
CPU use
Source + 1 Destination
Source
Dummy
cycle
CPU use
(3) One wait is inserted into the source read under the conditions in (1)
BCLK
Address
bus
CPU use
Source
Destination
Dummy
cycle
CPU use
RD signal
WR signal
Data
bus
CPU use
Source
Destination
Dummy
cycle
CPU use
(4) One wait is inserted into the source read under the conditions in (2)
(When 16-bit data is transferred on an 8-bit data bus, there are two destination write cycles).
BCLK
Address
bus
CPU use
Source
Source + 1
Destination
Dummy
cycle
CPU use
RD signal
WR signal
Data
bus
CPU use
Source
Source + 1
Destination
Dummy
cycle
CPU use
Note: The same timing changes occur with the respective conditions at the destination as at the source.
Figure 2.9.8 Example of the transfer cycles for a source read
Rev.1.00
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M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
2.9.2 DMAC Transfer Cycles
Any combination of even or odd transfer read and write addresses is possible. Table 2.9.2 shows the
number of DMAC transfer cycles.
The number of DMAC transfer cycles can be calculated as follows:
No. of transfer cycles per transfer unit = No. of read cycles ✕ j + No. of write cycles ✕ k
Table 2.9.2 No. of DMAC transfer cycles
Single-chip mode
Transfer unit
8-bit transfers
(DMBIT= “1”)
16-bit transfers
(DMBIT= “0”)
Memory expansion mode
Bus width
Access address
Microprocessor mode
No. of read No. of write No. of read No. of write
cycles
cycles
cycles
cycles
16-bit
Even
1
1
1
1
(BYTE= “L”)
Odd
1
1
1
1
8-bit
Even
—
—
1
1
(BYTE = “H”)
Odd
—
—
1
1
16-bit
Even
1
1
1
1
(BYTE = “L”)
Odd
2
2
2
2
8-bit
Even
—
—
2
2
(BYTE = “H”)
Odd
—
—
2
2
Coefficient j, k
Internal memory
Internal ROM/RAM
SFR area
1
Rev.1.00
May 18, 2004
2
page 77 of 296
External memory
Separate bus Separate bus
/OSD RAM
No wait
With wait
1
2
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
2.9.3 DMA Enable Bit
Setting the DMA enable bit to 1 makes the DMAC active. The DMAC carries out the following operations
at the time data transfer starts immediately after DMAC is turned active.
(1) Reloads the value of one of the source pointer and the destination pointer - the one specified for the
forward direction - to the forward direction address pointer.
(2) Reloads the value of the transfer counter reload register to the transfer counter.
Thus overwriting 1 to the DMA enable bit with the DMAC being active carries out the operations given
above, so the DMAC operates again from the initial state at the instant 1 is overwritten to the DMA
enable bit.
2.9.4 DMA Request Bit
The DMAC can generate a DMA transfer request signal triggered by a factor chosen in advance out of
DMA request factors for each channel.
DMA request factors include the following.
* Factors effected by using the interrupt request signals from the built-in peripheral functions and software
DMA factors (internal factors) effected by a program.
* External factors effected by utilizing the input from external interrupt signals.
For the selection of DMA request factors, see the descriptions of the DMAi factor selection register.
The DMA request bit turns to 1 if the DMA transfer request signal occurs regardless of the DMAC’s state
(regardless of whether the DMA enable bit is set 1 or to 0). It turns to 0 immediately before data transfer
starts.
In addition, it can be set to 0 by use of a program, but cannot be set to 1.
There can be instances in which a change in DMA request factor selection bit causes the DMA request bit
to turn to 1. So be sure to set the DMA request bit to 0 after the DMA request factor selection bit is
changed.
The DMA request bit turns to 1 if a DMA transfer request signal occurs, and turns to 0 immediately before
data transfer starts. If the DMAC is active, data transfer starts immediately, so the value of the DMA
request bit, if read by use of a program, turns out to be 0 in most cases. To examine whether the DMAC
is active, read the DMA enable bit.
Here follows the timing of changes in the DMA request bit.
(1) Internal factors
Except the DMA request factors triggered by software, the timing for the DMA request bit to turn to 1
due to an internal factor is the same as the timing for the interrupt request bit of the interrupt control
register to turn to 1 due to several factors.
Turning the DMA request bit to 1 due to an internal factor is timed to be effected immediately before
the transfer starts.
(2) External factors
_______
An external factor is a factor caused to occur by the leading edge of input from the INTi pin (i depends
on which DMAC channel is used).
_______
Selecting the INTi pins as external factors using the DMA request factor selection bit causes input
from these pins to become the DMA transfer request sig=ls.
Rev.1.00
May 18, 2004
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M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
The timing for the DMA request bit to turn to 1 when an external factor is selected synchronizes with
the signal’s edge applicable to the function specified by the DMA request factor selection bit (synchro_______
nizes with the trailing edge of the input signal to each INTi pin, for example).
With an external factor selected, the DMA request bit is timed to turn to 0 immediately before data
transfer starts similarly to the state in which an internal factor is selected.
(3) The priorities of channels and DMA transfer timing
If a DMA transfer request signal falls on a single sampling cycle (a sampling cycle means one period
from the leading edge to the trailing edge of BCLK), the DMA request bits of applicable channels
concurrently turn to 1. If the channels are active at that moment, DMA0 is given a high priority to start
data transfer. When DMA0 finishes data transfer, it gives the bus right to the CPU. When the CPU
finishes single bus access, then DMA1 starts data transfer and gives the bus right to the CPU. Figure
2.9.9 illustrates these operations.
An example in which DMA transfer is carried out in minimum cycles at the time when DMA transfer
request signals due to external factors concurrently occur.
An example in which DMA transmission is carried out in minimum
cycles at the time when DMA transmission request signals due to
external factors concurrently occur.
BCLK
DMA0
DMA1
CPU
INT0
AAAA
AAAA AAAA
AAAAAA AAA AAAAAA
AA
AAAAAA AAA AAAAAA
AA
Obtainm
ent of the
bus right
DMA0
request bit
INT1
DMA1
request bit
Figure 2.9.9 An example of DMA transfer effected by external factors
Rev.1.00
May 18, 2004
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M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
2.10 Timer
There are eight 16-bit timers. These timers can be classified by function into timers A (five) and timers B
(three). All these timers function independently. Figures 2.10.1 and 2.10.2 show the block diagram of
timers.
Clock prescaler
f1
XIN
f8
1/8
1/4
f32
1/32
XCIN
Clock prescaler reset flag (bit 7
at address 038116) set to “1”
fC32
Reset
f1 f8 f32 fC32
• Timer mode
• One-shot mode
Timer A0 interrupt
Timer A0
• Event counter mode
• Timer mode
• One-shot mode
Timer A1 interrupt
Timer A1
• Event counter mode
• Timer mode
• One-shot mode
• PWM mode
Timer A2 interrupt
Timer A2
• Event counter mode
• Timer mode
• One-shot mode
• PWM mode
Timer A3 interrupt
Timer A3
• Event counter mode
• Timer mode
• One-shot mode
Timer A4 interrupt
Timer A4
• Event counter mode
Timer B2 overflow
Figure 2.10.1 Timer A block diagram
Rev.1.00
May 18, 2004
page 80 of 296
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
Clock prescaler
f1
XIN
f8
1/8
1/4
f32
1/32
XCIN
Clock prescaler reset flag (bit 7
at address 038116) set to “1”
fC32
Reset
f1 f8 f32 fC32
Timer A
• Timer mode
• Pulse period/pulse width measuring mode
TB0IN
Timer B0 interrupt
Noise
filter
Timer B0
• Event counter mode
• Timer mode
• Pulse period/pulse width measuring mode
TB1IN
Noise
filter
Timer B1 interrupt
Timer B1
• Event counter mode
• Timer mode
• Pulse period/pulse width measuring mode
TB2IN
Noise
filter
Timer B2
• Event counter mode
Figure 2.10.2 Timer B block diagram
Rev.1.00
May 18, 2004
page 81 of 296
Timer B2 interrupt
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
2.10.1 Timer A
Figure 2.10.3 shows the block diagram of timer A. Figures 2.10.4 to 2.10.10 show the timer A-related
registers.
Except the pulse output function, timers A0 through A4 all have the same function. Use the timer Ai mode
register (i = 0 to 4) bits 0 and 1 to choose the desired mode.
Timer A has the four operation modes listed as follows:
• Timer mode: The timer counts an internal count source.
• Event counter mode: The timer counts a timer over flow.
• One-shot timer mode: The timer stops counting when the count reaches “000016”.
• Pulse width modulation (PWM) mode: The timer outputs pulses of a given width.
Data bus high-order bits
Clock source
selection
Data bus low-order bits
• Timer
• One shot
• PWM
f1
f8
f32
High-order
8 bits
Low-order
8 bits
Reload register (16)
fC32
• Event counter
Counter (16)
Up count/down count
Always down count except
in event counter mode
Count start flag
(Address 038016)
• Clock selection
TAi
Timer A0
Timer A1
Timer A2
Timer A3
Timer A4
Down count
TB2 overflow
External
trigger
TAj overflow
(j = i – 1. Note, however, that j = 4 when i = 0)
Up/down flag
(Address 038416)
Addresses
TA
j
038716 038616
Timer A4
038916 038816
Timer A0
038B16 038A16
Timer A1
038D16 038C16 Timer A2
038F16 038E16
Timer A3
TAk
Timer A1
Timer A2
Timer A3
Timer A4
Timer A0
TAk overflow
(k = i + 1. Note, however, that k = 0 when i = 4)
Pulse output
TAiOUT
(i = 2, 3)
Toggle flip-flop
Figure 2.10.3 Block diagram of timer A
Timer Ai mode register
b7
b6
b5
b4
b3
b2
b1
Symbol
TAiMR(i=0 to 4)
b0
Bit symbol
TMOD0
Address
When reset
039616 to 039A 16
0016
Bit name
Operation mode select bit
TMOD1
MR0
MR1
0 0 : Timer mode
0 1 : Event counter mode
1 0 : One-shot timer mode
1 1 : Pulse width modulation
(PWM) mode
Function varies with each operation mode
MR2
MR3
TCK0
TCK1
Count source select bit
(Function varies with each operation mode)
Note: Only timers 2 and 3 have PWM mode.
Figure 2.10.4 Timer Ai mode register (i = 0 to 4)
Rev.1.00
May 18, 2004
page 82 of 296
R W
Function
b1 b0
(Note)
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
Timer Ai register (Note)
(b15)
b7
(b8)
b0 b7
Symbol
TA0
TA1
TA2
TA3
TA4
b0
Address
0387 16, 0386 16
0389 16, 0388 16
038B16, 038A16
038D16, 038C16
038F16, 038E16
Function
When reset
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Values that can be set
• Timer mode
Counts an internal count source
000016 to FFFF16
• Event counter mode
Counts pulses from an timer overflow
000016 to FFFF16
• One-shot timer mode
Counts a one shot width
000016 to FFFF16
• Pulse width modulation mode (16-bit PWM) (TA2, TA3)
Function as a 16-bit pulse width modulator
000016 to FFFE16
• Pulse width modulation mode (8-bit PWM) (TA2, TA3)
Timer low-order address functions as an 8-bit
prescaler and high-order address functions as an 8-bit
pulse width modulator
0016 to FE16
(Both high-order
and low-order
addresses)
R W
Note: Read and write data in 16-bit units.
Figure 2.10.5 Timer Ai register (i = 0 to 4)
Count start flag
b7
b6
b5
b4
b3
b2
b1
Symbol
TABSR
b0
Bit symbol
May 18, 2004
Bit name
TA0S
Timer A0 count start flag
TA1S
Timer A1 count start flag
TA2S
Timer A2 count start flag
TA3S
Timer A3 count start flag
TA4S
Timer A4 count start flag
TB0S
Timer B0 count start flag
TB1S
Timer B1 count start flag
TB2S
Timer B2 count start flag
Figure 2.10.6 Count start flag
Rev.1.00
Address
0380 16
page 83 of 296
When reset
0016
Function
0 : Stops counting
1 : Starts counting
R W
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
Up/down flag
b7
b6
b5
b4
b3
b2
b1
Symbol
UDF
b0
0 0 0
Address
0384 16
Bit symbol
When reset
0016
Bit name
TA0UD
Timer A0 up/down flag
TA1UD
Timer A1 up/down flag
TA2UD
Timer A2 up/down flag
TA3UD
Timer A3 up/down flag
TA4UD
Timer A4 up/down flag
Function
R W
0 : Down count
1 : Up count
This specification becomes valid
when the up/down flag content is
selected for up/down switching
cause
Must always be set to “0”
Reserved bit
Figure 2.10.7 Up/down flag
One-shot start flag
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
ONSF
Address
0382 16
When reset
00X00000 2
0
Bit symbol
Bit name
TA0OS
Timer A0 one-shot start flag
TA1OS
Timer A1 one-shot start flag
TA2OS
Timer A2 one-shot start flag
TA3OS
Timer A3 one-shot start flag
TA4OS
Timer A4 one-shot start flag
Reserved bit
TA0TGL
TA0TGH
Figure 2.10.8 One-shot start flag
Rev.1.00
May 18, 2004
page 84 of 296
Timer A0 event/trigger
select bit
Function
1 : Timer start
When read, the value is “0”
Must always be set to “0”
b7 b6
0 0 : Do not set
0 1 : TB2 overflow is selected
1 0 : TA4 overflow is selected
1 1 : TA1 overflow is selected
R W
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
Trigger select register
b7
b6
b5
b4
b3
b2
b1
Symbol
TRGSR
b0
Address
0383 16
Bit symbol
TA1TGL
Bit name
Timer A1 event/trigger
select bit
Timer A2 event/trigger
select bit
b3 b2
Timer A3 event/trigger
select bit
b5 b4
Timer A4 event/trigger
select bit
b7 b6
TA2TGH
TA3TGL
TA3TGH
TA4TGL
Function
b1 b0
TA1TGH
TA2TGL
When reset
0016
TA4TGH
R W
0 0 : Do not set
0 1 : TB2 overflow is selected
1 0 : TA0 overflow is selected
1 1 : TA2 overflow is selected
0 0 : Do not set
0 1 : TB2 overflow is selected
1 0 : TA1 overflow is selected
1 1 : TA3 overflow is selected
0 0 : Do not set
0 1 : TB2 overflow is selected
1 0 : TA2 overflow is selected
1 1 : TA4 overflow is selected
0 0 : Do not set
0 1 : TB2 overflow is selected
1 0 : TA3 overflow is selected
1 1 : TA0 overflow is selected
Figure 2.10.9 Trigger select register
Clock prescaler reset flag
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
CPSRF
Address
038116
Bit symbol
Bit name
When reset
0XXXXXXX 2
Function
Nothing is assigned.
In an attempt to write to these bits, write “0.” The value, if read, turns out to be indeterminate.
CPSR
Clock prescaler reset flag
Figure 2.10.10 Clock prescaler reset flag
Rev.1.00
May 18, 2004
page 85 of 296
0 : No effect
1 : Prescaler is reset
(When read, the value is “0”)
RW
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
(1) Timer mode
In this mode, the timer counts an internally generated count source. (See Table 2.10.1.) Figure 2.10.11
shows the timer Ai mode register in timer mode.
Table 2.10.1 Specifications of timer mode
Item
Specification
Count source
f1, f8, f32, fc32
Count operation
• Down count
• When the timer underflows, it reloads the reload register contents before continuing counting
Divide ratio
1/(n+1)
Count start condition
Count start flag is set (= 1)
n : Set value
Count stop condition
Count start flag is reset (= 0)
Interrupt request generation timing
When the timer underflows
TA2OUT/TA3OUT pin function
Programmable I/O port or pulse output
Read from timer
Count value can be read out by reading timer Ai register
Write to timer
• When counting stopped
When a value is written to timer Ai register, it is written to both reload register and counter
• When counting in progress
When a value is written to timer Ai register, it is written to only reload register
(Transferred to counter at next reload time)
Select function
• Pulse output function
Each time the timer underflows, the TAiOUT pin’s polarity is reversed
Timer Ai mode register
b7
b6
b5
b4
b3
0 0 0
b2
b1
b0
0 0
Symbol
TAiMR(i=0 to 4)
Bit symbol
TMOD0
TMOD1
MR0
Address
0396 16 to 039A 16
When reset
0016
Bit name
Operation mode
select bit
Pulse output function
select bit
(Note 2)
Function
0 0 : Timer mode
0 : Pulse is not output
(TA2OUT/TA3OUT pin is a normal port pin)
1 : Pulse is output (Note 1)
(TA2OUT/TA3OUT pin is a pulse output pin)
Must always be set to “0”
Reserved bits
MR3
0 (Must always be set to “0” in timer mode)
TCK0
Count source select bit
TCK1
R W
b1 b0
b7 b6
0 0 : f1
0 1 : f8
1 0 : f 32
1 1 : f C32
Notes 1 : The settings of the corresponding port register and port direction register
are invalid.
This bit of TAiMR (i = 0, 1, 4) must always be set to “0.”
Figure 2.10.11 Timer Ai mode register in timer mode (i = 0 to 4)
Rev.1.00
May 18, 2004
page 86 of 296
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
(2) Event counter mode
In this mode, the timer counts an internal timer’s overflow.
Table 2.10.2 Timer specifications in event counter mode
Item
Specification
Count source
Count operation
Divide ratio
Count start condition
Count stop condition
Interrupt request generation timing
TA2OUT/TA3OUT pin function
Read from timer
Write to timer
Select function
• TB2 overflow, TAj overflow, TAk overflow
• Up count or down count can be selected by external signal or software
• When the timer overflows or underflows, it reloads the reload register contents
before continuing counting (Note)
1/ (FFFF16 - n + 1) for up count
1/ (n + 1) for down count
n : Set value
Count start flag is set (= 1)
Count start flag is reset (= 0)
The timer overflows or underflows
Programmable I/O port, pulse output, or up/down count select input
Count value can be read out by reading timer Ai register
• When counting stopped
When a value is written to timer Ai register, it is written to both reload register and counter
• When counting in progress
When a value is written to timer Ai register, it is written to only reload register
(Transferred to counter at next reload time)
• Free-run count function
Even when the timer overflows or underflows, the reload register content is not reloaded to it
• Pulse output function
Each time the timer overflows or underflows, the TAiOUT pin’s polarity is reversed
Note: This does not apply when the free-run function is selected.
Rev.1.00
May 18, 2004
page 87 of 296
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
Timer Ai mode register
b7
0
b6
b5
0
b4
b3
0
b2
b1
b0
0 1
Symbol
TAiMR(i = 0 to 4)
Bit symbol
TMOD0
Address
When reset
0016
039616 to 039A16
Bit name
Operation mode select bit
Pulse output function
select bit
0 : Pulse is not output
(TA2OUT/TA3OUT pin is a normal port pin)
1 : Pulse is output (Note 2)
(TA2OUT/TA3OUT pin is a pulse output pin)
TMOD1
M R0
Function
b1 b0
Reserved bit
0 1 : Event counter mode (Note 1)
Must always be set to “0”
M R2
Up/down switching
cause select bit
M R3
0 : (Must always be set to “0” in event counter mode)
TCK0
Count operation type select 0 : Reload type
bit
1 : Free-run type
Reserved bit
R W
0 : Up/down flag’s content
1 : TA2OUT/TA3OUT pin’s input signal
(Notes 3, 4)
Must always be set to “0”
Notes 1: In event counter mode, the count source is selected by the event / trigger
select bit (addresses 038216 and 038316).
2: The settings of the corresponding port register and port direction register
are invalid.
3: This bit of TAiMR (i = 0, 1, 4) must always be set to “0.”
4: When an “L” signal is input to the input signal from TA2OUT/TA3OUT pin,
the downcount is activated. When “H,” the upcount is activated. Set the
corresponding port direction register to “0.”
Figure 2.10.12 Timer Ai mode register in event counter mode (i = 0 to 4)
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(3) One-shot timer mode
In this mode, the timer operates only once. (See Table 2.10.3.) When a trigger occurs, the timer starts up
and continues operating for a given period. Figure 2.10.13 shows the timer Ai mode register in one-shot
timer mode.
Table 2.10.3 Timer specifications in one-shot timer mode
Item
Specification
Count source
f1, f8, f32, fC32
Count operation
• The timer counts down
• When the count reaches 000016, the timer stops counting after reloading a new count
• If a trigger occurs when counting, the timer reloads a new count and restarts counting
Divide ratio
1/n
n : Set value
Count start condition
• The timer overflows
• The one-shot start flag is set (= 1)
Count stop condition
• A new count is reloaded after the count has reached 000016
• The count start flag is reset (= 0)
Interrupt request generation timing The count reaches 000016
TA2OUT/TA3OUT pin function Programmable I/O port or pulse output
Read from timer
When timer Ai register is read, it indicates an indeterminate value
Write to timer
• When counting stopped
When a value is written to timer Ai register, it is written to both reload register and
counter
• When counting in progress
When a value is written to timer Ai register, it is written to only reload register
(Transferred to counter at next reload time)
Timer Ai mode register
b7
b6
b5
b4
0
b3
0
b2
b1
b0
1 0
Symbol
TAiMR(i = 0 to 4)
Bit symbol
TMOD0
Address
When reset
0396 16 to 039A 16
0016
Bit name
Operation mode select bit
Pulse output function
select bit
(Note 2)
0 : Pulse is not output
(TA2OUT/TA3OUT pin is a normal port pin)
1 : Pulse is output (Note 1)
(TA2OUT/TA3OUT pin is a pulse output pin)
TMOD1
MR0
Function
b1 b0
Reserved bits
1 0 : One-shot timer mode
Must always be set to “0”
MR2
Trigger select bit
MR3
0 (Must always be “0” in one-shot timer mode)
TCK0
Count source select bit
TCK1
0 : Count start flag is valid
1 : Selected by event/trigger select register
b7 b6
0 0 : f1
0 1 : f8
1 0 : f 32
1 1 : f C32
Notes 1 : The settings of the corresponding port register and port direction register
are invalid.
2 : This bit of TAiMR (i = 0, 1, 4) must always be set to “0.”
Figure 2.10.13 Timer Ai mode register in one-shot timer mode (i = 0 to 4)
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(4) Pulse width modulation (PWM) mode
In this mode, the timer outputs pulses of a given width in succession. (See Table 2.10.4.) In this mode, the
counter functions as either a 16-bit pulse width modulator or an 8-bit pulse width modulator. Figure 2.10.14
shows the timer Ai mode register in pulse width modulation mode. Figure 2.10.15 shows the example of how
an 8-bit pulse width modulator operates.
Table 2.10.4 Timer specifications in pulse width modulation mode
Item
Specification
Count source
Count operation
f1, f8, f32, fC32
• The timer counts down (operating as an 8-bit or a 16-bit pulse width modulator)
• The timer reloads a new count at a rising edge of PWM pulse and continues counting
• The timer is not affected by a trigger that occurs when counting
16-bit PWM
• High level width n / fi n : Set value
• Cycle time
(216-1) / fi fixed
8-bit PWM
• High level width n ✕ (m+1) / fi n : values set to timer Ai register’s high-order address
• Cycle time
(28-1) ✕ (m+1) / fi
m : values set to timer Ai register’s low-order address
Count start condition
• The timer overflows
• The count start flag is set (= 1)
Count stop condition
• The count start flag is reset (= 0)
Interrupt request generation timing PWM pulse goes “L”
TA2OUT/TA3OUT pin function Pulse output
Read from timer
When timer Ai register is read, it indicates an indeterminate value
Write to timer
• When counting stopped
When a value is written to timer Ai register, it is written to both reload register and
counter
• When counting in progress
When a value is written to timer Ai register, it is written to only reload register
(Transferred to counter at next reload time)
Timer Ai mode register
b7
b6
b5
b4
b3
b1
b0
0 1 1
b2
1
Symbol
TAiMR(i=2 and 3)
Bit symbol
TMOD0
TMOD1
MR0
Address
When reset
0398 16 and 0399 16 0016
Bit name
Operation mode
select bit
Function
R W
b1 b0
1 1 : PWM mode
1 (Must always be “1” in PWM mode)
Reserved bits
Must always be set to “0”
MR2
Trigger select bit
0: Count start flag is valid
1: Selected by event/trigger select register
MR3
16/8-bit PWM mode
select bit
0: Functions as a 16-bit pulse width modulator
1: Functions as an 8-bit pulse width modulator
TCK0
Count source select bit
0 0 : f1
0 1 : f8
1 0 : f32
1 1 : fC32
b7 b6
TCK1
Figure 2.10.14 Timer Ai mode register in pulse width modulation mode (i = 2 and 3)
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Condition : Reload register high-order 8 bits = 0216
Reload register low-order 8 bits = 0216
Timer overflow is selected
8
1 / fi X (m + 1) X (2 – 1)
Count source (Note1)
“H”
Timer overflow
“L”
1 / fi X (m + 1)
“H”
Underflow signal of
8-bit prescaler (Note2) “L”
1 / fi X (m + 1) X n
PWM pulse output
from TAiOUT pin
“H”
Timer Ai interrupt
request bit
“1”
“L”
“0”
fi : Frequency of count source
(f1, f8, f32, fC32)
Cleared to “0” when interrupt request is accepted, or cleared by software
Notes 1: The 8-bit prescaler counts the count source.
2: The 8-bit pulse width modulator counts the 8-bit prescaler's underflow signal.
3: m = 0016 to FE16; n = 0016 to FE16.
Figure 2.10.15 Example of how an 8-bit pulse width modulator operates
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2.10.2 Timer B
Figure 2.10.16 shows the block diagram of timer B. Figures 2.10.17 and 2.10.18 show the timer B-related
registers.
Use the timer Bi mode register (i = 0 to 2) bits 0 and 1 to choose the desired mode.
Timer B has three operation modes listed as follows:
• Timer mode: The timer counts an internal count source.
• Event counter mode: The timer counts pulses from an external source or a timer overflow.
• Pulse period/pulse width measuring mode: The timer measures an external signal’s pulse period or
pulse width.
Data bus high-order bits
Data bus low-order bits
Clock source selection
High-order 8 bits
Low-order 8 bits
f1
• Timer
• Pulse period/pulse width measurement
f8
f32
fC32
Reload register (16)
Counter (16)
• Event counter
Count start flag
Polarity switching
and edge pulse
TBiIN
(i = 0 to 2)
(address 0380 16)
Counter reset circuit
Can be selected in only
event counter mode
TBi
Timer B0
Timer B1
Timer B2
TBj overflow
(j = i – 1.
Note, however,
j = 2 when i = 0)
Address
0391 16 0390 16
0393 16 0392 16
0395 16 0394 16
TBj
Timer B2
Timer B0
Timer B1
Figure 2.10.16 Block diagram of timer B
Timer Bi mode register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
Address
TBiMR(i = 0 to 2) 039B16 to 039D 16
Bit symbol
Bit name
TMOD0
Operation mode select bit
TMOD1
MR0
When reset
00?X0000 2
Function
R
b1 b0
0 0 : Timer mode
0 1 : Event counter mode
1 0 : Pulse period/pulse width
measurement mode
1 1 : Inhibited
Function varies with each operation mode
MR1
MR2
(Note 1)
(Note 2)
MR3
TCK0
TCK1
Count source select bit
(Function varies with each operation mode)
Notes 1: Timer B0.
2: Timer B1, timer B2.
Figure 2.10.17 Timer Bi mode register (i = 0 to 2)
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Timer Bi register (Note)
(b15)
b7
(b8)
b0 b7
b0
Symbol
TB0
TB1
TB2
Address
039116, 0390 16
039316, 0392 16
039516, 0394 16
Function
When reset
Indeterminate
Indeterminate
Indeterminate
R W
Values that can be set
• Timer mode
Counts the timer's period
000016 to FFFF 16
• Event counter mode
Counts external pulses input or a timer overflow
000016 to FFFF 16
• Pulse period / pulse width measurement mode
Measures a pulse period or width
Note: Read and write data in 16-bit units.
Figure 2.10.18 Timer Bi register (i = 0 to 2)
Count start flag
b7
b6
b5
b4
b3
b2
b1
Symbol
TABSR
b0
Bit symbol
Address
038016
When reset
0016
Bit name
TA0S
Timer A0 count start flag
TA1S
Timer A1 count start flag
TA2S
Timer A2 count start flag
TA3S
Timer A3 count start flag
TA4S
Timer A4 count start flag
TB0S
Timer B0 count start flag
TB1S
Timer B1 count start flag
TB2S
Timer B2 count start flag
Function
R W
0 : Stops counting
1 : Starts counting
Figure 2.10.19 Count start flag
Clock prescaler reset flag
b7
b6
b5
b4
b3
b2
b1
Symbol
CPSRF
b0
Address
038116
Bit symbol
When reset
0XXXXXXX 2
Bit name
Function
Nothing is assigned.
In an attempt to write to these bits, write “0.”
The value, if read, turns out to be indeterminate.
CPSR
Clock prescaler reset flag
Figure 2.10.20 Clock prescaler reset flag
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0 : No effect
1 : Prescaler is reset
(When read, the value is “0”)
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(1) Timer mode
In this mode, the timer counts an internally generated count source. (See Table 2.10.5) Figure 2.10.21
shows the timer Bi mode register in timer mode.
Table 2.10.5 Timer specifications in timer mode
Item
Specification
Count source
f1, f8, f32, fC32
Count operation
• Counts down
• When the timer underflows, it reloads the reload register contents before continuing
counting
Divide ratio
1/(n+1)
n : Set value
Count start condition
Count start flag is set (= 1)
Count stop condition
Count start flag is reset (= 0)
Interrupt request generation timing The timer underflows
TBiIN pin function
Programmable I/O port
Read from timer
Count value is read out by reading timer Bi register
Write to timer
• When counting stopped
When a value is written to timer Bi register, it is written to both reload register and counter
• When counting in progress
When a value is written to timer Bi register, it is written to only reload register
(Transferred to counter at next reload time)
AA
A
AAA
Timer Bi mode register
b7
b6
b5
b4
b3
0
b2
b1
b0
0 0
Symbol
TBiMR(i=0 to 2)
Bit symbol
TMOD0
Address
039B16 to 039D16
Bit name
Operation mode select bit
TMOD1
MR0
When reset
00?X00002
Function
b1 b0
0 0 : Timer mode
MR1
Invalid in timer mode
Can be “0” or “1”
MR2
0 (Fixed to “0” in timer mode ; i = 0)
AAAA
AA
A
AA
A
AA
AA
A
A
AAAA
AA
AAAA
AA
AA
AAAA
R
(Note 1)
Nothing is assigned (i = 1, 2).
In an attempt to write to this bit, write “0.” The value, if read, turns out to (Note 2)
be indeterminate.
Invalid in timer mode.
In an attempt to write to this bit, write “0.” The value, if read in
timer mode, turns out to be indeterminate.
b7 b6
Count source select bit
TCK0
0 0 : f1
0 1 : f8
TCK1
1 0 : f32
1 1 : fC32
Notes 1: Timer B0.
2: Timer B1, timer B2.
MR3
Figure 2.10.21 Timer Bi mode register in timer mode (i = 0 to 2)
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(2) Event counter mode
In this mode, the timer counts an external signal or an internal timer’s overflow. (See Table 2.10.6) Figure
2.10.22 shows the timer Bi mode register in event counter mode.
Table 2.10.6 Timer specifications in event counter mode
Item
Specification
Count source
• External signals input to TBiIN pin
• Effective edge of count source can be a rising edge, a falling edge, or falling and
rising edges as selected by software
• TBj overflow
Count operation
• Counts down
• When the timer underflows, it reloads the reload register contents before continuing
counting
Divide ratio
1/(n+1)
Count start condition
Count start flag is set (= 1)
n : Set value
Count stop condition
Count start flag is reset (= 0)
Interrupt request generation timing The timer underflows
TBiIN pin function
Count source input
Read from timer
Count value can be read out by reading timer Bi register
Write to timer
• When counting stopped
When a value is written to timer Bi register, it is written to both reload register and counter
• When counting in progress
When a value is written to timer Bi register, it is written to only reload register
(Transferred to counter at next reload time)
AA
AA
Timer Bi mode register
b7
b6
b5
b4
b3
0
b2
b1
b0
0
1
Symbol
TBiMR(i=0 to 2)
Address
039B16 to 039D16
When reset
00?X00002
Bit symbol
Bit name
TMOD0
Operation mode select bit
b1 b0
Count polarity select
bit (Note 1)
b3 b2
0 1 : Event counter mode
TMOD1
MR0
MR1
MR2
0 0 : Counts external signal's falling
edges
0 1 : Counts external signal's rising
edges
1 0 : Counts external signal's falling
and rising edges
1 1 : Inhibited
0 (Fixed to “0” in event counter mode; i = 0)
AA
AA
AA
AA
AA
A
A
A
A
A
AA
R
Function
(Note 2)
Nothing is assigned (i = 1, 2).
In an attempt to write to this bit, write “0.” The value, if read, turns out to
(Note 3)
be indeterminate.
MR3
Invalid in timer mode.
In an attempt to write to this bit, write “0.” The value, if read in
event counter mode, turns out to be indeterminate.
TCK0
Invalid in event counter mode.
Can be “0” or “1”.
TCK1
Event clock select
0 : Input from TBiIN pin (Note 4)
1 : TBj overflow
(j = i – 1; however, j = 2 when i = 0)
Notes 1: Valid only when input from the TBiIN pin is selected as the event clock.
If timer's overflow is selected, this bit can be “0” or “1”.
2: Timer B0.
3: Timer B1, timer B2.
Figure 2.10.22 Timer Bi mode register in event counter mode (i = 0 to 2)
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(3) Pulse period/pulse width measurement mode
In this mode, the timer measures the pulse period or pulse width of an external signal. (See Table 2.10.7)
Figure 2.10.23 shows the timer Bi mode register in pulse period/pulse width measurement mode. Figure
2.10.24 shows the operation timing when measuring a pulse period. Figure 2.10.25 shows the operation
timing when measuring a pulse width.
Table 2.10.7 Timer specifications in pulse period/pulse width measurement mode
Item
Specification
Count source
f1, f8, f32, fc32
Count operation
• Up count
• Counter value “000016” is transferred to reload register at measurement pulse's
effective edge and the timer continues counting
Count start condition
Count start flag is set (= 1)
Count stop condition
Count start flag is reset (= 0)
Interrupt request generation timing • When measurement pulse's effective edge is input (Note 1)
• When an overflow occurs. (Simultaneously, the timer Bi overflow flag changes to “1”.
The timer Bi overflow flag changes to “0” when the count start flag is “1” and value is
written to the timer Bi mode register after the count timinng of the next count source.
TBiIN pin function
Measurement pulse input
Read from timer
When timer Bi register is read, it indicates the reload register’s content
Write to timer
Cannot be written to
(measurement result) (Note 2)
Notes 1: An interrupt request is not generated when the first effective edge is input after the timer has started counting.
2: The value read out from the timer Bi register is indeterminate until the second effective edge is input after the timer.
Timer Bi mode register
b7
b6
b5
b4
b3
0
b2
b1
b0
1 0
Symbol
TBiMR(i=0 to 2)
Bit symbol
TMOD0
TMOD1
MR0
Address
039B16 to 039D16
Bit name
Operation mode
select bit
Measurement mode
select bit
MR1
MR2
When reset
00?X00002
Function
R
W
b1 b0
1 0 : Pulse period / pulse width
measurement mode
b3 b2
0 0 : Pulse period measurement (Interval between
measurement pulse's falling edge to falling edge)
0 1 : Pulse period measurement (Interval between
measurement pulse's rising edge to rising edge)
1 0 : Pulse width measurement (Interval between
measurement pulse's falling edge to rising edge,
and between rising edge to falling edge)
1 1 : Inhibited
0 (Fixed to “0” in pulse period/pulse width measurement mode; i = 0)
(Note 2)
Nothing is assigned (i = 1, 2).
In an attempt to write to this bit, write “0.” The value, if read, turns out to be
indeterminate.
MR3
Timer Bi overflow
flag ( Note 1)
TCK0
Count source
select bit
(Note 3)
0 : Timer did not overflow
1 : Timer has overflowed
b7 b6
0 0 : f1
0 1 : f8
1 0 : f 32
TCK1
1 1 : f C32
Notes 1: The timer Bi overflow flag changes to “0” when the count start flag is “1” and a value is written to the
timer Bi mode register. This flag cannot be set to “1” by software.
2: Timer B0.
3: Timer B1, timer B2.
Figure 2.10.23 Timer Bi mode register in pulse period/pulse width measurement mode (i = 0 to 2)
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When measuring measurement pulse time interval from falling edge to falling edge
Count source
“H”
Measurement pulse
Reload register
transfer timing
“L”
Transfer
(indeterminate value)
Transfer
(indeterminate value)
counter
(Note 1)
(Note 1)
(Note 2)
Timing at which counter
reaches "000016"
“1”
Count start flag
“0”
Timer Bi interrupt
request bit
“1”
“0”
Cleared to “0” when interrupt request is accepted, or cleared by software.
“1”
Timer Bi overflow flag
“0”
Notes 1: Counter is initialized at completion of measurement.
2: Timer has overflowed.
Figure 2.10.24 Operation timing when measuring a pulse period
Count source
“H”
Measurement pulse
Reload register
transfer timing
“L”
Transfer
(indeterminate
value)
Transfer
(measured value)
Transfer
(measured
value)
Transfer
(measured value)
counter
(Note 1)
(Note 1)
(Note 1) (Note 1)
(Note 2)
Timing at which counter
reaches "000016"
Count start flag
“1”
“0”
Timer Bi interrupt
request bit
“1”
“0”
Cleared to “0” when interrupt request is accepted, or cleared by software.
Timer Bi overflow flag
“1”
“0”
Notes 1: Counter is initialized at completion of measurement.
2: Timer has overflowed.
Figure 2.10.25 Operation timing when measuring a pulse width
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Reserved register
b7
b6
b5
b4
b3
b2
0
0
0
0
0
0 0
b1
b0
0
Symbol
RUS2S4
RUS2S3
RUS2S2
RUS0S4
RUS0S3
RUS0S2
RUS0S1
Bit symbol
Address
0374
0375
0376
03AC
03AD
03AE
03AF
When reset
000000002
000000002
000000002
000000002
000000002
000000002
000000002
Bit name
Reserved bits
R
Description
W
Must always be set to “0”
Reserved register
b7
b6
b5
b4
b3
b2
b1
b0
0 0 0 0 0 0 0 0
Symbol
ROT1
Bit symbol
Address
029E 16
Bit name
When reset
XXXXXXX02
Function
Reserved bit
Must always be set to “0”
Reserved bits
Must always be set to “0”
R
W
✕
Reserved register
b7
b6
b5
b4
b3
b2
0
b1
b0
0
Symbol
ROT2
Bit symbol
Reserved bit
Address
029F 16
Bit name
When reset
XXX0XXX02
Function
Must always be set to “0”
R
✕
Nothing is assigned.
In an attempt to write to this bit, write “0.” The value, if read, turns out to be
indeterminate.
Reserved bit
Must always be set to “0”
Nothing is assigned.
In an attempt to write to this bit, write “0.” The value, if read, turns out to be
indeterminate.
Figure 2.10.26 Reserved register
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(4) TB0IN noise filter
The input signal of pin TB0IN has the noise filter. The ON/OFF of noise filter and selection of filter clock
are set by bits 2 to 4 of the peripheral mode register.
Note: When using the noise filter, set bit 7 of the peripheral mode register according to the main clock
frequency.
b7
b6
b5
b4
b3
0 0
b2
b1
b0
Symbol
PM
Address
027D16
Bit symbol
BSEL0
Bit name
I2C-BUS interface port
selection bit
BSEL1
WSEL0
When reset
0016
TB0IN pin noise filter clock
selection bit
Function
b1 b0
00:
0 1 : SCL1, SDA1
1 0 : SCL2, SDA2
1 1 : SCL1 and SDA1, SCL2 and SDA2
b3 b2
0 0 : 0.25ms
(The removable maximum bus width = 1ms)
0 1 : 8ms
(The removable maximum bus width = 32ms)
1 0 : 16ms
(The removable maximum bus width = 64ms)
1 1 : 32ms
WSEL1
NFON
(The removable maximum bus width = 128ms)
TB0IN pin noise filter ON/OFF
selection bit
Must always be set to “0”
Reserved bit
SSCK
Main clock frequency
selection bit
Figure 2.10.27 Peripheral mode register
Rev.1.00
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page 99 of 296
0 : Noise filter OFF
1 : Noise filter ON
0 : f(XIN)=10MHz
1 : f(XIN)=16MHz
R
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M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
2.11 Serial I/O
Serial I/O is configured as 4 unites: UART0, UART2, multi-master I2C-BUS interface 0, and multi-master
I2C-BUS interface 1.
2.11.1 UART0 and UART2
UART0 and UART2 each have an exclusive timer to generate a transfer clock, so they operate independently of each other.
Figure 2.11.1 shows the block diagram of UART0 and UART2. Figures 2.11.2 and 2.11.3 show the block
diagram of the transmit/receive unit.
UARTi (i = 0 and 2) has two operation modes: a clock synchronous serial I/O mode and a clock asynchronous
serial I/O mode (UART mode). The contents of the serial I/O mode select bits (bits 0 to 2 at addresses 03A016
and 037816) determine whether UARTi is used as a clock synchronous serial I/O or as a UART. Although a
few functions are different, UART0 and UART2 have almost the same functions.
UART0 and UART2 are almost equal in their functions with minor exceptions. UART2, in particular, also
has the bus collision detection function that generates an interrupt request if the TxD pin and the RxD pin
are different in level.
Table 2.11.1 shows the comparison of functions of UART0 and UART2, and Figures 2.11.4 to 2.11.13
show the registers related to UARTi.
Table 2.11.1 Comparison of functions of UART0 and UART2
Function
UART0
UART2
CLK polarity selection
Possible
(Note 1)
Possible
(Note 1)
LSB first / MSB first selection
Possible
(Note 1)
Possible
(Note 2)
Continuous receive mode selection
Possible
(Note 1)
Possible
(Note 1)
Transfer clock output from multiple
pins selection
Impossible
Impossible
Serial data logic switch
Impossible
Possible
TxD, RxD I/O polarity switch
Impossible
Possible
TxD, RxD port output format
CMOS output
N-channel open-drain
output
Parity error signal output
Impossible
Possible
Bus collision detection
Impossible
Possible
Notes 1: Only when clock synchronous serial I/O mode.
2: Only when clock synchronous serial I/O mode and 8-bit UART mode.
Rev.1.00
May 18, 2004
page 100 of 296
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
(UART0)
RxD0
TxD0
UART reception
1/16
Clock source selection UART 0 bit rate
f1
f8
f32
Internal
Reception
control circuit
Clock synchronous type
generator
(address 03A1 16)
1 / (n0+1)
UART transmission
1/16
Transmission
control circuit
Clock synchronous type
External
Receive
clock
Transmit/
receive
unit
Transmit
clock
Clock synchronous type
(when internal clock is selected)
1/2
Clock synchronous type
(when internal clock is selected)
CLK
polarity
reversing
circuit
CLK0
Clock synchronous type
(when external clock is
selected)
CTS/RTS disabled
CTS/RTS selected
RTS0
CTS0 / RTS0
Vcc
CTS/RTS disabled
CTS0
(UART2)
TxD
polarity
reversing
circuit
RxD polarity
reversing circuit
RxD2
Clock source selection
f1
f8
f32
Internal
UART reception
1/16
UART2 bit rate
Clock synchronous type
generator
(address 0379 16)
1 / (n2+1)
UART transmission
1/16
Clock synchronous type
External
Reception
control circuit
Transmission
control circuit
Receive
clock
Transmit/
receive
unit
Transmit
clock
Clock synchronous type
1/2
CLK2
CLK
polarity
reversing
circuit
(when internal clock is selected)
Clock synchronous type
(when internal clock is selected)
CTS/RTS
selected
Clock synchronous type
(when external clock is
selected)
CTS/RTS disabled
RTS2
CTS2 / RTS2
Vcc
CTS/RTS disabled
CTS 2
n0 : Values set to UART0 bit rate generator (BRG0)
n2 : Values set to UART2 bit rate generator (BRG2)
Figure 2.11.1 Block diagram of UARTi (i = 0 and 2)
Rev.1.00
May 18, 2004
page 101 of 296
TxD2
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
Clock
synchronous type
PAR
disabled
1SP
RxD0
SP
SP
UART (7 bits)
UART (8 bits)
Clock
synchronous
type
UARTi receive register
UART (7 bits)
PAR
PAR
enabled
2SP
UART
UART (9 bits)
Clock
synchronous type
UART (8 bits)
UART (9 bits)
0
0
0
0
0
0
0
D8
D7
D6
D5
D4
D3
D2
D1
D0
UART0 receive
buffer register
Address 03A616
Address 03A716
MSB/LSB conversion circuit
Data bus high-order bits
Data bus low-order bits
MSB/LSB conversion circuit
D7
D8
D6
D5
D4
D3
D2
D1
D0
UART0 transmit
buffer register
Address 03A216
Address 03A316
UART (8 bits)
UART (9 bits)
UART (9 bits)
PAR
enabled
2SP
SP
SP
Clock synchronous
type
UART
TxD0
PAR
1SP
PAR
disabled
“0”
Clock
synchronous
type
UART (7 bits)
UART (7 bits)
UART (8 bits)
Clock synchronous
type
Figure 2.11.2 Block diagram of UART0 transmit/receive unit
Rev.1.00
May 18, 2004
page 102 of 296
UART0 transmit register
SP: Stop bit
PAR: Parity bit
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
No reverse
RxD data
reverse circuit
RxD2
Reverse
Clock
synchronous type
PAR
disabled
1SP
SP
UART2 receive register
UART(7 bits)
PAR
SP
2SP
PAR
enabled
0
UART
(7 bits)
UART
(8 bits)
Clock
synchronous
type
0
0
0
UART
0
Clock
synchronous type
UART
(9 bits)
0
0
UART
(8 bits)
UART
(9 bits)
D8
D0
UART2 receive
buffer register
Logic reverse circuit + MSB/LSB conversion circuit
Address 037E16
Address 037F16
D7
D6
D5
D4
D3
D2
D1
Data bus high-order bits
Data bus low-order bits
Logic reverse circuit + MSB/LSB conversion circuit
D7
D8
D6
D5
D4
D3
D2
D1
D0
UART2 transmit
buffer register
Address 037A16
Address 037B16
UART
(8 bits)
UART
(9 bits)
PAR
enabled
2SP
SP
SP
UART
(9 bits)
Clock
synchronous type
UART
PAR
1SP
PAR
disabled
“0”
Clock
synchronous
type
UART
(7 bits)
UART
(8 bits)
UART(7 bits)
UART2 transmit register
Clock
synchronous type
Error signal output
disable
No reverse
TxD data
reverse circuit
Error signal
output circuit
Error signal output
enable
Reverse
SP: Stop bit
PAR: Parity bit
Figure 2.11.3 Block diagram of UART2 transmit/receive unit
Rev.1.00
May 18, 2004
page 103 of 296
TxD2
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
UARTi transmit buffer register
(b15)
b7
(b8)
b0 b7
Symbol
U0TB
U2TB
b0
Address
03A3 16, 03A216
037B 16, 037A16
When reset
Indeterminate
Indeterminate
Function
R W
Transmit data (Note)
Nothing is assigned.
In an attempt to write to these bits, write “0.” The value, if read, turns out to be indeterminate.
Figure 2.11.4 UARTi transmit buffer register (i = 0 and 2)
UARTi receive buffer register
(b15)
b7
(b8)
b0 b7
Symbol
U0RB
U2RB
b0
0
Bit
symbol
Address
03A7 16, 03A6 16
037F16, 037E 16
When reset
Indeterminate
Indeterminate
Function
(During clock synchronous
serial I/O mode)
Bit name
Receive data
Function
(During UART mode)
R W
Receive data
Nothing is assigned.
In an attempt to write to these bits, write “0.” The value, if read, turns out to be “0.”
Reserved bit
Must always be set to “0”
Must always be set to “0”
OER
Overrun error flag (Note 1)
0 : No overrun error
1 : Overrun error found
0 : No overrun error
1 : Overrun error found
FER
Framing error flag (Note 1) Invalid
0 : No framing error
1 : Framing error found
PER
Parity error flag (Note 1)
Invalid
0 : No parity error
1 : Parity error found
SUM
Error sum flag (Note 1)
Invalid
0 : No error
1 : Error found
Notes 1: Bits 15 through 12 are set to “0” when the serial I/O mode select bit (bits 2 to 0 at addresses
03A0 16 and 0378 16) are set to “000 2” or the receive enable bit is set to “0”.
(Bit 15 is set to “0” when bits 14 to 12 all are set to “0.”) Bits 14 and 13 are also set to “0” when
the lower byte of the UARTi receive buffer register (addresses 03A6 16 and 037E 16) is read out.
2: The Receive Buffer Register (received data and error flag) must be read in one operation by
accessing it wordwise.
Figure 2.11.5 UARTi receive buffer register (i = 0 and 2)
*1 Before writing any value, make sure no transmit or receive operation is forbiddew.
*2 Use the MOV instruction to write to this register.
UARTi bit rate generator
b7
b0
Symbol
U0BRG
U2BRG
Address
03A1 16
037916
When reset
Indeterminate
Indeterminate
Function
Assuming that set value = n, BRGi divides the count source by
n+1
Figure 2.11.6 UARTi bit rate generator (i = 0 and 2)
Rev.1.00
May 18, 2004
page 104 of 296
Values that can be set
0016 to FF16
R W
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
UART0 transmit/receive mode register
b7
b6
b5
b4
b3
b2
b1
Symbol
U0MR
b0
0
Address
03A0 16
When reset
0016
Function
(During clock synchronous
serial I/O mode)
Bit
symbol
Bit name
SMD0
Serial I/O mode select bit
Must be fixed to 001
b2 b1 b0
0 0 0 : Serial I/O invalid
0 1 0 : Inhibited
0 1 1 : Inhibited
1 1 1 : Inhibited
SMD1
SMD2
Function
(During UART mode)
b2 b1 b0
1 0 0 : Transfer data 7 bits long
1 0 1 : Transfer data 8 bits long
1 1 0 : Transfer data 9 bits long
0 0 0 : Serial I/O invalid
0 1 0 : Inhibited
0 1 1 : Inhibited
1 1 1 : Inhibited
CKDIR Internal/external clock
select bit
0 : Internal clock
1 : External clock
0 : Internal clock
1 : External clock
STPS
Stop bit length select bit
Invalid
0 : One stop bit
1 : Two stop bits
PRY
Odd/even parity select bit
Invalid
Valid when bit 6 = “1”
0 : Odd parity
1 : Even parity
PRYE
Parity enable bit
Invalid
0 : Parity disabled
1 : Parity enabled
Must always be set to “0”
Must always be set to “0”
IOPOL Reserved bit
R W
Figure 2.11.7 UART0 transmit/receive mode register
UART2 transmit/receive mode register
b7
b6
b5
b4
b3
b2
b1
Symbol
U2MR
b0
Address
037816
Bit
symbol
Bit name
SMD0
Serial I/O mode select bit
When reset
0016
Function
(During clock synchronous
serial I/O mode)
Must be fixed to 001
b2 b1 b0
0 0 0 : Serial I/O invalid
0 1 0 : Inhibited
0 1 1 : Inhibited
1 1 1 : Inhibited
SMD1
SMD2
May 18, 2004
b2 b1 b0
1 0 0 : Transfer data 7 bits long
1 0 1 : Transfer data 8 bits long
1 1 0 : Transfer data 9 bits long
0 0 0 : Serial I/O invalid
0 1 0 : Inhibited
0 1 1 : Inhibited
1 1 1 : Inhibited
CKDIR
Internal/external clock
select bit
0 : Internal clock
1 : External clock
0 : Internal clock
1 : External clock
STPS
Stop bit length select bit
Invalid
0 : One stop bit
1 : Two stop bits
PRY
Odd/even parity select bit
Invalid
Valid when bit 6 = “1”
0 : Odd parity
1 : Even parity
PRYE
Parity enable bit
Invalid
0 : Parity disabled
1 : Parity enabled
IOPOL
TxD, RxD I/O polarity
reverse bit
0 : No reverse
1 : Reverse
Usually set to “0”
0 : No reverse
1 : Reverse
Usually set to “0”
Figure 2.11.8 UART2 transmit/receive mode register
Rev.1.00
Function
(During UART mode)
page 105 of 296
R W
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
UART0 transmit/receive control register 0
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
U0C0
Bit
symbol
CLK0
Address
03A416
Bit name
TXEPT
Function
(During clock synchronous
serial I/O mode)
b1 b0
Function
(During UART mode)
0 0 : f1 is selected
0 1 : f8 is selected
1 0 : f32 is selected
1 1 : Inhibited
0 0 : f 1 is selected
0 1 : f 8 is selected
1 0 : f 32 is selected
1 1 : Inhibited
CTS/RTS function
select bit
Valid when bit 4 = “0”
0 : CTS function is selected (Note 1)
1 : RTS function is selected (Note 2)
Valid when bit 4 = “0”
0 : CTS function is selected (Note 1)
1 : RTS function is selected (Note 2)
0 : Data present in transmit
register (during transmission)
1 : No data present in transmit
register (transmission
completed)
0 : Data present in transmit register
(during transmission)
1 : No data present in transmit
register (transmission completed)
Transmit register empty
flag
CRD
CTS/RTS disable bit
0 : CTS/RTS function enabled
1 : CTS/RTS function disabled
(P60 functions as
programmable I/O port)
0 : CTS/RTS function enabled
1 : CTS/RTS function disabled
(P60 functions as
programmable I/O port)
NCH
Data output select bit
0 : TXDi pin is CMOS output
1 : TXDi pin is N-channel
open-drain output
0: TXDi pin is CMOS output
1: TXDi pin is N-channel
open-drain output
CKPOL
CLK polarity select bit
0 : Transmit data is output at
falling edge of transfer clock
and receive data is input at
rising edge
1 : Transmit data is output at
rising edge of transfer clock
and receive data is input at
falling edge
Must always be set to “0”
UFORM Transfer format select bit 0 : LSB first
1 : MSB first
R W
b1 b0
BRG count source
select bit
CLK1
CRS
When reset
0816
Must always be set to “0”
Notes 1: Set the corresponding port direction register to “0”.
2: The settings of the corresponding port register and port direction register are invalid.
3: When change these register value, change during transmission and reception are forbiddew.
Figure 2.11.9 UART0 transmit/receive control register 0
Rev.1.00
May 18, 2004
page 106 of 296
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
UART2 transmit/receive control register 0
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
U2C0
Bit
symbol
CLK0
Address
037C16
Bit name
TXEPT
Function
(During clock synchronous
serial I/O mode)
b1 b0
b1 b0
0 0 : f1 is selected
0 1 : f8 is selected
1 0 : f32 is selected
1 1 : Inhibited
0 0 : f1 is selected
0 1 : f8 is selected
1 0 : f32 is selected
1 1 : Inhibited
CTS/RTS function
select bit
Valid when bit 4 = “0”
Valid when bit 4 = “0”
0 : CTS function is selected (Note 1)
1 : RTS function is selected (Note 2)
0 : CTS function is selected (Note 1)
1 : RTS function is selected (Note 2)
R W
0 : Data present in transmit
0 : Data present in transmit register
Transmit register empty
register (during transmission)
(during transmission)
flag
1 : No data present in transmit
1 : No data present in transmit
register (transmission
completed)
CRD
Function
(During UART mode)
BRG count source
select bit
CLK1
CRS
When reset
0816
CTS/RTS disable bit
0 : CTS/RTS function enabled
1 : CTS/RTS function disabled
(P73 functions
programmable I/O port)
register (transmission completed)
0 : CTS/RTS function enabled
1 : CTS/RTS function disabled
(P73 functions programmable
I/O port)
0: TXDi pin is CMOS output
0 : TXDi pin is CMOS output
Nothing is assigned.
In an attempt to write to this bit, write1 “:0TXDi
.” Thpin
e vaisluN-channel
e, if read, turns o1u:tTtX
oDbiepi“n0i.s” N-channel
CKPOL
CLK polarity select bit
open-drain output
0 : Transmit data is output at
falling edge of transfer clock
and receive data is input at
rising edge
1 : Transmit data is output at
rising edge of transfer clock
and receive data is input at
falling edge
UFORM Transfer format select bit 0 : LSB first
(Note 3)
1 : MSB first
open-drain output
Must always be set to “0”
0 : LSB first
1 : MSB first
Notes 1: Set the corresponding port direction register to “0”.
2: The settings of the corresponding port register and port direction register are invalid.
3: Only clock synchronous serial I/O mode and 8-bit UART mode are valid.
4: When change these register value, change during transmission and reception are forbiddew.
Figure 2.11.10 UART2 transmit/receive control register 0
Rev.1.00
May 18, 2004
page 107 of 296
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
UART0 transmit/receive control register 1
b7
b6
0
0
b5
b4
b3
b2
b1
b0
Symbol
U0C1
Bit
symbol
Address
03A516
When reset
0216
Function
(During clock synchronous
serial I/O mode)
Bit name
Function
(During UART mode)
TE
Transmit enable bit
0 : Transmission disabled
1 : Transmission enabled
0 : Transmission disabled
1 : Transmission enabled
TI
Transmit buffer
empty flag
0 : Data present in
transmit buffer register
1 : No data present in
transmit buffer register
0 : Data present in
transmit buffer register
1 : No data present in
transmit buffer register
RE
Receive enable bit
0 : Reception disabled
1 : Reception enabled
0 : Reception disabled
1 : Reception enabled
RI
Receive complete flag
0 : No data present in
receive buffer register
1 : Data present in
receive buffer register
0 : No data present in
receive buffer register
1 : Data present in
receive buffer register
U0IRS
UART0 transmit
interrupt cause select bit
0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed
0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed
(TXEPT = 1)
(TXEPT = 1)
U0RRM UART0 continuous
receive mode select bit
0 : Continuous receive mode
Reserved bits
Must always be set to “0”
disabled
RW
Must always be set to “0”
1 : Continuous receive mode
enable
Must always be set to “0”
Figure 2.11.11 UART0 transmit/receive control register 1
UART2 transmit/receive control register 1
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
U2C1
0
Bit
symbol
Address
037D 16
Bit name
When reset
0216
Function
(During clock synchronous
serial I/O mode)
TE
Transmit enable bit
0 : Transmission disabled
1 : Transmission enabled
0 : Transmission disabled
1 : Transmission enabled
TI
Transmit buffer
empty flag
0 : Data present in
transmit buffer register
1 : No data present in
transmit buffer register
0 : Data present in
transmit buffer register
1 : No data present in
transmit buffer register
RE
Receive enable bit
0 : Reception disabled
1 : Reception enabled
0 : Reception disabled
1 : Reception enabled
RI
Receive complete flag
0 : No data present in
receive buffer register
1 : Data present in
receive buffer register
0 : No data present in
receive buffer register
1 : Data present in
receive buffer register
UART2 transmit interrupt
cause select bit
0 : Transmit buffer empty
(TI = 1)
1 : Transmit is completed
(TXEPT = 1)
0 : Transmit buffer empty
(TI = 1)
1 : Transmit is completed
(TXEPT = 1)
U2RRM UART2 continuous
receive mode enable bit
0 : Continuous receive
mode disabled
1 : Continuous receive
mode enabled
Must always be set to “0”
U2LCH Data logic select bit
0 : No reverse
1 : Reverse
0 : No reverse
1 : Reverse
U2ERE Reserved bit
Must always be set to “0”
Must always be set to “0”
U2IRS
Figure 2.11.12 UART2 transmit/receive control register 1
Rev.1.00
May 18, 2004
Function
(During UART mode)
page 108 of 296
RW
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
UART2 special mode register
b7
0
b6
b5
b4
b3
0 0
b2
b1
b0
Symbol
U2SMR
0 0 0
Bit
symbol
Address
037716
Bit name
Reserved bits
Function
(During UART mode)
Must always be set to “0”
Must always be set to “0”
Auto clear function
select bit of transmit
enable bit
Must always be set to “0”
0 : No auto clear function
1 : Auto clear at occurrence of
bus collision
SSS
Transmit start condition
select bit
Must always be set to “0”
0 : Ordinary
1 : Falling edge of RxD2
Must always be set to “0”
Must always be set to “0”
Figure 2.11.13 UART2 special mode register
May 18, 2004
Function
(During clock synchronous
serial I/O mode)
ACSE
Reserved bit
Rev.1.00
When reset
0016
page 109 of 296
R W
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
2.11.2 Clock Synchronous Serial I/O Mode
The clock synchronous serial I/O mode uses a transfer clock to transmit and receive data. Tables 2.11.2
and 2.11.3 list the specifications of the clock synchronous serial I/O mode. Figures 2.11.14 and 2.11.15
show the UARTi transmit/receive mode register in clock synchronous serial I/O mode.
Table 2.11.2 Specifications of clock synchronous serial I/O mode (1)
Item
Specification
Transfer data format
• Transfer data length: 8 bits
Transfer clock
• When internal clock is selected (bit 3 at addresses 03A016, 037816 = “0”) :
fi/ 2(n+1) (Note 1) fi = f1, f8, f32
• When external clock is selected (bit 3 at addresses 03A016, 037816 = “1”) :
Input from CLKi pin
_______
_______
_______ _______
Transmission/reception control • CTS function/RTS function/CTS, RTS function chosen to be invalid
Transmission start condition • To start transmission, the following requirements must be met:
Transmit enable bit (bit 0 at addresses 03A516, 037D16) = “1”
Transmit
buffer empty flag (bit _______
1 at addresses 03A516, 037D16) = “0”
_______
When CTS function selected, CTS input level = “L”
• Furthermore, if external clock is selected, the following requirements must
also be met:
CLKi polarity select bit (bit 6 at addresses 03A416, 037C16) = “0”:
CLKi input level = “H”
CLKi polarity select bit (bit 6 at addresses 03A416, 037C16) = “1”:
CLKi input level = “L”
Reception start condition • To start reception, the following requirements must be met:
Receive enable bit (bit 2 at addresses 03A516, 037D16) = “1”
Transmit enable bit (bit 0 at addresses 03A516, 037D16) = “1”
Transmit buffer empty flag (bit 1 at addresses 03A516, 037D16) = “0”
• Furthermore, if external clock is selected, the following requirements must
also be met:
CLKi polarity select bit (bit 6 at addresses 03A416, 037C16) = “0”:
CLKi input level = “H”
CLKi polarity select bit (bit 6 at addresses 03A416, 037C16) = “1”:
CLKi input level = “L”
Interrupt request
• When transmitting
generation timing
Transmit interrupt cause select bit (bit 0 at address 03B016, bit 4 at
address 037D16) = “0”: Interrupts requested when data transfer from UARTi
transfer buffer register to UARTi transmit register is completed
Transmit interrupt cause select bit (bit 0 at address 03B016, bit 4 at
address 037D16) = “1”: Interrupts requested when data transmission from
UARTi transfer register is completed
• When receiving
Interrupts requested when data transfer from UARTi receive register to
UARTi receive buffer register is completed
Error detection
• Overrun error (Note 2)
This error occurs when the next data is ready before contents of UARTi
receive buffer register are read out
Rev.1.00
May 18, 2004
page 110 of 296
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
Table 2.11.3 Specifications of clock synchronous serial I/O mode (2)
Item
Select function
Specification
• CLK polarity selection
Whether transmit data is output/input at the rising edge or falling edge of the
transfer clock can be selected
• LSB first/MSB first selection
Whether transmission/reception begins with bit 0 or bit 7 can be selected
• Continuous receive mode selection
Reception is enabled simultaneously by a read from the receive buffer register
• Switching serial data logic (UART2)
Whether to reverse data in writing to the transmission buffer register or
reading the reception buffer register can be selected.
• TxD, RxD I/O polarity reverse (UART2)
This function is reversing TxD port output and RxD port input. All I/O data
level is reversed.
Notes 1: “n” denotes the value 0016 to FF16 that is set to the UART bit rate generator.
2: If an overrun error occurs, the UARTi receive buffer will have the next data written in. Note also
that the UARTi receive interrupt request bit is not set to “1”.
Rev.1.00
May 18, 2004
page 111 of 296
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
UART0 transmit/receive mode register
b7
b6
b5
b4
b3
0
b2
b1
b0
Symbol
U0MR
0 0 1
Address
03A0 16
Bit symbol
SMD0
Bit name
Serial I/O mode select bit
SMD1
SMD2
CKDIR
When reset
0016
Internal/external clock
select bit
Function
RW
b2 b1 b0
0 0 1 : Clock synchronous serial
I/O mode
0 : Internal clock
1 : External clock
STPS
PRY
Invalid in clock synchronous serial I/O mode
PRYE
IOPOL
Reserved bit
Must always be set to “0”
Figure 2.11.14 UART0 transmit/receive mode registers in clock synchronous serial I/O mode
UART2 transmit/receive mode register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
U2MR
0 0 1
Address
037816
Bit symbol
SMD0
Bit name
Serial I/O mode select bit
SMD1
SMD2
CKDIR
When reset
0016
Internal/external clock
select bit
Function
b2 b1 b0
0 0 1 : Clock synchronous serial
I/O mode
0 : Internal clock
1 : External clock
STPS
PRY
Invalid in clock synchronous serial I/O mode
PRYE
IOPOL
TxD, RxD I/O polarity
reverse bit (Note)
Note: Usually set to “0”.
0 : No reverse
1 : Reverse
A
A
A
A
A
A
RW
Figure 2.11.15 UART2 transmit/receive mode register in clock synchronous serial I/O mode
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Table 2.11.4 lists the functions of the input/output pins during clock synchronous serial I/O mode. Note
that for a period from when the UARTi operation mode is selected to when transfer starts, the TxDi pin
outputs a “H”. (If the N-channel open-drain is selected, this pin is in floating state.)
Table 2.11.4 Input/output pin functions in clock synchronous serial I/O mode
Pin name
Function
Method of selection
TxDi
(P63, P70)
Serial data output
(Outputs dummy data when performing reception only)
RxDi
(P62, P71)
Serial data input
Port P6 2 and P7 1 direction register (bits 2 at address 03EE 16,
bit 1 at address 03EF 16)= “0”
(Can be used as an input port when performing transmission only)
CLKi
(P61, P72)
Transfer clock output
Internal/external clock select bit (bit 3 at address 03A0 16, 0378 16) = “0”
Transfer clock input
Internal/external clock select bit (bit 3 at address 03A0 16, 0378 16) = “1”
Port P6 1 and P7 2 direction register (bits 1 at address 03EE 16,
bit 2 at address 03EF 16) = “0”
CTS input
CTS/RTS disable bit (bit 4 at address 03A4 16, 037C 16) =“0”
CTS/RTS function select bit (bit 2 at addresses 03A4 16, 037C 16) = “0”
Port P6 0 and P7 3 direction register (bits 0 at address 03EE 16,
bit 3 at address 03EF 16) = “0”
RTS output
CTS/RTS disable bit (bit 4 at address 03A4 16, 037C 16) = “0”
CTS/RTS function select bit (bit 2 at address 03A4 16, 037C 16) = “1”
Programmable I/O port
CTS/RTS disable bit (bit 4 at address 03A4 16, 037C 16) = “1”
CTSi/RTSi
(P60, P73)
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• Example of transmit timing (when internal clock is selected)
Tc
Transfer clock
“1”
Transmit enable
bit (TE)
“0”
Data is set in UARTi transmit buffer register
“1”
Transmit buffer
empty flag (Tl)
“0”
Transferred from UARTi transmit buffer register to UARTi transmit register
“H”
CTSi
TCLK
“L”
Stopped pulsing because CTS = “H”
Stopped pulsing because transfer enable bit = “0”
CLKi
TxDi
D0 D1 D2 D3 D4 D5 D6 D7
Transmit
register empty
flag (TXEPT)
“1”
Transmit interrupt
request bit (IR)
“1”
D0 D 1 D2 D3 D4 D5 D6 D7
D0 D1 D 2 D 3 D4 D5 D6 D7
“0”
“0”
Cleared to “0” when interrupt request is accepted, or cleared by software
Shown in ( ) are bit symbols.
The above timing applies to the following settings:
• Internal clock is selected.
• CTS function is selected.
• CLK polarity select bit = “0”.
• Transmit interrupt cause select bit = “0”.
Tc = TCLK = 2(n + 1) / fi
fi: frequency of BRGi count source (f 1, f8, f32)
n: value set to BRGi
• Example of receive timing (when external clock is selected)
Receive enable
bit (RE)
Transmit enable
bit (TE)
Transmit buffer
empty flag (Tl)
“1”
“0”
“1”
“0”
“0”
“H”
RTSi
Dummy data is set in UARTi transmit buffer register
“1”
Transferred from UARTi transmit buffer register to UARTi transmit register
“L”
1 / fEXT
CLKi
Receive data is taken in
D0 D1 D2 D3 D4 D5 D6 D7
RxDi
“1”
Receive complete
“0”
flag (Rl)
Receive interrupt
request bit (IR)
Transferred from UARTi receive register
to UARTi receive buffer register
D 0 D1 D2
D3 D4 D5
Read out from UARTi receive buffer register
“1”
“0”
Cleared to “0” when interrupt request is accepted, or cleared by software
Shown in ( ) are bit symbols.
The above timing applies to the following settings:
• External clock is selected.
• RTS function is selected.
• CLK polarity select bit = “0”.
Meet the following conditions are met when the CLK
input before data reception = “H”
• Transmit enable bit “1”
• Receive enable bit “1”
• Dummy data write to UARTi transmit buffer register
fEXT: frequency of external clock
Figure 2.11.16 Typical transmit/receive timings in clock synchronous serial I/O mode
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(1) Polarity select function
As shown in Figure 2.11.17, the CLK polarity select bit (bit 6 at addresses 03A416, 037C16) allows
selection of the polarity of the transfer clock.
• When CLK polarity select bit = “0”
CLKi
TXDi
D0
D1
D2
D3
D4
D5
D6
D7
RXDi
D0
D1
D2
D3
D4
D5
D6
D7
Note 1: The CLK pin level when not
transferring data is “H”.
• When CLK polarity select bit = “1”
CLKi
TXDi
D0
D1
D2
D3
D4
D5
D6
D7
RXDi
D0
D1
D2
D3
D4
D5
D6
D7
Note 2: The CLK pin level when not
transferring data is “L”.
Figure 2.11.17 Polarity of transfer clock
(2) LSB first/MSB first select function
As shown in Figure 2.11.18, when the transfer format select bit (bit 7 at addresses 03A416, 037C16) =
“0”, the transfer format is “LSB first”; when the bit = “1”, the transfer format is “MSB first”.
• When transfer format select bit = “0”
CLKi
TXDi
D0
D1
D2
D3
D4
D5
D6
D7
LSB first
RXDi
D0
D1
D2
D3
D4
D5
D6
D7
D2
D1
D0
• When transfer format select bit = “1”
CLKi
TXDi
D7
D6
D5
D4
D3
MSB first
RXDi
D7
D6
D5
D4
D3
D2
D1
D0
Note: This applies when the CLK polarity select bit = “0”.
Figure 2.11.18 Transfer format
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(3) Continuous receive mode
If the continuous receive mode enable bit (bits 2 at address 03A516, bit 5 at address 037D16) is set to
“1”, the unit is placed in continuous receive mode. In this mode, when the receive buffer register is
read out, the unit simultaneously goes to a receive enable state without having to set dummy data to
the transmit buffer register back again.
(4) Serial data logic switch function (UART2)
When the data logic select bit (bit6 at address 037D16) = “1”, and writing to transmit buffer register or
reading from receive buffer register, data is reversed. Figure 2.11.19 shows the example of serial data
logic switch timing.
•When LSB first
Transfer clock
“H”
“L”
TxD2
“H”
(no reverse) “L”
TxD2
“H”
(reverse) “L”
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
Figure 2.11.19 Serial data logic switch timing
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2.11.3 Clock Asynchronous Serial I/O (UART) Mode
The UART mode allows transmitting and receiving data after setting the desired transfer rate and transfer
data format. Tables 2.11.5 and 2.11.6 list the specifications of the UART mode. Figure 2.11.20 and
2.11.21 show the UARTi transmit/receive mode register in UART mode.
Table 2.11.5 Specifications of UART Mode (1)
Item
Transfer data format
Transfer clock
Specification
• Character bit (transfer data): 7 bits, 8 bits, or 9 bits as selected
• Start bit: 1 bit
• Parity bit: Odd, even, or nothing as selected
• Stop bit: 1 bit or 2 bits as selected
• When internal clock is selected (bit 3 at addresses 03A016, 037816 = “0”) :
fi/16(n+1) (Note 1) fi = f1, f8, f32
• When external clock is selected (bit 3 at addresses 03A016, 037816 =“1”) :
fEXT/16(n+1)(Note 1) (Note 2)
_______
_______
_______
_______
Transmission/reception control • CTS function/RTS function/CTS, RTS function chosen to be invalid
Transmission start condition • To start transmission, the following requirements must be met:
Transmit enable bit (bit 0 at addresses 03A516, 037D16) = “1”
Transmit buffer empty flag (bit 1 at addresses 03A516, 037D16) = “0”
_______
_______
When CTS function selected, CTS input level = “L”
Reception start condition • To start reception, the following requirements must be met:
Receive enable bit (bit 2 at addresses 03A516, 037D16) = “1”
Start bit detection
Interrupt request
• When transmitting
generation timing
Transmit interrupt cause select bits (bits 0 at address 03B016, bit4 at
address 037D16) = “0”: Interrupts requested when data transfer from UARTi
transfer buffer register to UARTi transmit register is completed
Transmit interrupt cause select bits (bits 0 at address 03B016, bit4 at
address 037D16) = “1”: Interrupts requested when data transmission from
UARTi transfer register is completed
• When receiving
Interrupts requested when data transfer from UARTi receive register to
UARTi receive buffer register is completed
Error detection
• Overrun error (Note 3)
This error occurs when the next data is ready before contents of UARTi
receive buffer register are read out
• Framing error
This error occurs when the number of stop bits set is not detected
• Parity error
This error occurs when if parity is enabled, the number of 1’s in parity and
character bits does not match the number of 1’s set
• Error sum flag
This flag is set (= 1) when any of the overrun, framing, and parity errors is
encountered
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Table 2.11.6 Specifications of UART Mode (2)
Item
Select function
Specification
• Serial data logic switch (UART2)
This function is reversing logic value of transferring data. Start bit, parity bit
and stop bit are not reversed.
• TxD, RxD I/O polarity switch
This function is reversing TxD port output and RxD port input. All I/O data
level is reversed.
Notes 1: ‘n’ denotes the value 0016 to FF16 that is set to the UARTi bit rate generator.
2: fEXT is input from the CLKi pin.
3: If an overrun error occurs, the UARTi receive buffer will have the next data written in. Note also
that the UARTi receive interrupt request bit is not set to “1”.
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UART0 transmit/receive mode register
b7
b6
b5
b4
b3
b2
b1
Symbol
U0MR
b0
0
Address
03A0 16
Bit symbol
SMD0
When reset
0016
Bit name
Serial I/O mode select bit
SMD1
SMD2
Function
1 0 0 : Transfer data 7 bits long
1 0 1 : Transfer data 8 bits long
1 1 0 : Transfer data 9 bits long
Internal / external clock
select bit
Stop bit length select bit
0 : Internal clock
1 : External clock
0 : One stop bit
1 : Two stop bits
PRY
Odd / even parity
select bit
Valid when bit 6 = “1”
0 : Odd parity
1 : Even parity
PRYE
Parity enable bit
0 : Parity disabled
1 : Parity enabled
IOPOL
Reserved bit
Must always be set to “0”
CKDIR
STPS
RW
b2 b1 b0
Figure 2.11.20 UART0 transmit/receive mode register in UART mode
UART2 transmit/receive mode register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
U2MR
Address
0378 16
Bit symbol
SMD0
When reset
0016
Bit name
Serial I/O mode select bit
SMD1
SMD2
Function
b2 b1 b0
1 0 0 : Transfer data 7 bits long
1 0 1 : Transfer data 8 bits long
1 1 0 : Transfer data 9 bits long
Internal / external clock
select bit
Stop bit length select bit
0 : Internal clock
1 : External clock
0 : One stop bit
1 : Two stop bits
PRY
Odd / even parity
select bit
Valid when bit 6 = “1”
0 : Odd parity
1 : Even parity
PRYE
Parity enable bit
0 : Parity disabled
1 : Parity enabled
IOPOL
TxD, RxD I/O polarity
reverse bit (Note)
0 : No reverse
1 : Reverse
CKDIR
STPS
Note: Usually set to “0”.
Figure 2.11.21 UART2 transmit/receive mode register in UART mode
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RW
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
Table 2.11.7 lists the functions of the input/output pins during UART mode. Note that for a period from
when the UARTi operation mode is selected to when transfer starts, the TxDi pin outputs a “H”. (If the Nchannel open-drain is selected, this pin is in floating state.)
Table 2.11.7 Input/output pin functions in UART mode
Pin name
Function
Method of selection
TxDi
(P63, P70)
Serial data output
RxDi
(P62, P71)
Serial data input
CLKi
(P61, P72)
Programmable I/O port
Internal/external clock select bit (bit 3 at address 03A0 16, 0378 16) = “0”
Transfer clock input
Internal/external clock select bit (bit 3 at address 03A0 16, 0378 16) = “1”
Port P6 1 and P7 2 direction register (bit 1 at address 03EE 16,
bit 2 at address 03EF 16) = “0”
CTSi/RTSi
(P60, P73)
CTS input
CTS/RTS disable bit (bit 4 at address 03A4 16 , 037C16) =“0”
CTS/RTS function select bit (bit 2 at address 03A4 16, 037C 16) = “0”
Port P6 0 and P7 3 direction register (bit 0 at address 03EE 16,
bit 3 at address 03EF 16) = “0”
RTS output
CTS/RTS disable bit (bit 4 at address 03A4 16 , 037C16) = “0”
CTS/RTS function select bit (bit 2 at address 03A4 16, 037C 16) = “1”
Programmable I/O port
CTS/RTS disable bit (bit 4 at address 03A4 16 , 037C16) = “1”
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Port P6 2 and P7 1 direction register (bit 2 at address 03EE 16 ,
bit 1 at address 03EF 16)= “0”
(Can be used as an input port when performing transmission only)
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
<UART0>
• Example of transmit timing when transfer data is 8 bits long (parity enabled, one stop bit)
The transfer clock stops momentarily as CTS is “H” when the stop bit is checked.
The transfer clock starts as the transfer starts immediately CTS changes to “L”.
Tc
Transfer clock
Transmit enable
bit(TE)
“1”
Transmit buffer
empty flag(TI)
“1”
“0”
Data is set in UARTi transmit buffer register.
“0”
Transferred from UARTi transmit buffer register to UARTi transmit register
“H”
CTSi
“L”
Start
bit
TxDi
Parity
bit
ST D0 D1 D2 D3 D4 D5 D6 D7
Transmit register
empty flag (TXEPT)
“1”
Transmit interrupt
request bit (IR)
“1”
P
Stopped pulsing because transmit enable bit = “0”
Stop
bit
SP
ST D0 D1 D2 D3 D4 D5 D6 D7
P
ST D0 D1
SP
“0”
“0”
Cleared to “0” when interrupt request is accepted, or cleared by software
Shown in ( ) are bit symbols.
The above timing applies to the following settings :
• Parity is enabled.
• One stop bit.
• CTS function is selected.
• Transmit interrupt cause select bit = “1”.
Tc = 16 (n + 1) / fi or 16 (n + 1) / f EXT
fi : frequency of BRGi count source (f 1, f8, f32)
fEXT : frequency of BRGi count source (external clock)
n : value set to BRGi
<UART0>
• Example of transmit timing when transfer data is 9 bits long (parity disabled, two stop bits)
Tc
Transfer clock
Transmit enable
bit(TE)
“1”
Transmit buffer
empty flag(TI)
“1”
“0”
Data is set in UARTi transmit buffer register
“0”
Transferred from UARTi transmit buffer register to UARTi transmit register
Start
bit
TxDi
Stop
bit
ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP SP
Stop
bit
ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SPSP
ST D0 D1
“1”
Transmit register
empty flag (TXEPT)
“0”
Transmit interrupt
request bit (IR)
“1”
“0”
Cleared to “0” when interrupt request is accepted, or cleared by software
Shown in ( ) are bit symbols.
The above timing applies to the following settings :
• Parity is disabled.
• Two stop bits.
• CTS function is disabled.
• Transmit interrupt cause select bit = “0”.
Tc = 16 (n + 1) / fi or 16 (n + 1) / f EXT
fi : frequency of BRGi count source (f 1, f8, f32)
fEXT : frequency of BRGi count source (external clock)
n : value set to BRGi
Figure 2.11.22 Typical transmit/receive timings in UART mode (1)
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<UART2>
• Example of transmit timing when transfer data is 8 bits long (parity enabled, one stop bit)
Tc
Transfer clock
Transmit enable
bit(TE)
“1”
Transmit buffer
empty flag(TI)
“1”
Data is set in UART2 transmit buffer register
“0”
Note
“0”
Transferred from UART2 transmit buffer register to UARTi transmit register
Parity
bit
Start
bit
TxD2
ST D0 D1 D2 D3 D4 D5 D6 D7
P
Stop
bit
ST D0 D1 D2 D3 D4 D5 D6 D7
SP
P
SP
“1”
Transmit register
empty flag (TXEPT) “0”
Transmit interrupt
request bit (IR)
“1”
“0”
Cleared to “0” when interrupt request is accepted, or cleared by software
Shown in ( ) are bit symbols.
The above timing applies to the following settings :
• Parity is enabled.
• One stop bit.
• Transmit interrupt cause select bit = “1”.
Tc = 16 (n + 1) / fi
fi : frequency of BRG2 count source (f 1, f8, f32)
n : value set to BRG2
Note: The transmit is started with overflow timing of BRG after having written in a value at the transmit buffer in the above timing.
<UART2, UART0>
• Example of receive timing when transfer data is 8 bits long (parity disabled, one stop bit)
BRGi count
source
Receive enable bit
“1”
“0”
Stop bit
Start bit
RxDi
D0
D1
D7
Sampled “L”
Receive data taken in
Transfer clock
Receive
complete flag
RTSi
Receive interrupt
request bit
“1”
Reception triggered when transfer clock
is generated by falling edge of start bit
Transfered from UARTi receive register to
UARTi receive buffer register
“0”
“H”
“L”
“1”
“0”
Cleared to “0” when interrupt request is accepted, or cleared by software
The above timing applies to the following settings :
•Parity is disabled.
O
t bit
Figure 2.11.23 Typical transmit/receive timings in UART mode (2)
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(1) Function for switching serial data logic (UART2)
When the data logic select bit (bit 6 of address 037D16) is assigned 1, data is inverted in writing to the
transmission buffer register or reading the reception buffer register. Figure 2.11.24 shows the example of timing for switching serial data logic.
• When LSB first, parity enabled, one stop bit
Transfer clock
“H”
“L”
TxD2
“H”
(no reverse)
“L”
TxD2
“H”
(reverse)
“L”
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
ST : Start bit
P : Even parity
SP : Stop bit
Figure 2.11.24 Timing for switching serial data logic
(2) TxD, RxD I/O polarity reverse function (UART2)
This function is to reverse TxD pin output and RxD pin input. The level of any data to be input or output
(including the start bit, stop bit(s), and parity bit) is reversed. Set this function to “0” (not to reverse) for
usual use.
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(3) Bus collision detection function and other functions (UART2)
This function is to sample the output level of the TxD pin and the input level of the RxD pin at the rising
edge of the transfer clock; if their values are different, then an interrupt request occurs. Figure 2.11.25
shows the example of detection timing of a buss collision (in UART mode).
And also, bit 5 of the special UART2 mode register is used as the selection bit for auto clear function
select bit of enable bit. Setting this bit to “1” automatically resets the transmit enable bit to “0” when “1”
is set in the bus collision detection interrupt request bit (nonconformity) (refer to Figure 2.11.25).
Bit 6 of the special UART2 mode register is used as the transmit start condition select bit. Setting this
bit to “1” starts the TxD transmission in synchronization with the falling edge of the RxD terminal (refer
to Figure 2.11.26).
Transfer clock
“H”
“L”
TxD2
“H”
ST
SP
ST
SP
“L”
RxD2
“H”
“L”
Bus collision detection
interrupt request signal
“1”
Bus collision detection
interrupt request bit
“1”
“0”
“0”
ST : Start bit
SP : Stop bit
Figure 2.11.25 Detection timing of a bus collision (in UART mode)
Transmit start condition select bit (Bit 6 of the UART2 special mode register)
0: In normal state
CLK
TxD
Enabling transmission
With "1: falling edge of RxD2" selected
CLK
TxD
RxD
Figure 2.11.26 Some other functions
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2.11.4 Serial Interface Ports
The I/O ports (P67, P70 to P72, P93, P94) function as I/O ports of UART2 and multi-master I2C-BUS interface 0 and 1 (refer to “2.11.6 Multi-master I2C-BUS interface i”) . Set the connection between both serial
interfaces and each port by bits 0 and 1 (BSEL0 and BSEL1) of the peripheral mode register (address
027D16), bits 0 and 2 (PSEL0 and FIICON) of the I2C0 port selection register (address 02E516), and bits 2
(FIICON) of the I2C1 port selection register (address 02ED16).
I2C1-FIICON
“1”
SCL
Multi-master I2C-BUS
interface 1
“0”
SCL3/RxD2/DA1/P94
“1”
SDA
“0”
PSEL0
RxD2
CLK2
UART2
TxD2
SDA3/TxD2/DA0/P93
I2C0-FIICON
“1”
“0”
“1”
“0”
“1”
“0”
“1”
“0”
“1”
“0”
BSEL0
“0”
“1”
SCL1/RxD2/P71
BSEL1
“0”
“1”
“0”
“1”
SCL2/CLK2/P72
SCL
Multi-master
interface 0
I2C-BUS
SDA
BSEL0
“0”
“0”
“1”
“1”
SDA1/TxD2/P70
BSEL1
“0”
“1”
SDA2/P67
Figure 2.11.27 Serial interface port control
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2.11.5 Multi-master I2C-BUS Interface 0 and Multi-master I2C-BUS Interface 1
The multi-master I2C-BUS interface 0 and 1 have each dedicated circuit and operate independently.
The multi-master I2C-BUS interface i is a serial communications circuit, conforming to the Philips I2CBUS data transfer format. This interface i, offering both arbitration lost detection and a synchronous
functions, is useful for the multi-master serial communications.
Figures 2.11.28 and 2.11.29 show a block diagram of the multi-master I2C-BUS interface i and Table
2.11.8 shows multi-master I2C-BUS interface i functions.
This multi-master I2C-BUS interface i consists of the I2Ci address register, the I2Ci data shift register, the
I2Ci clock control register, the I2Ci control register, the I2Ci status register, the I2Ci port selection register
and other control circuits.
Table 2.11.8 Multi-master I2C-BUS Interface Functions
Item
Format
Communication mode
SCL clock frequencyn
Function
In conformity with Philips I2C-BUS standard:
10-bit addressing format
7-bit addressing format
High-speed clock mode
Standard clock mode
In conformity with Philips I2C-BUS standard:
Master transmission Master reception
Slave transmission
Slave reception
16.1 kHz to 400 kHz (at BCLK = 16 MHz)
Note : We are not responsible for any third party’s infringement of patent rights or other rights attributable
to the use of the control function (bits 6 and 7 of the I2C control register at address 027D16) for
connections between the I2C-BUS interface 0 and ports (SCL1, SCL2, SDA1, SDA2).
Rev.1.00
May 18, 2004
page 126 of 296
Rev.1.00
May 18, 2004
page 127 of 296
P72/CLK2/SCL2
P71/RxD2/SCL1
P67/SDA2
P70/TxD2/SDA1
“0”
“1”
“0”
“1”
“0”
“1”
“0”
“1”
Fig. 2.11.28 Block Diagram of Multi-master I2C-BUS Interface 0
(SCL)
Serial
clock
(SDA)
Serial
data
Noise
elimination
circuit
Noise
elimination
circuit
Clock
control
circuit
BB
circuit
AL
circuit
Data
control
circuit
I2C0 clock control register
(IIC0S2)
Clock division
b0
ACK F AST
CCR4 CCR3 CCR2 CCR1 CCR0
BIT MODE
b0
b7
I2C0 data shift register (IIC0S0)
ACK
b7
Address comparator
BCLK
10 BIT
S AD
AL S
b0
ESO BC2 BC1 BC0
b0
I2C0 status
register (IIC0S1)
AL AAS AD0 LRB
Interrupt
request signal
(IICIRQ)
Bit counter
I2C0 control register (IIC0S1D)
b7
Internal data bus
MST TRX BB PIN
b7
Interrupt
generating
circuit
Note: Select ports to use for multi-master I2C-BUS interface by bits 0 and 1 (BSEL0, BSEL1) of peripheral mode register.
Set bit 7 (SSCK) of the peripheral mode register according to the XIN frequency to be used.
BSEL1
BSEL0
BSEL1
BSEL0
SAD6 SAD5 SAD4 SAD3 SAD2 SAD1 SAD0 RBW
2
b7 I C0 address register (IIC0S0D) b0
0
0
0
0
FIICON
0
b0
PS EL0
I2C0 port selection register (IIC0S2D)
0
b7
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
Rev.1.00
May 18, 2004
page 128 of 296
P94/DA1/SCL3/RXD2
P93/DA0/SDA3/TXD2
Fig. 2.11.29 Block Diagram of Multi-master I2C-BUS Interface 1
(SCL)
Serial
clock
(SDA)
Serial
data
Noise
elimination
circuit
Noise
elimination
circuit
Clock
control
circuit
BB
circuit
AL
circuit
Data
control
circuit
2
b7 I C1 address register (IIC1S0D) b0
b0
b0
ACK F AST
CCR4 CCR3 CCR2 CCR1 CCR0
BIT MODE
I2C1 data shift register (IIC1S0)
I2C1 clock control register
(IIC1S2)
Clock division
ACK
b7
b7
Address comparator
SAD6 SAD5 SAD4 SAD3 SAD2 SAD1 SAD0 RBW
BCLK
10 BIT
S AD
AL S
b0
ESO BC2 BC1 BC0
b0
I2C1 status
register (IIC1S1)
AL AAS AD0 LRB
Interrupt
request signal
(IICIRQ)
Bit counter
I2C1 control register (IIC1S1D)
b7
Internal data bus
MST TRX BB PIN
b7
Interrupt
generating
circuit
0
0
0
0
FIICON
0
0
b0
I2C1 port selection register (IIC1S2D)
0
b7
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
(1) I2Ci port selection register (i = 0, 1)
The I2Ci port selection register consists of bit to validate the multi-master I2C-BUS interface i function.
■ Bit 0: TXD2, RXD2 port select bit
Note: I2C0 Port Selection Register only
When using UART2, setting bit to “0” causes P70 and P71 to function respectively as TXD2 and RXD2,
and setting bit to “1” causes P93 and P94 to function respectively as TXD2 and RXD2.
Note that the multimaster I2C-BUS interface enable bit (FIICON) described later has priority over this
bit.
■ Bit 2: Multi-master I2C-BUS interface valid bit (FIICON)
When this bit is “0”, the multi-master I2C-BUS interface i is nonactive; when “1”, it is active. When
selecting active, multi-master I2C-BUS interface 0 is connected with the ports selected by bits 0 and 1
of the peripheral mode register (address 027D16) and multi-master I2C-BUS interface 1 is connected
with the ports P93 and P94.
Note: It needs 20-BCLK cycles from setting this bit to “1” to being active of multi-master I2C-BUS
interface i. Accordingly, do not access multi-master I2C-BUS interface i-related registers in this
period.
I2C0 port selection register
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0 0 0
Symbol
IIC0S2D
0
Bit Symbol
PSEL0
Address
02E516
Bit name
Function
R W
0 : P70 and P71
1 : P93 and P94
TXD2 and RXD2
port select bit
Reserved bits
FIICON
When reset
00?000002
Must always be set to “0”
Multi-master I2C-BUS
interface valid bit
Reserved bits
0 : Nonactive
1 : Active
Must always be set to “0”
I2C1 port selection register
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0 0 0
Symbol
IIC1S2D
0 0
Bit Symbol
Address
02ED16
Bit name
Reserved bits
FIICON
Fig. 2.11.30 I2Ci port selection register (i = 0, 1)
May 18, 2004
page 129 of 296
Function
Must always be set to “0”
Multi-master I2C-BUS
interface valid bit
Reserved bits
Rev.1.00
When reset
00?000002
0 : Nonactive
1 : Active
Must always be set to “0”
R W
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
(2) I2Ci data shift register, I2Ci transmit buffer register (i = 0, 1)
The I2Ci data shift register is an 8-bit shift register to store receive data and write transmit data.
When transmit data is written into this register, it is transferred to the outside from bit 7 in synchronization with the SCL clock, and each time one-bit data is output, the data of this register are shifted one bit
to the left. When data is received, it is input to this register from bit 0 in synchronization with the SCL
clock, and each time one-bit data is input, the data of this register are shifted one bit to the left.
The I2Ci data shift register is in a write enable status only when the ESO bit of the I2Ci control register
is “1.” The bit counter is reset by a write instruction to the I2Ci data shift register. When both the ESO
bit and the MST bit of the I2Ci status register are “1,” the SCL is output by a write instruction to the I2Ci
data shift register. Reading data from the I2Ci data shift register is always enabled regardless of the
ESO bit value.
The I2Ci transmit buffer register is a register to store transmit data (slave address) to the I2Ci data shift
register before RESTART condition generation. That is, in master, transmit data written to the I2Ci
transmit buffer register is written to the I2Ci data shift register simultaneously. However, the SCL is not
output. The I2Ci transmit buffer register can be written only when the ESO bit is “1,” reading data from
the I2Ci transmit buffer register is disabled regardless of the ESO bit value.
Notes 1: To write data into the I2Ci data shift register or the I2Ci transmit buffer register after the MST
bit value changes from “1” to “0” (slave mode), keep an interval of 20 BCLK or more.
2: To generate START/RESTART condition after the I2Ci data shift register or the I2Ci transmit
buffer register is written, keep an interval of 4 BCLK or more.
Rev.1.00
May 18, 2004
page 130 of 296
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
I2Ci data shift register (i = 0, 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
IIC0S0
IIC1S0
Bit Symbol
D0
Address
02E016
02E816
Bit name
Data shift register
D1
When reset
Indeterminate
Indeterminate
Function
R W
This is an 8-bit shift register to store
receive data and write transmit data.
D2
D3
D4
D5
D6
D7
Note: To write data into the I2Ci data shift register after setting the MST bit to “0” (slave
mode), keep an interval of 8 machine cycles or more.
Fig. 2.11.31 I2Ci data shift register (i = 0, 1)
I2Ci transmit buffer register (i = 0, 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
IIC0S0S
IIC1S0S
Address
02E616
02EE16
Bit Symbol
Bit name
S0S0
Transmit buffer register
S0S1
S0S2
S0S3
S0S4
S0S5
S0S6
S0S7
Fig. 2.11.32 I2Ci transmit buffer register (i = 0, 1)
Rev.1.00
May 18, 2004
page 131 of 296
When reset
Indeterminate
Indeterminate
Function
This is an 8-bit register to write transmit
data to I2Ci data shift register.
R W
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
(3) I2Ci address register (i = 0, 1)
_______
The I2Ci address register consists of a 7-bit slave address and a read/write bit. In the addressing
mode, the slave address written in this register is compared with the address data to be received
immediately after the START condition are detected.
_______
■ Bit 0: read/write bit (RBW)
Not used when comparing addresses, in the 7-bit addressing mode. In the 10-bit addressing mode,
the first address data to be received is compared with the contents (SAD6 to SAD0 + RBW) of the I2Ci
address register.
The RBW bit is cleared to “0” automatically when the stop condition is detected.
■ Bits 1 to 7: slave address (SAD0–SAD6)
These bits store slave addresses. Regardless of the 7-bit addressing mode and the 10-bit addressing
mode, the address data transmitted from the master is compared with the contents of these bits.
I2Ci address register (i = 0, 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
IIC0S0D
IIC1S0D
Bit Symbol
<Only in 10-bit addressing (in slave) mode>
The last significant bit of address data is
compared.
0 : Wait the first byte of slave address
after START condition
(read state)
1 : Wait the first byte of slave address
after RESTART condition
(write state)
SAD0
Slave address
<In both modes>
The address data is compared.
SAD3
SAD4
SAD5
SAD6
Fig. 2.11.33 I2Ci address register (i = 0, 1)
page 132 of 296
Function
Read/write bit
SAD2
May 18, 2004
Bit name
When reset
0016
0016
RBW
SAD1
Rev.1.00
Address
02E116
02E916
R W
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
(4) I2Ci clock control register (i = 0, 1)
The I2Ci clock control register is used to set ACK control, SCL mode and SCL frequency.
■ Bits 0 to 4: SCL frequency control bits (CCR0–CCR4)
These bits control the SCL frequency.
■ Bit 5: SCL mode specification bit (FAST MODE)
This bit specifies the SCL mode. When this bit is set to “0,” the standard clock mode is set. When the
bit is set to “1,” the high-speed clock mode is set.
■ Bit 6: ACK bit (ACK BIT)
This bit sets the SDA status when an ACK clock✽ is generated. When this bit is set to “0,” the ACK
return mode is set and SDA goes to LOW at the occurrence of an ACK clock. When the bit is set to “1,”
the ACK non-return mode is set. The SDA is held in the HIGH status at the occurrence of an ACK
clock.
However, when the slave address matches the address data in the reception of address data at ACK
BIT = “0,” the SDA is automatically made LOW (ACK is returned). If there is a mismatch between the
slave address and the address data, the SDA is automatically made HIGH (ACK is not returned).
✽ACK clock: Clock for acknowledgement
■ Bit 7: ACK clock bit (ACK)
This bit specifies a mode of acknowledgment which is an acknowledgment response of data transmission. When this bit is set to “0,” the no ACK clock mode is set. In this case, no ACK clock occurs after
data transmission. When the bit is set to “1,” the ACK clock mode is set and the master generates an
ACK clock upon completion of each 1-byte data transmission.The device for transmitting address data
and control data releases the SDA at the occurrence of an ACK clock (make SDA HIGH) and receives
the ACK bit generated by the data receiving device.
Note: Do not write data into the I2Ci clock control register during transmission. If data is written during
transmission, the I2Ci clock generator is reset, so that data cannot be transmitted normally.
Rev.1.00
May 18, 2004
page 133 of 296
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
I2Ci clock control register (i = 0, 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
IIC0S2
IIC1S2
Bit Symbol
CCR0
Address
02E416
02EC16
When reset
0016
0016
Bit name
SCL frequency control
bits
Function
Setup value of
CCR4–CCR0
00 to 02
CCR1
CCR2
Setup disabled Setup disabled
Setup disabled
04
Setup disabled
250
05
100
400 (See note)
83.3
166
:
CCR4
R W
High speed
clock mode
03
06
CCR3
Standard
clock mode
333
500/CCR value 1000/CCR value
1D
17.2
34.5
1E
16.6
33.3
1F
16.1
32.3
(at BCLK = 10 MHz, unit : kHz)
FAST MODE
ACK BIT
ACK
SCL mode specification 0 : Standard clock mode
bit
1 : High-speed clock mode
ACK bit
0 : ACK is returned.
1 : ACK is not returned.
ACK clock bit
0 : No ACK clock
1 : ACK clock
Note: At 400 kHz in the high-speed clock mode, the duty is as below.
“0” period : “1” period = 3 : 2
In the other cases, the duty is as below.
“0” period : “1” period = 1 : 1
Fig. 2.11.34 I2Ci clock control register (i = 0, 1)
Rev.1.00
May 18, 2004
page 134 of 296
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
(5) I2Ci control register (i = 0, 1)
The I2Ci control register controls the data communication format.
■ Bits 0 to 2: bit counter (BC0–BC2)
These bits decide the number of bits for the next 1-byte data to be transmitted. An interrupt request
signal occurs immediately after the number of bits specified with these bits are transmitted.
When a START condition is received, these bits become “0002” and the address data is always transmitted and received in 8 bits.
Note: When the bit counter value = “1112,” a STOP condition and START condition cannot be waited.
■ Bit 3: I2C-BUS interface i use enable bit (ESO)
This bit enables usage of the multimaster I2C-BUS interface i. When this bit is set to “0,” the use
disable status is provided, so the SDA and the SCL become high-impedance. When the bit is set to
“1,” use of the interface is enabled.
When ESO = “0,” the following is performed.
• PIN = “1,” BB = “0” and AL = “0” are set (they are bits of the I2Ci status register).
• Writing data to the I2Ci data shift register and the I2Ci transmit buffer register is disabled.
■ Bit 4: data format selection bit (ALS)
This bit decides whether or not to recognize slave addresses. When this bit is set to “0,” the addressing format is selected, so that address data is recognized. When a match is found between a slave
address and address data as a result of comparison or when a general call (refer to “(6) I2Ci status
register,” bit 1) is received, transmission processing can be performed. When this bit is set to “1,” the
free data format is selected, so that slave addresses are not recognized.
■ Bit 5: addressing format selection bit (10BIT SAD)
This bit selects a slave address specification format. When this bit is set to “0,” the 7-bit addressing
format is selected. In this case, only the high-order 7 bits (slave address) of the I2Ci address register
are compared with address data. When this bit is set to “1,” the 10-bit addressing format is selected, all
the bits of the I2Ci address register are compared with address data.
Rev.1.00
May 18, 2004
page 135 of 296
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
I2Ci control register (i = 0, 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
IIC0S1D
IIC1S1D
Bit Symbol
BC0
Address
02E316
02EB16
When reset
0016
0016
Bit name
Function
Bit counter
(Number of
transmit/receive bits)
b2 b1 b0
ESO
I2C-BUS interface i use
enable bit
0 : Disabled
1 : Enabled
ALS
Data format selection
bit
0 : Addressing format
1 : Free data format
BC1
BC2
10BIT SAD
0
0
0
0
1
1
1
1
Fig. 2.11.35 I2Ci control register (i = 0, 1)
May 18, 2004
page 136 of 296
0
1
0
1
0
1
0
1
:8
:7
:6
:5
:4
:3
:2
:1
Address format selection 0 : 7-bit addressing format
bit
1 : 10-bit addressing format
Nothing is assigned.
In an attempt to write to these bits, write “0.”
The value, if read, turns out to be “0.”
Rev.1.00
0
0
1
1
0
0
1
1
R W
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
(6) I2Ci status register (i = 0, 1)
The I2Ci status register controls the I2C-BUS interface i status. Bits 0 to 3, 5 are read-only bits and bits
4, 6, 7 can be read out and written to.
■ Bit 0: last receive bit (LRB)
This bit stores the last bit value of received data and can also be used for ACK receive confirmation. If
ACK is returned when an ACK clock occurs, the LRB bit is set to “0.” If ACK is not returned, this bit is
set to “1.” Except in the ACK mode, the last bit value of received data is input. The state of this bit is
changed from “1” to “0” by executing a write instruction to the I2Ci data shift register or the I2Ci transmit
buffer register.
■ Bit 1: general call detecting flag (AD0)
This bit is set to “1” when a general call✽ whose address data is all “0” is received in the slave mode.
By a general call of the master device, every slave device receives control data after the general call.
The AD0 bit is set to “0” by detecting the STOP condition or START condition.
✽General call: The master transmits the general call address “0016” to all slaves.
■ Bit 2: slave address comparison flag (AAS)
This flag indicates a comparison result of address data.
<<In the slave receive mode, when the 7-bit addressing format is selected, this bit is set to “1” in one
of the following conditions.>>
• The address data immediately after occurrence of a START condition matches the slave address
stored in the high-order 7 bits of the I2Ci address register.
• A general call is received.
<<In the slave reception mode, when the 10-bit addressing format is selected, this bit is set to “1” with
the following condition.>>
• When the address data is compared with the I2Ci address register (8 bits consists of slave address
and RBW), the first bytes match.
<<The state of this bit is changed from “1” to “0” by executing a write instruction to the I2Ci data shift
register or the I2Ci transmit buffer register.>>
■ Bit 3: arbitration lost✽ detecting flag (AL)
n the master transmission mode, when a device other than the microcomputer sets the SDA to “L,”,
arbitration is judged to have been lost, so that this bit is set to “1.” At the same time, the TRX bit is set
to “0,” so that immediately after transmission of the byte whose arbitration was lost is completed, the
MST bit is set to “0.” When arbitration is lost during slave address transmission, the TRX bit is set to “0”
and the reception mode is set. Consequently, it becomes possible to receive and recognize its own
slave address transmitted by another master device.
✽Arbitration lost: The status in which communication as a master is disabled.
Rev.1.00
May 18, 2004
page 137 of 296
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
■ Bit 4: I2C-BUS interface i interrupt request bit (PIN)
This bit generates an interrupt request signal. Each time 1-byte data is transmitted, the state of the
PIN bit changes from “1” to “0.” At the same time, an interrupt request signal is sent to the CPU. The
PIN bit is set to “0” in synchronization with a falling edge of the last clock (including the ACK clock) of
an internal clock and an interrupt request signal occurs in synchronization with a falling edge of the
PIN bit. When detecting the STOP condition in slave, the multi-master I2C-BUS interface interrupt
request bit (IR) is set to “1” (interrupt requested) regardless of falling of PIN bit. When the PIN bit is “0,”
the SCL is kept in the “0” state and clock generation is disabled. Figure 2.11.37 shows an interrupt
request signal generating timing chart.
The PIN bit is set to “1” in any one of the following conditions.
• Writing “1” to the PIN bit
• Executing a write instruction to the I2Ci data shift register or the I2Ci transmit buffer register (See note).
• When the ESO bit is “0”
• At reset
Note: It takes 12 BCLK cycles or more until PIN bit becomes “1” after write instructions are executed
to these registers.
The conditions in which the PIN bit is set to “0” are shown below:
• Immediately after completion of 1-byte data transmission (including when arbitration lost is detected)
• Immediately after completion of 1-byte data reception
• In the slave reception mode, with ALS = “0” and immediately after completion of slave address or
general call address reception
• In the slave reception mode, with ALS = “1” and immediately after completion of address data reception
■ Bit 5: bus busy flag (BB)
This bit indicates the status of use of the bus system. When this bit is set to “0,” this bus system is not
busy and a START condition can be generated. When this bit is set to “1,” this bus system is busy and
the occurrence of a START condition is disabled by the START condition duplication prevention function (See note).
This flag can be written by software only in the master transmission mode. In the other modes, this bit is
set to “1” by detecting a START condition and set to “0” by detecting a STOP condition. When the ESO bit
of the I2Ci control register is “0” and at reset, the BB flag is kept in the “0” state.
■ Bit 6: communication mode specification bit (transfer direction specification bit: TRX)
This bit decides the direction of transfer for data communication. When this bit is “0,” the reception
mode is selected and the data of a transmitting device is received. When the bit is “1,” the transmission
mode is selected and address data and control data are output into the SDA in synchronization with
the clock generated on the SCL.
When the ALS bit of the I2Ci control register is “0” in the slave reception mode is selected, the TRX bit
___
is set to “1” (transmit) if the least significant bit (R/W bit) of the address data transmitted by the master
___
is “1.” When the ALS bit is “0” and the R/W bit is “0,” the TRX bit is cleared to “0” (receive).
The TRX bit is cleared to “0” in one of the following conditions.
• When arbitration lost is detected.
• When a STOP condition is detected.
• When occurence of a START condition is disabled by the START condition duplication prevention
function (Note).
• With MST = “0” and when a START condition is detected.
• With MST = “0” and when ACK non-return is detected.
• At reset
Rev.1.00
May 18, 2004
page 138 of 296
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
■ Bit 7: Communication mode specification bit (master/slave specification bit: MST)
This bit is used for master/slave specification for data communication. When this bit is “0,” the slave is
specified, so that a START condition and a STOP condition generated by the master are received,
and data communication is performed in synchronization with the clock generated by the master.
When this bit is “1,” the master is specified and a START condition and a STOP condition are generated, and also the clocks required for data communication are generated on the SCL.
The MST bit is cleared to “0” in one of the following conditions.
• Immediately after completion of 1-byte data transmission when arbitration lost is detected
• When a STOP condition is detected.
• When occurence of a START condition is disabled by the START condition duplication preventing
function (See note).
• At reset
Note: The START condition duplication prevention function disables the following: the START condition generation; bit counter reset, and SCL output with the generation. This bit is valid from
setting of BB flag to the completion of 1-byte transmittion/reception (occurrence of transmission/
reception interrupt request) <IICIRQ>.
I2Ci status register (i = 0, 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
IIC0S1
IIC1S1
Bit Symbol
LRB
Address
02E216
02EA16
When reset
0001000?2
0001000?2
Bit name
Last receive bit
Function
0 : Last bit = “0”
1 : Last bit = “1”
General call detecting
flag (See note)
AAS
Slave address comparison 0 : Address mismatch
flag (See note)
1 : Address match
(See note 1)
Arbitration lost detecting 0 : Not detected
flag (See note)
1 : Detected
(See note 1)
2
0 : No general call detected
1 : General call detected (See note 1)
PIN
I C-BUS interface i
interrupt request bit
0 : Interrupt request issued
1 : No interrupt request issued (See note 2)
BB
Bus busy flag
0 : Bus free
1 : Bus busy
Communication mode
specification bits
b7b6
TRX
MST
0
0
1
1
0 : Slave receive mode
1 : Slave transmit mode
0 : Master receive mode
1 : Master transmit mode
Notes 1: These bits and flags can be read out, but cannot be written.
2: This bit can be written only “1.”
Fig. 2.11.36 I2Ci status register (i = 0, 1)
SCL
PIN
IICIRQ
Fig. 2.11.37 Interrupt request signal generation timing
May 18, 2004
page 139 of 296
(See note 1)
AD0
AL
Rev.1.00
R W
(See note 1)
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
(7) START condition generation method
When the ESO bit of the I2Ci control register is “1,” execute a write instruction to the I2Ci status register
to set the MST, TRX and BB bits to “1.” A START condition will then be generated. After that, the bit
counter becomes “0002” and an SCL for 1 byte is output. The START condition generation timing and
BB bit set timing are different in the standard clock mode and the high-speed clock mode. Refer to
Figure 2.11.38 for the START condition generation timing diagram, and Table 2.11.9 for the START
condition/STOP condition generation timing table.
I2Ci status register write signal
SCL
SDA
Setup
time
Hold time
Set time for
BB flag
BB flag
Fig. 2.11.38 START condition generation timing diagram
(8) STOP condition generation method
When the ESO bit of the I2Ci control register is “1,” execute a write instruction to the I2Ci status register
for setting the MST bit and the TRX bit to “1” and the BB bit to “0”. A STOP condition will then be
generated. The STOP condition generation timing and the BB flag reset timing are different in the
standard clock mode and the high-speed clock mode. Refer to Figure 2.11.39 for the STOP condition
generation timing diagram, and Table 2.11.9 for the START condition/STOP condition generation
timing table.
I2Ci status register write signal
SCL
SDA
BB flag
Setup
time
Hold time
Reset time
for
BB flag
Fig. 2.11.39 STOP condition generation timing diagram
Table 2.11.9 START condition/STOP condition generation timing table
Item
Setup time (Min.)
Hold time (Min.)
Set/reset time for BB flag
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Standard Clock Mode
5.6 µs
4.8 µs
3.5 µs
High-speed Clock Mode
2.1 µs
2.3 µs
0.75 µs
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
(9) START/STOP condition detect conditions
The START/STOP condition detect conditions are shown in Figure 2.11.40 and Table 2.11.10. Only
when the 3 conditions of Table 2.11.10 are satisfied, a START/STOP condition can be detected.
Note: When a STOP condition is detected in the slave mode (MST = 0), an interrupt request signal
<IICIRQ> is generated to the CPU.
SCL release time
SCL
SDA
(START condition)
Setup
time
Hold time
Setup
time
Hold time
SDA
(STOP condition)
Fig. 2.11.40 START condition/STOP condition detect timing diagram
Table 2.11.10 START condition/STOP condition detect conditions
Standard Clock Mode
High-speed Clock Mode
6.5 µs < SCL release time
1.0 µs < SCL release time
3.25 µs < Setup time
0.5 µs < Setup time
3.25 µs < Hold time
0.5 µs < Hold time
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(10) Address data communication
There are two address data communication formats, namely, 7-bit addressing format and 10-bit addressing format. The respective address communication formats is described below.
■ 7-bit addressing format
To meet the 7-bit addressing format, set the 10BIT SAD bit of the I2Ci control register to “0.” The first
7-bit address data transmitted from the master is compared with the high-order 7-bit slave address
stored in the I2Ci address register. At the time of this comparison, address comparison of the RBW bit
of the I2Ci address register is not made. For the data transmission format when the 7-bit addressing
format is selected, refer to Figure 2.11.41, (1) and (2).
■ 10-bit addressing format
To meet the 10-bit addressing format, set the 10BIT SAD bit of the I2Ci control register to “1.” An
address comparison is made between the first-byte address data transmitted from the master and the
7-bit slave address stored in the I2Ci address register. At the time of this comparison, an address
___
comparison between the RBW bit of the I2Ci address register and the R/W bit which is the last bit of
___
the address data transmitted from the master is made. In the 10-bit addressing mode, the R/W bit
which is the last bit of the address data not only specifies the direction of communication for control
data but also is processed as an address data bit.
When the first-byte address data matches the slave address, the AAS bit of the I2Ci status register is
set to “1.” After the second-byte address data is stored into the I2Ci data shift register, make an
address comparison between the second-byte data and the slave address by software. When the
address data of the 2nd bytes matches the slave address, set the RBW bit of the I2Ci address register
___
to “1” by software. This processing can match the 7-bit slave address and R/W data, which are received after a RESTART condition is detected, with the value of the I2Ci address register. For the data
transmission format when the 10-bit addressing format is selected, refer to Figure 2.11.41, (3) and (4).
Rev.1.00
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(11) Example of Master Transmission
An example of master transmission in the standard clock mode, at the SCL frequency of 100 kHz and
in the ACK return mode is shown below.
➀ Set a slave address in the high-order 7 bits of the I2Ci address register and “0” in the RBW bit.
➁ Set the ACK return mode and SCL = 100 kHz by setting “8516” in the I2Ci clock control register.
➂ Set “1016” in the I2Ci status register and hold the SCL at the HIGH.
➃ Set a communication enable status by setting “0816” in the I2Ci control register.
➄ Set the address data of the destination of transmission in the high-order 7 bits of the I2Ci data shift
register and set “0” in the least significant bit.
➅ Set “F016” in the I2Ci status register to generate a START condition. At this time, an SCL for 1 byte
and an ACK clock automatically occurs.
➆ Set transmit data in the I2Ci data shift register. At this time, an SCL and an ACK clock automatically
occurs.
➇ When transmitting control data of more than 1 byte, repeat step ➆.
➈ Set “D016” in the I2Ci status register. After this, if ACK is not returned or transmission ends, a STOP
condition will be generated.
(12) Example of Slave Reception
An example of slave reception in the high-speed clock mode, at the SCL frequency of 400 kHz, in the
ACK non-return mode, using the addressing format, is shown below.
➀ Set a slave address in the high-order 7 bits of the I2Ci address register and “0” in the RBW bit.
➁ Set the no ACK clock mode and SCL = 400 kHz by setting “2516” in the I2Ci clock control register.
➂ Set “1016” in the I2Ci status register and hold the SCL at the HIGH.
➃ Set a communication enable status by setting “0816” in the I2Ci control register.
➄ When a START condition is received, an address comparison is made.
➅
•When all transmitted address are“0” (general call):
AD0 of the I2Ci status register is set to “1”and an interrupt request signal occurs.
•When the transmitted addresses match the address set in ➀:
ASS of the I2Ci status register is set to “1” and an interrupt request signal occurs.
•In the cases other than the above:
AD0 and AAS of the I2Ci status register are set to “0” and no interrupt request signal occurs.
➆ Set dummy data in the I2Ci data shift register.
➇ When receiving control data of more than 1 byte, repeat step ➆.
➈ When a STOP condition is detected, the communication ends.
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M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
S
Slave address R/W
A
Data
A
Data
A/A
P
A
P
Data
A
7 bits
“ 0”
1 to 8 bits
1 to 8 bits
(1) A master-transmitter transmits data to a slave-receiver
S
Slave address R/W
A
Data
A
Data
7 bits
“1”
1 to 8 bits
1 to 8 bits
(2) A master-receiver receives data from a slave-transmitter
S
Slave address
R/W
1st 7 bits
A
Slave address
2nd byte
A
Data
A/A
P
1 to 8 bits
7 bits
“ 0”
8 bits
1 to 8 bits
(3) A master-transmitter transmits data to a slave-receiver with a 10-bit address
S
Slave address
R/W
1st 7 bits
A
Slave address
2nd byte
A
Sr
Slave address
R/W
1st 7 bits
Data
7 bits
“ 0”
8 bits
7 bits
“1” 1 to 8 bits
(4) A master-receiver receives data from a slave-transmitter with a 10-bit address
S : START condition
A : ACK bit
Sr :Restart condition
P : STOP condition
R/W : Read/Write bit
A
Data
A
P
1 to 8 bits
From master to slave
From slave to master
Fig. 2.11.41 Address data communication format
(13) Precautions when using multi-master I2C-BUS interface i
■ BCLK operation mode
Select the no-division mode and set the main clock frequency to f(XIN) = 16 MHz or 10 MHz.
In this case, make sure the Peripheral Mode Register (address 027D16) bit 7 is set according to
the frequency.
■ Used instructions
Specify byte (.B) as data size to access multi-master I2C-BUS interface i-related registers.
■ Read-modify-write instruction
The precautions when the read-modify-write instruction such as BSET, BCLR etc. is executed for
each register of the multi-master I2C-BUS interface are described below.
•I2Ci data shift register (IICiS0)
When executing the read-modify-write instruction for this register during transfer, data may
become a value not intended.
2
•I Ci address register (IICiS0D)
When the read-modify-write instruction is executed for this register at detecting the STOP con______
dition, data may become a value not intended. It is because hardware changes the read/write
bit (RBW) at the above timing.
2
•I Ci status register (IICiS1)
Do not execute the read-modify-write instruction for this register because all bits of this register
are changed by hardware.
•I2Ci control register (IICiS1D)
When the read-modify-write instruction is executed for this register at detecting the START
condition or at completing the byte transfer, data may become a value not intended. Because
hardware changes the bit counter (BC0–BC2) at the above timing.
•I2Ci clock control register (IICiS2)
The read-modify-write instruction can be executed for this register.
•I2Ci port selection register (IICiS2D)
Since the read value of high-order 4 bits is indeterminate, the read-modify-write instruction
cannot be used.
2
•I Ci transmit buffer register (IICiS0S)
Since the value of all bits is indeterminate, the read-modify-write instruction cannot be used.
Rev.1.00
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■ START condition generating procedure using multi-master
:
FCLR
I
(Interrupt disabled)
BTST
5, IICiS1
(BB flag confirming and branch process)
JC
BUSBUSY
BUSFREE:
MOV.B
SA, IICiS0
(Writing of slave address value <SA>)
NOP
➀
➁
NOP
NOP
NOP
MOV.B
#F0H, IICiS1
(Trigger of START condition generating)
FSET
I
(Interrupt enabled)
:
BUSBUSY:
FSETI
(Interrupt enabled)
:
➀ Be sure to add NOP instruction ✕ 4 between writing the slave address value and setting trigger of
START condition generating shown the above procedure example.
➁ When using multi-master system, disable interrupts during the following three process steps:
• BB flag confirming
• Writing of slave address value
• Trigger of START condition generating
When the condition of the BB flag is bus busy, enable interrupts immediately.
When using single-master system, it is not necessary to disable interrupts above.
■ RESTART condition generating procedure
:
➀
MOV.B
SA, IICiS0S
(Writing of slave address value <SA>)
NOP
NOP
MOV.B
#F0H, IICiS1
(Trigger of RESTART condition generating)
:
➀ Use the I2Ci transmit buffer register to write the slave address value to the I2Ci data shift register.
And also, be sure to add NOP instruction ✕ 4.
■ Writing to I2Ci status register
Do not execute an instruction to set the PIN bit to “1” from “0” and an instruction to set the MST and
TRX bits to “0” from “1” simultaneously. It is because it may enter the state that the SCL pin is released
and the SDA pin is released after about one machine cycle. Do not execute an instruction to set the
MST and TRX bits to “0” from “1” simultaneously when the PIN bit is “1.” It is because it may become
the same as above.
■ Process of after STOP condition generating
Do not write data in the I2Ci data shift register (IICiS0) and the I2Ci status register (IICiS1) until the bus
busy flag BB becomes “0” after generating the STOP condition in the master mode. It is because the
STOP condition waveform might not be normally generated. Reading to the above registers do not have
the problem.
Rev.1.00
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M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
2.12 A-D Converter
The A-D converter consists of one 8-bit successive approximation A-D converter circuit with a capacitive coupling
amplifier. Pins P102 to P107 also function as the analog signal input pins. The direction registers of these pins for AD conversion must therefore be set to input. The Vref connect bit (bit 5 at address 03D716) can be used to isolate the
resistance ladder of the A-D converter from the reference voltage (VREF) when the A-D converter is not used. Doing
so stops any current flowing into the resistance ladder from VREF, reducing the power dissipation. When using the AD converter, start A-D conversion only after setting bit 5 of 03D716 to connect VREF.
The result of A-D conversion is stored in the A-D registers of the selected pins.
Table 2.12.1 shows the performance of the A-D converter. Figure 2.12.1 shows the block diagram of the AD converter, and Figures 2.12.2 to 2.12.5 show the A-D converter-related registers.
Table 2.12.1 Performance of A-D converter
Item
Method of A-D conversion
Analog input voltage (Note 1)
Operating clock φAD (Note 2)
Resolution
Absolute precision
Performance
Successive approximation (capacitive coupling amplifier)
0V to VCCI
fAD/divide-by-2 of fAD/divide-by-4 of fAD, fAD=f(XIN)
8-bit
• Without sample and hold function: ±5 LSB
• With sample and hold function: ±5 LSB
Operating modes
One-shot mode, repeat mode, single sweep mode, repeat sweep mode 0,
and repeat sweep mode 1
Analog input pins
6 pins (AN0 to AN5)
A-D conversion start condition • Software trigger
A-D conversion starts when the A-D conversion start flag changes to “1”
Conversion speed per pin • Without sample and hold function
49 φAD cycles
• With sample and hold function
28 φAD cycles
Notes 1: Does not depend on use of sample and hold function.
2: Divide the frequency if f(XIN) exceeds 10 MHz, and make φAD frequency equal to 10 MHz. Without
sample and hold function, set the φAD frequency to 250kHz min.
With the sample and hold function, set the φAD frequency to 1MHz min.
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CKS1=1
φAD
CKS0=1
fAD
1/2
1/2
CKS0=0
CKS1=0
A-D conversion rate
selection
*Do not set CKS1=1 and CKS0=0.
(VCC) V REF
VCUT=0
Resistor ladder
VSS
VCUT=1
Successive conversion register
A-D control register 1 (address 03D7 16)
A-D control register 0 (address 03D6 16)
Addresses
(03C4 16)
(03C6 16)
A-D register 0(8)
A-D register 1(8)
(03C8 16)
A-D register 2(8)
(03CA 16)
A-D register 3(8)
(03CC16)
A-D register 4(8)
(03CE 16)
A-D register 5(8)
Vref
Decoder
V IN
Data bus high-order
Data bus low-order
AN0
CH2,CH1,CH0=010
AN1
CH2,CH1,CH0=011
AN2
CH2,CH1,CH0=100
AN3
CH2,CH1,CH0=101
AN4
CH2,CH1,CH0=110
AN5
CH2,CH1,CH0=111
Figure 2.12.1 Block diagram of A-D converter
Rev.1.00
May 18, 2004
page 147 of 296
Comparator
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
A-D control register 0 (Note 1)
b7
b6
b5
b4
b3
b2
b1
0
b0
Symbol
ADCON0
Bit symbol
Address
03D616
When reset
00000??? 2
Bit name
R W
Function
b2 b1 b0
Analog input pin select bit
CH0
CH1
CH2
(Note 2)
b4 b3
A-D operation mode
select bit 0
MD0
0 0 0 : Do not set
0 0 1 : Do not set
0 1 0 : AN 0 is selected
0 1 1 : AN 1 is selected
1 0 0 : AN 2 is selected
1 0 1 : AN 3 is selected
1 1 0 : AN 4 is selected
1 1 1 : AN 5 is selected
0 0 : One-shot mode
0 1 : Repeat mode
1 0 : Single sweep mode
1 1 : Repeat sweep mode 0
Repeat sweep mode 1
MD1
(Note 2)
Must always be set to “0”
Reserved bit
ADST
A-D conversion start flag
0 : A-D conversion disabled
1 : A-D conversion started
CKS0
Frequency select bit 0
0 : fAD/4 is selected
1 : fAD/2 is selected
(Note 3)
Notes 1: If the A-D control register is rewritten during A-D conversion, the conversion result is
indeterminate.
2: When changing A-D operation mode, set analog input pin again.
3: When selecting fAD/1, always be sure to set this bit to “1”. Also , if f(Xin) exceeds 10 MHz,
lower the φA-D frequency to 10 MHz or below by dividing it.
Figure 2.12.2 A-D control register 0
A-D control register 1 (Note 1)
b7
b6
b5
b4
0 0
b3
0
b2
b1
b0
Symbol
ADCON1
Bit symbol
Address
03D716
When reset
00 16
Bit name
A-D sweep pin select bit
SCAN0
RW
Function
When single sweep and repeat sweep
mode 0 are selected
b1 b0
0 0 : Do not set
0 1 : AN 0 and AN 1 (2 pins)
1 0 : AN 0 to AN 3 (4 pins)
1 1 : AN 0 to AN 5 (6 pins)
When repeat sweep mode 1 is selected
SCAN1
b1 b0
0 0 : Do not set
0 1 : Do not set
1 0 : AN 0 (1 pin)
1 1 : AN 0 and AN 1 (2 pins)
MD2
A-D operation mode
select bit 1
Reserved bit
CKS1
VCUT
0 : Any mode other than repeat sweep
mode 1
1 : Repeat sweep mode 1
Must always be set to “0”
Frequency select bit 1
0 : f AD/2 or f AD/4 is selected
1 : f AD is selected
Vref connect bit
0 : Vref not connected
1 : Vref connected
Reserved bits
(Note 2)
Must always be set to “0”
Notes 1: If the A-D control register is rewritten during A-D conversion, the conversion result is
indeterminate.
2: When selecting fAD/1, always be sure to set the A-D control register 0 bit 7 (CKS0) to “1”.
Also , if f(Xin) exceeds 10 MHz, lower the φA-D frequency to 10 MHz or below by dividing it.
Figure 2.12.3 A-D control register 1
Rev.1.00
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M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
A-D control register 2 (Note 1)
b7
b6
b5
b4
b3
b2
b1
b0
0 0 0 0 0 0 0
Symbol
Address
When reset
ADCON2
03D4 16
0000???0 2
Bit symbol
Bit name
A-D conversion method
select bit
SMP
RW
0 : Without sample and hold
1 : With sample and hold
Must always be set to “0”
Reserved bits
Reserved bits
Function
Must always be set to “0”
(Note 2)
Notes 1: If the A-D control register is rewritten during A-D conversion, the conversion
result is indeterminate.
2: The value of this bit when read is indeterminate.
Figure 2.12.4 A-D control register 2
A-D register i
Symbol
ADi(i=0 to 5)
b7
b0
Address
When reset
03C4 16, 03C6 16, 03C8 16 Indeterminate
03CA 16, 03CC 16, 03CE 16 Indeterminate
Function
Eight bits of A-D conversion result
Figure 2.12.5 A-D register i (i = 0 to 5)
Rev.1.00
May 18, 2004
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R W
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
2.12.1 One-shot Mode
In one-shot mode, the pin selected using the analog input pin select bit is used for one-shot A-D conversion. Table 2.12.2 shows the specifications of one-shot mode. Figures 2.12.6 and 2.12.7 show the A-D
control register in one-shot mode.
Table 2.12.2 One-shot mode specifications
Item
Function
Start condition
Stop condition
Interrupt request generation timing
Input pin
Reading of result of A-D converter
Rev.1.00
May 18, 2004
Specification
The pin selected by the analog input pin select bit is used for one A-D conversion
Writing “1” to A-D conversion start flag
• End of A-D conversion
• Writing “0” to A-D conversion start flag
End of A-D conversion
One of AN0 to AN5, as selected
Read A-D register corresponding to selected pin
page 150 of 296
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
A-D control register 0 (Note 1)
b7
b6
b5
b4
b3
b2
b1
b0
0 0 0
Symbol
ADCON0
Bit symbol
Address
03D616
When reset
00000??? 2
Bit name
CH0
Function
Analog input pin select
bit
b2 b1 b0
A-D operation mode
select bit 0
b4 b3
0 0 0 : Do not set
0 0 1 : Do not set
0 1 0 : AN 0 is selected
0 1 1 : AN 1 is selected
1 0 0 : AN 2 is selected
1 0 1 : AN 3 is selected
1 1 0 : AN 4 is selected
1 1 1 : AN 5 is selected
CH1
CH2
MD0
MD1
0 0 : One-shot mode
Reserved bit
RW
(Note 2)
(Note 2)
Must always be set to “0”
ADST
A-D conversion start flag
0 : A-D conversion disabled
1 : A-D conversion started
CKS0
Frequency select bit 0
0: f AD/4 is selected
1: f AD/2 is selected
(Note 3)
Notes 1: If the A-D control register is rewritten during A-D conversion, the conversion
result is indeterminate.
2: When changing A-D operation mode, it is necessary to set analog input pins
again.
3: When selecting fAD/1, always be sure to set this bit to “1”. Also , if f(Xin) exceeds
10 MHz, lower the φA-D frequency to 10 MHz or below by dividing it.
Figure 2.12.6 A-D control register 0 in one-shot mode
A-D control register 1 (Note 1)
b7
b6
b5
0 0 1
b4
b3
b2
0
0
b1
b0
Symbol
ADCON1
Bit symbol
SCAN0
Address
03D716
When reset
0016
Bit name
Function
RW
A-D sweep pin
select bit
Invalid in one-shot mode
A-D operation mode
select bit 1
0 : Any mode other than repeat sweep
mode 1
SCAN1
MD2
Reserved bit
Must always be set to “0”
CKS1
Frequency select bit1
0 : f AD/2 or fAD/4 is selected
1 : f AD is selected
VCUT
Vref connect bit
1 : Vref connected
Reserved bits
(Note 2)
Must always be set to “0”
Notes 1: If the A-D control register is rewritten during A-D conversion, the conversion result
is indeterminate.
2: When selecting fAD/1, always be sure to set the A-D control register 0 bit 7 (CKS0) to “1”.
Also , if f(Xin) exceeds 10 MHz, lower the φA-D frequency to 10 MHz or below by dividing it.
Figure 2.12.7 A-D control register 1 in one-shot mode
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2.12.2 Repeat Mode
In repeat mode, the pin selected using the analog input pin select bit is used for repeated A-D conversion.
Table 2.12.3 shows the specifications of repeat mode. Figures 2.12.8 and 2.12.9 show the A-D control
register in repeat mode.
Table 2.12.3 Repeat mode specifications
Item
Function
Star condition
Stop condition
Interrupt request generation timing
Input pin
Reading of result of A-D converter
Rev.1.00
May 18, 2004
Specification
The pin selected by the analog input pin select bit is used for repeated A-D conversion
Writing “1” to A-D conversion start flag
Writing “0” to A-D conversion start flag
None generated
One of AN0 to AN5, as selected
Read A-D register corresponding to selected pin
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A-D control register 0 (Note 1)
b7
b6
b5
b4
b3
b2
b1
b0
0 0 1
Symbol
ADCON0
Bit symbol
CH0
Address
03D6 16
Bit name
Analog input pin
select bit
CH1
CH2
MD0
MD1
When reset
00000??? 2
A-D operation mode
select bit 0
Function
RW
b2 b1 b0
0 0 0 : Do not set
0 0 1 : Do not set
0 1 0 : AN 0 is selected
0 1 1 : AN 1 is selected
1 0 0 : AN 2 is selected
1 0 1 : AN 3 is selected
1 1 0 : AN 4 is selected
1 1 1 : AN 5 is selected
(Note 2)
b4 b3
0 1 : Repeat mode
(Note 2)
Must always be set to “0”
Reserved bit
ADST
A-D conversion start flag
0 : A-D conversion disabled
1 : A-D conversion started
CKS0
Frequency select bit 0
0 : f AD/4 is selected
1 : f AD/2 is selected
(Note 3)
Notes 1: If the A-D control register is rewritten during A-D conversion, the conversion result is
indeterminate.
2: When changing A-D operation mode, it is necessary to set analog input pins again.
3: When selecting fAD/1, always be sure to set this bit to “1”. Also , if f(Xin) exceeds 10 MHz,
lower the φA-D frequency to 10 MHz or below by dividing it.
Figure 2.12.8 A-D conversion register 0 in repeat mode
A-D control register 1 (Note 1)
b7
b6
b5
0 0 1
b4
b3
b2
0 0
b1
b0
Symbol
ADCON1
Bit symbol
SCAN0
Address
03D7 16
When reset
00 16
Bit name
Function
RW
A-D sweep pin
select bit
Invalid in repeat mode
A-D operation mode
select bit 1
0 : Any mode other than repeat sweep mode 1
SCAN1
MD2
Reserved bit
Must always be set to “0”
CKS1
Frequency select bit 1
0 : f AD/2 or f AD/4 is selected
1 : f AD is selected
VCUT
Vref connect bit
1 : Vref connected
Reserved bits
(Note 2)
Must always be set to “0”
Notes 1: If the A-D control register is rewritten during A-D conversion, the conversion result is
indeterminate.
2: When selecting fAD/1, always be sure to set the A-D control register 0 bit 7 (CKS0) to “1”.
Also , if f(Xin) exceeds 10 MHz, lower the φA-D frequency to 10 MHz or below by dividing it.
Figure 2.12.9 A-D conversion register 1 in repeat mode
Rev.1.00
May 18, 2004
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2.12.3 Single Sweep Mode
In single sweep mode, the pins selected using the A-D sweep pin select bit are used for one-by-one A-D
conversion. Table 2.12.4 shows the specifications of single sweep mode. Figures 2.12.10 and 2.12.11
show the A-D control register in single sweep mode.
Table 2.12.4 Single sweep mode specifications
Item
Function
Start condition
Stop condition
Interrupt request generation timing
Input pin
Reading of result of A-D converter
Rev.1.00
May 18, 2004
Specification
The pins selected by the A-D sweep pin select bit are used for one-by-one A-D conversion
Writing “1” to A-D converter start flag
• End of A-D conversion
• Writing “0” to A-D conversion start flag
End of A-D conversion
AN0 and AN1 (2 pins), AN0 to AN3 (4 pins), AN0 to AN5 (6 pins)
Read A-D register corresponding to selected pin
page 154 of 296
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
A-D control register 0 (Note 1)
b7
b6
b5
b4
b3
b2
b1
b0
0 1 0
Symbol
ADCON0
Bit symbol
CH0
Address
03D616
When reset
00000??? 2
Bit name
Function
Analog input pin
select bit
Invalid in single sweep mode
A-D operation mode
select bit 0
1 0 : Single sweep mode
RW
CH1
CH2
MD0
b4 b3
MD1
Reserved bit
Must always be set to “0”
ADST
A-D conversion start flag
0 : A-D conversion disabled
1 : A-D conversion started
CKS0
Frequency select bit 0
0 : f AD/4 is selected
1 : f AD/2 is selected
(Note 2)
Notes 1: If the A-D control register is rewritten during A-D conversion, the conversion result is
indeterminate.
2: When changing A-D operation mode, set analog input pin again.
3: When selecting fAD/1, always be sure to set this bit to “1”. Also , if f(Xin) exceeds 10 MHz,
lower the φA-D frequency to 10 MHz or below by dividing it.
Figure 2.12.10 A-D control register 0 in single sweep mode
A-D control register 1 (Note 1)
b7
b6
b5
0 0 1
b4
b3
b2
0 0
b1
b0
Symbol
ADCON1
Address
03D7 16
Bit symbol
SCAN0
When reset
00 16
Bit name
A-D sweep pin select bit
Function
R W
When single sweep and repeat sweep mode 0
are selected
b1 b0
0 0 : Do not set
0 1 : AN 0 and AN 1 (2 pins)
1 0 : AN 0 to AN 3 (4 pins)
1 1 : AN 0 to AN 5 (6 pins)
SCAN1
MD2
A-D operation mode
select bit 1
Reserved bit
0 : Any mode other than repeat sweep mode 1
Must always be set to “0”
CKS1
Frequency select bit 1
0 : f AD/2 or f AD/4 is selected
1 : f AD is selected
VCUT
Vref connect bit
1 : Vref connected
Reserved bits
(Note 2)
Must always be set to “0”
Notes 1: If the A-D control register is rewritten during A-D conversion, the conversion result is
indeterminate.
2: When selecting fAD/1, always be sure to set the A-D control register 0 bit 7 (CKS0) to “1”.
Also , if f(Xin) exceeds 10 MHz, lower the φA-D frequency to 10 MHz or below by dividing it.
Figure 2.12.11 A-D control register 1 in single sweep mode
Rev.1.00
May 18, 2004
page 155 of 296
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
2.12.4 Repeat Sweep Mode 0
In repeat sweep mode 0, the pins selected using the A-D sweep pin select bit are used for repeat sweep
A-D conversion. Table 2.12.5 shows the specifications of repeat sweep mode 0. Figures 2.12.12 and
2.12.13 show the A-D control register in repeat sweep mode 0.
Table 2.12.5 Repeat sweep mode 0 specifications
Item
Function
Start condition
Stop condition
Interrupt request generation timing
Input pin
Reading of result of A-D converter
Rev.1.00
May 18, 2004
Specification
The pins selected by the A-D sweep pin select bit are used for repeat sweep A-D conversion
Writing “1” to A-D conversion start flag
Writing “0” to A-D conversion start flag
None generated
AN0 and AN1 (2 pins), AN0 to AN3 (4 pins), AN0 to AN5 (6 pins)
Read A-D register corresponding to selected pin (at any time)
page 156 of 296
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
A-D control register 0 (Note 1)
b7
b6
b5
b4
0
1 1
b3
b2
b1
b0
Symbol
ADCON0
Address
03D6 16
Bit symbol
CH0
When reset
00000??? 2
Bit name
Analog input pin
select bit
Function
RW
Invalid in repeat sweep mode 0
CH1
CH2
MD0
A-D operation mode
select bit 0
b4 b3
1 1 : Repeat sweep mode 0
MD1
Reserved bit
Must always be set to “0”
ADST
A-D conversion start flag
0 : A-D conversion disabled
1 : A-D conversion started
CKS0
Frequency select bit 0
0 : f AD/4 is selected
1 : f AD/2 is selected
(Note 2)
Notes 1: If the A-D control register is rewritten during A-D conversion, the conversion result is
indeterminate.
2: When changing A-D operation mode, set analog input pin again.
3: When selecting fAD/1, always be sure to set this bit to “1”. Also , if f(Xin) exceeds 10 MHz,
lower the φA-D frequency to 10 MHz or below by dividing it.
Figure 2.12.12 A-D control register 0 in repeat sweep mode 0
A-D control register 1 (Note 1)
b7
b6
b5
0 0 1
b4
b3
b2
0
0
b1
b0
Symbol
ADCON1
Address
03D7 16
Bit symbol
SCAN0
When reset
0016
Bit name
A-D sweep pin select bit
Function
R W
When single sweep and repeat sweep mode 0
are selected
b1 b0
0 0 : Do not set
0 1 : AN 0 and AN 1 (2 pins)
1 0 : AN 0 to AN 3 (4 pins)
1 1 : AN 0 to AN 5 (6 pins)
SCAN1
MD2
A-D operation mode
select bit 1
Reserved bit
0 : Any mode other than repeat sweep mode 1
Must always be set to “0”
CKS1
Frequency select bit 1
0 : f AD/2 or f AD/4 is selected
1 : f AD is selected
VCUT
Vref connect bit
1 : Vref connected
Reserved bits
(Note 2)
Must always be set to “0”
Notes 1: If the A-D control register is rewritten during A-D conversion, the conversion result is
indeterminate.
2: When selecting fAD/1, always be sure to set the A-D control register 0 bit 7 (CKS0) to “1”.
Also , if f(Xin) exceeds 10 MHz, lower the φA-D frequency to 10 MHz or below by dividing it.
Figure 2.12.13 A-D control register 1 in repeat sweep mode 0
Rev.1.00
May 18, 2004
page 157 of 296
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
2.12.5 Repeat Sweep Mode 1
In repeat sweep mode 1, all pins are used for A-D conversion with emphasis on the pin or pins selected
using the A-D sweep pin select bit. Table 2.12.6 shows the specifications of repeat sweep mode 1.
Figures 2.12.14 and 2.12.15 show the A-D control register in repeat sweep mode 1.
Table 2.12.6 Repeat sweep mode 1 specifications
Item
Function
Start condition
Stop condition
Interrupt request generation timing
Input pin
Reading of result of A-D converter
Specification
All pins perform repeat sweep A-D conversion, with emphasis on the pin or
pins selected by the A-D sweep pin select bit
Example : AN0 selected AN0
AN1
AN0
AN2
AN0
AN3, etc
Writing “1” to A-D conversion start flag
Writing “0” to A-D conversion start flag
None generated
AN0 (1 pin), AN0 and AN1 (2 pins)
Read A-D register corresponding to selected pin (at any time)
A-D control register 0 (Note 1)
b7
b6
b5
b4
b3
b2
0 1 1
b1
b0
Symbol
ADCON0
Bit symbol
CH0
Address
03D616
When reset
00000??? 2
Bit name
Analog input pin
select bit
Function
RW
Invalid in repeat sweep mode 1
CH1
CH2
MD0
A-D operation mode
select bit 0
b4 b3
1 1 : Repeat sweep mode 1
MD1
Reserved bit
Must always be set to “0”
ADST
A-D conversion start flag
0 : A-D conversion disabled
1 : A-D conversion started
CKS0
Frequency select bit 0
0 : f AD/4 is selected
1 : f AD/2 is selected
(Note 2)
Notes 1: If the A-D control register is rewritten during A-D conversion, the conversion result is
indeterminate.
2: When changing A-D operation mode, set analog input pin again.
3: When selecting fAD/1, always be sure to set this bit to “1”. Also , if f(Xin) exceeds 10 MHz,
lower the φA-D frequency to 10 MHz or below by dividing it.
Figure 2.12.14 A-D control register 0 in repeat sweep mode 1
Rev.1.00
May 18, 2004
page 158 of 296
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
A-D control register 1 (Note 1)
b7
b6
b5
0 0 1
b4
b3
b2
0 1
b1
b0
Symbol
ADCON1
Address
03D7 16
Bit symbol
Bit name
SCAN0
A-D sweep pin select bit
When reset
00 16
Function
R W
When repeat sweep mode 1 is selected
b1 b0
0 0 : Do not set
0 1 : Do not set
1 0 : AN 0 (1 pin)
1 1 : AN 0 and AN 1 (2 pins)
SCAN1
MD2
A-D operation mode
select bit 1
Reserved bit
1 : Repeat sweep mode 1
Must always be set to “0”
CKS1
Frequency select bit 1
0 : f AD/2 or f AD/4 is selected
1 : f AD/1 is selected
VCUT
Vref connect bit
1 : Vref connected
Reserved bits
(Note 2)
Must always be set to “0”
Notes 1: If the A-D control register is rewritten during A-D conversion, the conversion result is
indeterminate.
2: When selecting fAD/1, always be sure to set the AD control Register 0 bit 7 (CKS0) to “1”.
Also , if f(Xin) exceeds 10 MHz, lower the φA-D frequency to 10 MHz or below by dividing it.
Figure 2.12.15 A-D control register 1 in repeat sweep mode 1
Rev.1.00
May 18, 2004
page 159 of 296
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
2.12.6 Sample and Hold
Sample and hold is selected by setting bit 0 of the A-D control register 2 (address 03D416) to “1”. When
sample and hold is selected, the rate of conversion of each pin increases. As a result, a 28 φAD cycle is
achieved. Sample and hold can be selected in all modes. However, in all modes, be sure to specify before
starting A-D conversion whether sample and hold is to be used.
Rev.1.00
May 18, 2004
page 160 of 296
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
2.13 D-A Converter
This is an 8-bit, R-2R type D-A converter. The microcomputer contains two independent D-A converters of
this type.
D-A conversion is performed when a value is written to the corresponding D-A register. Bits 0 and 1 (D-A
output enable bits) of the D-A control register decide if the result of conversion is to be output. Do not set the
target port to output mode if D-A conversion is to be performed.
Output analog voltage (V) is determined by a set value (n : decimal) in the D-A register.
V = VREF X n/ 256 (n = 0 to 255)
VREF : reference voltage
Table 2.13.1 lists the performance of the D-A converter. Figure 2.13.1 shows the block diagram of the D-A
converter. Figure 2.13.2 shows the A-D control register, Figure 2.13.3 shows the D-A register and Figure
2.13.4 shows the D-A converter equivalent circuit.
Table 2.13.1 Performance of D-A converter
Item
Conversion method
Resolution
Analog output pin
Performance
R-2R method
8 bits
2 channels
Data bus low-order bits
D-A register0 (8)
(Address 03D816)
D-A0 output enable bit
R-2R resistor ladder
D-A register1 (8)
P93/DA0
(Address 03DA16)
D-A1 output enable bit
R-2R resistor ladder
Figure 2.13.1 Block diagram of D-A converter
Rev.1.00
May 18, 2004
page 161 of 296
P94/DA1
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
D-A control register
b7
b6
b5
b4
b3
b2
b1
Symbol
DACON
b0
Address
03DC 16
Bit symbol
When reset
00 16
Bit name
Function
DA0E
D-A0 output enable bit
0 : Output disabled
1 : Output enabled
DA1E
D-A1 output enable bit
0 : Output disabled
1 : Output enabled
RW
Nothing is assigned.
In an attempt to write to these bits, write “0.” The value, if read, turns out to be “0.”
Figure 2.13.2 D-A control register
D-A register i (i = 0, 1)
b7
Symbol
DAi (i = 0,1)
b0
Address
03D8 16, 03DA 16
When reset
Indeterminate
Function
R
RW
W
Output value of D-A conversion
Note: When not using D-A conversion, set the value 0016 in this register.
Figure 2.13.3 D-A register i (i = 0 and 1)
D-A0 output enable bit
"0"
R
R
R
R
2R
2R
2R
2R
R
R
R
2R
DA0
"1"
2R
MSB
2R
2R
2R
LSB
D-A0 register0
VSS
VCCI(VREF)
Note 1: The above diagram shows an instance in which the D-A register is assigned 2A 16.
2: The same circuit as this is also used for D-A1.
3: To reduce the current consumption when the D-A converter is not used, set the D-A output enable bit to 0 and set the D-A register to
0016 so that no current flows in the resistors Rs and 2Rs.
Figure 2.13.4 D-A converter equivalent circuit
Rev.1.00
May 18, 2004
page 162 of 296
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
2.14 Data Slicer
This microcomputer includes the data slicer function for the closed caption decoder (referred to as the
CCD) and video ID (referred to as the ID1). This function takes out CC and ID1 (note 2) superimposed in the
vertical blanking interval of a composite video signal. A composite video signal which makes the sync. tip’s
polarity negative is input to the CVIN pin.
When the data slicer function is not used, the data slicer circuit and the timing signal generating circuit can
be cut off by setting bit 0 of the data slicer control register 1 (address 026016/030016) to “0.” These settings
can realize the low-power dissipation.
Notes 1. When using the data slicer, set bit 7 of the peripheral mode register (address 027D16) according
to the main clock frequency.
2. 525i/p:ID1 data slice can be performed. No CC data slice at 525p.
3. When there is no specification, it becomes the publication about 525i below.
0.1 µF
Composite video
signal
Input amplitude = 1.75 Vpp
470 Ω
Note 2 (P164)
680 pF
1 MΩ
1 kΩ
2.2 µF
200 pF
Note 1 (P164)
HSYNC
CVIN
HLF
Synchronizing
signal counter
Clamping
circuit
ID1 reserved register
(address 026116/030116)
1 1
Low-pass
filter
Synchronizing
separation
circuit
Sync slice
circuit
Timing signal
generating
circuit
VHOLD
Reference
voltage
generating
1000 pF circuit
+
Comparator 1
Data slicer control register 1
(address 026016/030016)
–
Note : Make the length of wiring which is
connected to VHOLD, HLF, and CVIN pin
as short as possible so that a leakage
current may not be generated when
mounting a resistor or
a capacitor on each pin.
Internal absolute
standard voltage
generating
circuit
Clock run-in
determination
circuit
+
–
Start bit detecting
circuit
ID1 reference
detection circuit
Data clock
generating circuit
Data clock position register
(address 026A16/030A16)
Data register
control circuit
ID1 data clock
generating circuit
CRCC data register
(addresses 026D16 and 030D16)
Caption position register
(address 026616/030616)
Clock run-in detect
register
(address 026916/030916)
Comparator 2
ID1 reference
judgment circuit
Standard clock detection register
(addresses 026C16 and 030C16)
Data slice line
specification
circuit
Address 026716
b1, b0
control circuit
External circuit
1 0 0
ID1 control register
(addresses 026B16 and 030B16)
Data slicer control register 2
(address 026116/030116)
Interrupt request
generating circuit
Caption register 2
(addresses 026516 and 026416/
030516 and 030416)
Data slicer
interrupt
request
Caption register 1
(addresses 026316 and 026216/
030316 and 030216)
Data bus
0 0 0 0 0 0 0 0
Data slicer reserved register 1
(addresses 026816 and 030816)
0
Reserved register
(addresses 026F16 and 030F16)
Figure 2.14.1 Data slicer block diagram
Rev.1.00
May 18, 2004
page 163 of 296
1 0 1 0 0 0 0 0
Test reserved register 0
(addresses 026E16)
0 0 0 0 0 0 0 0
Test reserved register 1
(addresses 030E16)
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
Notes 1 : Set up the amplitude inputted from CVIN pin to satisfy the following conditions.
(1) Set up as below :
input amplitude + synchronized chip clamp potential < VCCi + 0.3 V.
Vcci shows Vcci power supply pin voltage.
Sink tip clamp pin serves as (43/120) x VCCi .
Example) In the case of VCCi = 3.3V input amplitude = 2.0V
2.0V + 1.18 V = 3.18 V < 3.6 V = 3.3 V + 0.3 V
(2) Each signal level to input amplitude of CVIN pin is shown in Figure 2.14.2.
White level
ID1 data
max
A : 140 IRE = CVIN input amplitude
D : 70IRE
CC data
max
B : 50IRE
Pedestal
C : 40IRE
synchronized
chip
Example) When it inputs by 1.75Vpp(s) from CVIN pin, each level becomes the following.
A = 140 IRE = 1.75 V
B = 50 IRE = 1.75 x (50/140) = 0.625 V
C = 40 IRE = 1.75 x (40/140) = 0.5 V
D = 70 IRE = 1.75 x (70/140) = 0.875 V
Figure 2.14.2 Each signal level to input amplitude of CVIN pin
Notes 2 : External each constant shown in Figure 2.14.1 is an example, and is greatly influenced by video
signal output impedance, substrate capacity, etc. on a system. Evaluate input amplitude and
external each constant perfectly, and determine it.
2.14.1 Notes when not Using Data Slicer
When bit 0 of data slicer control register 1 (address 026016/030016) is “0,” terminate the pins as shown in
Figure 2.14.3
<When data slicer circuit and timing signal generating circuit is in OFF state>
HLF/HLF2
Pull-down HLF pin and VHOLD pin to
Vss through a resistor of 5 kΩ or more.
VHOLD/VHOLD2
VCCI
5 kΩ or more
Pull-up CVIN pin to Vcc through
a resistor of 5 kΩ or more.
CVIN/CVIN2
Figure 2.14.3 Termination of data slicer input/output pins when data slicer circuit and timing
generating circuit is in OFF state
Rev.1.00
May 18, 2004
page 164 of 296
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
Figures 2.14.4 and 2.14.5 the data slicer control registers.
Data slicer control register 1
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0 0 0
Symbol
Address
When reset
DSC01
DSC11
026016
030016
0016
00 16
Bit symbol
Bit name
Data slicer and timing signal
generating circuit control bit
DSC010/
DSC110
DSC011/
DSC111
Selection bit of data slice reference
voltage generating field
DSC012/
DSC112
Reference clock source
selection bit
Function
R W
0: Stopped (Set at slicer unused)
1: Operating (Set at slicer used)
0: F2
1: F1
At two lines: CC21, and CCX or ID1 are sliced
(notes 1 and 2)
1: Select F1, normally
At only ID1 is sliced
0/1: Select either (note 3)
525p:When ID1 data slice
X:This bit setting is invalid.
0: Video signal (Set “0”, normally)
1: H SYNC signal
Reserved bits
Must always be set to “0”
Notes 1. Selected by addresses 026616, 026B16, 030616 and 030B16 register setting.
2. When ID1 slice is set, addresses 026B16 and 030B16 are need to be set.
3. It is required to superimpose F1 and F2 on the same data.
4. CC21: line 21data of CC format.
CCX: the line data which can be selected by addresses 026616 and 030616 of CC format.
ID1: ID1 format data.
Definition of fields 1 (F1) and 2 (F2)
F1: Hsep
Vsep
F2: Hsep
Vsep
Figure 2.14.4 Data slicer control register 1
Data slicer control register 2
b7 b6 b5 b4 b3 b2 b1 b0
0
0
Symbol
DSC02
DSC12
Bit symbol
DSC020/
DSC120
Address
026116
030116
When reset
?0?0??0?2
?0?0??0?2
Function
Bit name
Caption data latch
completion flag 1
When two lines of CC21 and CCX are sliced,
0: Incompletion of CC21 caption data latch, or no clock run-in.
1: Completion of CC21 caption data latch, and clock run-in.
When only CCX is sliced,
0: Incompletion of CCX caption data latch, or no clock run-in.
1: Completion of CCX caption data latch, and clock run-in.
When only ID1 is sliced,
0: Incompletion of ID1 caption data latch.
1: Completion of ID1 caption data latch.
note: A flag is reset by 0 in falling of vertical synchronized signal.
Reserved bit
Must always be set to “0”
Test bit
Read-only
DSC023/
DSC123
Field determination flag
0: F2
1: F1
(*)This flag is invalid at 026B16 and 030B16 at the time of 525p selection.
DSC024/
DSC124
Vertical synchronous signal
(Vsep) generating method
selection bit
0: Method (1)
1: Method (2)
DSC025/
DSC125
V-pulse shape
determination flag
0: Match
1: Mismatch
Reserved bit
Must always be set to “0”
Test bit
Read-only
Definition of fields 1 (F1) and 2 (F2)
F1: Hsep
Vsep
F2: Hsep
Vsep
Figure 2.14.5 Data slicer control register 2
Rev.1.00
May 18, 2004
page 165 of 296
R W
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
2.14.2 Clamping Circuit and Low-pass Filter
The clamp circuit clamps the sync. tip part of the composite video signal input from the CVIN pin. The lowpass filter attenuates the noise of clamped composite video signal. The CVIN pin to which composite video
signal is input requires a capacitor (0.1 µF) coupling outside. Pull down the CVIN pin with a resistor of
hundreds of kiloohms to 1 MΩ. In addition, we recommend to install externally a simple low-pass filter
using a resistor and a capacitor at the CVIN pin (refer to Figure 2.14.1 and notes).
2.14.3 Sync Slice Circuit
This circuit takes out a composite sync signal from the output signal of the low-pass filter.
Set bit 6 and 7 to 11b of ID1 reserved register (addresses 037C16 and 031D16) show in Fig 2.14.21.
2.14.4 Synchronous Signal Separation Circuit
This circuit separates a horizontal synchronous signal and a vertical synchronous signal from the composite sync signal taken out in the sync slice circuit.
(1) Horizontal synchronous signal (Hsep)
A one-shot horizontal synchronizing signal Hsep is generated at the falling edge of the composite sync
signal.
(2) Vertical synchronous signal (Vsep)
As a Vsep signal generating method, it is possible to select one of the following 2 methods by using bit
4 of the data slicer control register 2 (address 026116/030116).
•Method 1 The “L” level width of the composite sync signal is measured. If this width exceeds a
certain time, a Vsep signal is generated in synchronization with the rising of the timing
signal immediately after this “L” level.
•Method 2 The “L” level width of the composite sync signal is measured. If this width exceeds a
certain time, it is detected whether a falling of the composite sync signal exits or not in the
“L” level period of the timing signal immediately after this “L” level. If a falling exists, a Vsep
signal is generated in synchronization with the rising of the timing signal (refer to Figure
2.14.6).
Figure 2.14.6 shows a Vsep generating timing. The timing signal shown in the figure is generated from the
reference clock which the timing generating circuit outputs.
Reading bit 5 of data slicer control register 2 permits determinating the shape of the V-pulse portion of the
composite sync signal. As shown in Figure 2.14.7, when the A level matches the B level, this bit is “0.” In
the case of a mismatch, the bit is “1.”
Composite sync
Bit 5 of
DSC02/DSC12
“L” level width is measured
Timing
signal
0
“L” level period of a timing signal
Composite
sync signal
1
Vsep signal
1
A Vsep signal is generated at a rising of the timing signal
immediately after the “L” level width of the composite
sync signal exceeds a certain time.
Figure 2.14.6 Vsep generating timing (method 2)
Rev.1.00
May 18, 2004
page 166 of 296
A
B
Figure 2.14.7 Determination of v-pulse waveform
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
2.14.5 Timing Signal Generating Circuit
This circuit generates a reference clock which is 832 times as large as the horizontal synchronous signal
frequency. It also generates various timing signals on the basis of the reference clock, horizontal synchronous signal and vertical synchronizing signal. The circuit operates by setting bit 0 of data slicer
control register 1 (address 026016/030016) to “1.”
The reference clock is the HSYNC signal can be used as a count source instead of the composite sync
signal. However, when the HSYNC signal is selected, the data slicer cannot be used. A count source of the
reference clock can be selected by bit 2 of data slicer control register 1 (address 026016/030016).
For the pins HLF, connect a resistor and a capacitor as shown in Figure 2.14.1 Make the length of wiring
which is connected to these pins as short as possible so that a leakage current may not be generated.
Note: It takes a few tens of milliseconds until the reference clock becomes stable after the data slicer and
the timing signal generating circuit are started. In this period, various timing signals, Hsep signals
and Vsep signals become unstable. For this reason, take stabilization time into consideration
when programming.
Rev.1.00
May 18, 2004
page 167 of 296
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
2.14.6 Data Slice Line Specification Circuit
(1) Specification of data slice line
This circuit decides a line on which caption data is superimposed. The line 21 (fixed), 1 appropriate
line for a period of 1 field (total 2 line for a period of 1 field), and both fields (F1 and F2) are sliced their
data. The caption position register (address 026616/030616) is used for each setting (refer to Table
2.14.1).
The counter is reset at the falling edge of Vsep and is incremented by 1 every Hsep pulse. When the
counter value matched the value specified by bits 4 to 0 of the caption position register, this Hsep is
sliced.
The values of “0016” to “1F16” can be set in the caption position register (at setting only 1 appropriate
line, refer to Table 2.14.1). Figure 2.14.8 shows the signals in the vertical blanking interval. Figure
2.14.9 shows the caption position register.
When slice ID1, set bits 0 to 4 of addresses 026616 and 030616 = 10000b.
525p:When ID1 data slice, set up addresses 026616/030616 bit 4-0 = 00001b and the data clock
position register (addresses 026A16 and 030A16) bit 6, and 5 = 01b.
(2) Specification of line to set slice voltage
When slice CC21 and CCX, the reference voltage for slicing (slice voltage) is generated for the clock
run-in pulse in the particular line (refer to Table 2.14.1). The field to generate slice voltage is specified
by bit 1 of data slicer control register 1. The line to generate slice voltage 1 field is specified by bits 6,
7 of the caption position register (refer to Table 2.14.1).
When slice ID1, set bit 6 and 7 of addresses 026616 and 030616 = 00b or 01b.
525p:When ID1 data slice, set up the addresses 026616 and 030616 bit 7 and 6 = 01b.
(3) Field determination
The field determination flag can be read out by bit 3 of data slicer control register 2. This flag change
at the falling edge of Vsep.
525p:When ID1 data slice, this bit setting is invalid.
Vertical blanking interval
Video signal
Composite video
signal
1 appropriate line is set by
the caption position register
Line 21
(when setting line 19)
Vsep
Hsep
Count value to be set in the caption position register (“0F16” in this case)
Hsep
Clock run-in
S
T
B
Composite video
signal
Window for
deteminating
clock-run-in
Figure 2.14.8 Signals in vertical blanking interval
Rev.1.00
May 18, 2004
page 168 of 296
C
C
1
C
C
2
..........
C C
C C
15 16
*STB shows start bit.
CC1 to 16 show CC data.
Magnified drawing
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
Caption position register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
CPS0
CPS1
Bit symbol
Address
026616
030616
When reset
00?000002
00?00000 2
Bit name
CPS00/CPS10 Caption position bits
CPS01/CPS11
CPS02/CPS12
CPS03/CPS13
CPS04/CPS14
CPS05/CPS15 Caption data latch
completion flag 2
Function
R W
Set caption position (CCX or ID1).
For CCX, refer to Table 2.14.1.
For ID1 slice, set bits 0 to 4 = 10000b (select 20)
525p:When ID1 data slice,
set up bit 4-0 = 00001b (line 41 selection).
(*) addresses 026A16 and 030A16
bit 6 and 5 = 01b need to be set up.
When two lines of CC21 and CCX are sliced,
0: Incompletion of CCX caption data latch, or no clock run-in.
1: Completion of CCX caption data latch, and clock run-in.
When two lines of CC21 and ID1 are sliced,
0: Incompletion of ID1 caption data latch.
1: Completion of ID1 caption data latch.
This bit is invalid when slice only any one line of CC21,
CCX and ID1.
note: A flag is reset by 0 in rising of vertical synchronized signal.
CPS06/CPS16 Slice line mode
specification bits
CPS07/CPS17 (in 1 field)
Refer to table 2.14.1 at slice CC21 or CCX.
Set bits 6 and 7 = 00b or 01b when ID1 slice.
525p:When ID1 data slice, set bit 7 and 6 = 01b.
Figure 2.14.9 Caption position register
Table 2.14.1 Specification of data slice line
CPS0/CPS1
Field and Line to Generate Slice Voltage
Field and Line to Be Sliced Data
b7
b6
0
0
• Both fields of F1 and F2
• Line 21 and a line specified by bits 4 to 0 of CPS0/
CPS1 (total 2 lines) (See note 2)
• Field specified by bit 1 of DSC01/DSC11
• Line 21 (total 1 line)
0
1
• Both fields of F1 and F2
• A line specified by bits 4 to 0 of CPS0/CPS1
(total 1 line) (See note 3)
• Field specified by bit 1 of DSC01/DSC11
• A line specified by bits 4 to 0 of CPS0/CPS1
(total 1 line) (See note 3)
1
0
• Both fields of F1 and F2
• Line 21 (total 1 line)
• Field specified by bit 1 of DSC01/DSC11
• Line 21 (total 1 line)
1
1
• Both fields of F1 and F2
• Line 21 and a line specified by bits 4 to 0 of CPS0/
CPS1 (total 2 lines) (See note 2)
• Field specified by bit 1 of DSC01/DSC11
• Line 21 and a line specified by bits 4 to 0 of CPS0/
CPS1 (total 2 lines) (See note 2)
Notes 1: DSC01/DSC11 is data slicer control register 1.
CPS0/CPS1 is caption position register.
2: Set the value of “0016” – “1016” to bits 4 to 0 of CPS0/CPS1.
3: Set the value of “0016” – “1F16” to bits 4 to 0 of CPS0/CPS1.
Slice standard voltage selection register
b7 b6 b5 b4 b3 b2 b1 b0
0
0
0
0
0
0
Symbol
SBV0
SBV1
Bit symbol
SVB00/SVB10
SVB01/SVB11
Reserved bits
Address
26716
30716
When reset
0016
0016
Bit name
Slice standard voltage
selection bit
Function
b1, b0
0
0
0
1
1
0
1
1
Must be set to “0.”
Figure 2.14.10 Slice standard voltage selection register
Rev.1.00
May 18, 2004
page 169 of 296
Standard voltage selection by standard voltage
generating circuit.
Internal absolute standard voltage selection.
CC21 is the voltage by the standard voltage generating
circuit. CCX or ID1 is internal absolute standard voltage
selection.
Do not set
R W
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
2.14.7 Reference Voltage Generating Circuit and Comparator
The composite video signal clamped by the clamping circuit is input to the reference voltage generating
circuit and the comparator 1 and 2.
(1) Reference voltage generating circuit
This circuit generates a reference voltage (slice voltage) by using the amplitude of the clock run-in
pulse in line specified by the data slice line specification circuit. Connect a capacitor between the
VHOLD pin and the VSS pin, and make the length of wiring as short as possible so that a leakage
current may not be generated.
Note: It takes a few tens of lines to generate slice voltage until the slice voltage becomes stable after
the data slicer is started. In this period, the slice data becomes unstable. For this reason, take
stabilization time into consideration when programming.
(2) Comparator 1
The comparator 1 compares the voltage of the composite video signal with the voltage (reference
voltage) generated in the reference voltage generating circuit, and converts the composite video signal into a digital value.
(3) Comparator 2
The comparator 2 compares the absolute standard voltage generated inside from the voltage and
power supply voltage of a composite video signal, and converts the composite video signal into a
digital value.
2.14.8 CC Start Bit • ID1 Reference Detecting Circuit
This circuit detects a CC start bit • ID1 reference bit at line decided in the data slice line specification
circuit.
In the case of CC start bit
1) Detect a clock run impulse at counting the input pulse of a data slice line.
2) When a clock run impulse is detected, the sampling clock outputted from a timing generating circuit
detects a start bit pattern, and judge CC start bit.
In the case of ID1 reference bit
1) Detect ID1 reference bit all over the window generated after fixed time from Hsep in a timing signal
generating circuit.
2.14.9 Clock Run-in Determination Circuit
Clock run in judging
By counting the number of pulses all over the specific window of a data slice line, it judges that it is clock
run in. When it judges with having no clock run in, the completion flag of a caption data latch is not set to
1. Moreover, the number of standard clocks counted in clock run impulse 1 cycle is stored in the bits 7-3
of a clock run in detection register (addresses 026916/030916).
ID1 reference bit judging
The number of standard clocks counted during fixed of ID1 reference bit is stored in the bits 5-0 of a
standard clock detection register (addresses 026C16/the 030C16). Read these bits after generating of
data slicer interruption ("(12) interruption demand generating circuit").
Clock run-in detection register is shown in Fig. 2.14.11, standard clock detection register is shown in Fig.
2.14.12.
Rev.1.00
May 18, 2004
page 170 of 296
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
Clock run-in detect register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
CRD0
CRD1
Bit symbol
Address
026916
030916
Bit name
Test bits
When reset
00000??? 2
00000??? 2
Function
R W
Read-only
CRD03/CRD13 Clock run-in detection bits
CRD04/CRD14
Number of reference clocks to
be counted in one clock run-in
pulse period.
CRD05/CRD15
CRD06/CRD16
CRD07/CRD17
Figure 2.14.11 Clock run-in detect register
Standard clock detection register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
BCD0
BCD1
Bit symbol
Address
026C16
030C16
When reset
??16
??16
Bit name
BCD00/BCD10 ID1 REF width detection bit
BCD01/BCD11
BCD02/BCD12
BCD03/BCD13
BCD04/BCD14
BCD05/BCD15
Function
R W
The number of standard clocks counted in a fixed
period of ID1 REF.
It is effective, only when "1" is set as the 026B16 and
030B16th bits 0 and ID1 slice function is operating.
Nothing is assigned.
If an attempt to write to these bits, write “0.” The read turns out to be “0.”
–
–
Figure 2.14.12 Standard clock detection register
2.14.10 Data Clock Generating Circuit
At the time of CC data slice
It synchronizes with CC start bit detected in CC start bit detection circuit, and a data clock is generated
after the fixed offset set up by the data clock position register (addresses 026A16/030A16). A data clock is
a clock for storing caption data in a caption register. When 16-bit data is stored in a caption register and
judged in a clock run in judging circuit that has clock run in, the completion flag of a caption data latch is
set.
A data clock position register is shown in Fig. 2.14.13.
At the time of ID1 data slice
The data clock which synchronized with ID1 reference bit is generated. With this data clock, the 6 bit data
of the remaining CRCC is stored in a caption register for 14-bit data among 20-bit data at a CRCC data
register (addresses 026D16/030D16). If 20-bit data is stored in each register, the completion flag of a
caption data latch will be set.
Rev.1.00
May 18, 2004
page 171 of 296
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
Data clock position register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
DPS0
DPS1
Address
026A16
030A16
Bit name
Bit symbol
DPS00/DPS10
DPS01/DPS11
DPS02/DPS12
DPS03/DPS13
Data clock position
set bits
When reset
X??00001 2
X??00001 2
Function
R
W
Only when CC21 or CCX slice is effective.
DPS04/DPS14
Reserved bit
Caption position bit 2
It is effective only at the time of 525p ID1 slice.
b6 b5
0 1
Nothing is assigned.
If an attempt to write to these bits, write “0.” The read turns out to be “0.”
Figure 2.14.13 Data clock position register
2.14.11 Caption Register and CRCC Data Register
The caption data converted into a digital value by the comparator is stored into the caption register and
CRCC data register in synchronization with the data clock. The contents of the stored caption data can be
obtained by reading out the caption data register and CRCC data register. These registers are reset to “0”
at a falling of Vsep. Read out these registers after the occurrence of a data slicer interrupt (refer to
“2.14.12 Interrupt request generating circuit)”.
Caption register 1L
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
C1L0
C1L1
Bit symbol
C1L00/C1L10
C1L01/C1L11
C1L02/C1L12
C1L03/C1L13
C1L04/C1L14
C1L05/C1L15
C1L06/C1L16
C1L07/C1L17
Figure 2.14.14 Caption register 1L
Rev.1.00
May 18, 2004
page 172 of 296
Address
0262 16
0302 16
Bit name
Caption data 1L
When reset
?? 16
?? 16
Function
R W
The following data is stored in 026616, and the 030616
street of bits 7 and 6.
In the case of CC caption
b7, b6
0
0
Data 16-9 of CC21 is stored in bit 7-0.
0
1
Data 16-9 of CCX is stored in bit 7-0.
1
0
Data 16-9 of CC21 is stored in bit 7-0.
1
1
Data 16-9 of CC21 is stored in bit 7-0.
In the case of ID1 caption
b7, b6
0
0
Data 16-9 of CC21 is stored in bit 7-0.
0
1
Data 14-7 of ID1 is stored in bit 7-0(*).
1
0
Data 16-9 of CC21 is stored in bit 7-0.
1
1
Do not set.
(*)525p:When ID1 data slice, set it as b7 and b6 = 01b.
The caption data stored also becomes the same.
✕
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
Caption register 1H
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
C1H0
C1H1
Bit symbol
C1H00/C1H10
Address
0263 16
0303 16
When reset
?? 16
?? 16
Bit name
Caption data 1H
Function
R W
The following data is stored in 026616, and the 030616
street of bits 7 and 6.
In the case of CC caption
b7, b6
0
0
Data 8-1 of CC21 is stored in bit 7-0.
0
1
Data 8-1 of CCX is stored in bit 7-0.
1
0
Data 8-1 of CC21 is stored in bit 7-0.
1
1
Data 8-1 of CC21 is stored in bit 7-0.
C1H01/C1H11
C1H02/C1H12
C1H03/C1H13
In the case of ID1 caption
b7, b6
0
0
Data 8-1 of CC21 is stored in bit 7-0.
0
1
Data 6-1 of ID1 is stored in bit 7-2 (note).
1
0
Data 8-1 of CC21 is stored in bit 7-0.
1
1
Do not set.
Note: The reading value of bits 1 and 0 is unfixed.
525p:When ID1 data slice, set it as b7 and b6 = 01b.
The caption data stored also becomes the same.
C1H04/C1H14
C1H05/C1H15
C1H06/C1H16
C1H07/C1H17
✕
Figure 2.14.15 Caption register 1H
Caption register 2L
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
C2L0
C2L1
Bit symbol
C2L00/C2L10
Address
0264 16
0304 16
When reset
?? 16
?? 16
Bit name
Caption data 2L
Function
In the case of CC caption
b7, b6
0
0
Data 16-9 of CCX is stored in bit 7-0.
0
1
Data is invalid.
1
0
Data is invalid.
1
1
Data 16-9 of CCX is stored in bit 7-0.
C2L01/C2L11
C2L02/C2L12
C2L03/C2L13
C2L04/C2L14
R W
The following data is stored in 026616, and the 030616
street of bits 7 and 6.
✕
In the case of ID1 caption
b7, b6
0
0
Data 14-7 of ID1 is stored in bit 7-0.
0
1
Data is invalid.
1
0
Data is invalid.
1
1
Do not set.
C2L05/C2L15
C2L06/C2L16
C2L07/C2L17
Figure 2.14.16 Caption register 2L
Caption register 2H
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
C2H0
C2H1
Bit symbol
C2H00/C2H10
C2H01/C2H11
C2H02/C2H12
C2H03/C2H13
C2H04/C2H14
C2H05/C2H15
C2H06/C2H16
C2H07/C2H17
Figure 2.14.17 Caption register 2H
Rev.1.00
May 18, 2004
page 173 of 296
Address
0265 16
0305 16
Bit name
Caption data 1H
When reset
?? 16
?? 16
Function
R W
The following data is stored in 026616, and the 030616
street of bits 7 and 6.
In the case of CC caption
b7, b6
0
0
Data 8-1 of CCX is stored in bit 7-0.
0
1
Data is invalid.
1
0
Data is invalid.
1
1
Data 8-1 of CCX is stored in bit 7-0.
In the case of ID1 caption
b7, b6
0
0
Data 6-1 of ID1 is stored in bit 7-2 (note).
0
1
Data is invalid.
1
0
Data is invalid.
1
1
Do not set.
Note : The reading value of bits 1 and 0 is unfixed.
✕
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
CRCC data register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
CRC0
CRC1
Bit symbol
Address
026D16
030D16
When reset
00?????? 2
00?????? 2
Bit name
CRC00/CRC10 CRCC data register
CRC01/CRC11
CRC02/CRC12
CRC03/CRC13
CRC04/CRC14
CRC05/CRC15
Function
R W
Data 20-15 of ID1 is stored in bit 5-0.
It is effective, only when "1" is set as the bit 0 of addresses
026B16 and 030B16, and ID1 slice function is operating.
✕
Nothing is assigned.
If an attempt to write to these bits, write “0.” The read turns out to be “0.”
Figure 2.14.18 CRCC data register
2.14.12 Interrupt Request Generating Circuit
The interrupt requests as shown in Table 2.14.2 are generated by combination of the following bits; bits 6
and 7 of the caption position register (addresses 026616/030616). Read out the contents of caption data
registers 1 and 2, CRCC data register, clock run-in detect register and standard clock detect register after
the occurrence of a data slicer interrupt request.
Table 2.14.2 Occurrence sources of Interrupt request
CPS
b7
Occurrence Sources of Interrupt Request at End of Data Slice Line
b6
0
1
0
After slicing line 21
1
After a line specified by bits 4 to 0 of CPS (Note)
0
After slicing line 21
1
After slicing line 21
CPS: Caption position register
Note: It becomes the one-line back specified in 525p caption position register bits 4 to 0 and the data clock
position register bits 6 and 5.
Data slicer reserved register 1
b7
0
b6
b5
b4
b3
0 0 0 0
b2
b1
0 0
b0
0
Symbol
DR01
DR11
Bit symbol
Address
When reset
026816
030816
0016
0016
Bit name
Reserved bits
Figure 2.14.19 Data slicer reserved register i (i = 1, 2)
Rev.1.00
May 18, 2004
page 174 of 296
Description
Must always be set to “0”
R
W
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
2.14.13 ID1 data slice
When data slice ID1, ID1 control register of Fig 2.14.20 needs to be set.
ID1 control register
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol
IDC0
IDC1
0 1 0 0
Address
026B16
030B16
Bit symbol
When reset
0016
0016
Bit name
Function
IDC00/IDC10
ID1 slice control bit
IDC01/IDC11
ID1 limitation slice select bit 0: Set this bit when slice simultaneously with CC21.
1: Set this bit when slice only ID1.
IDC02/IDC12
IDC03/IDC13
IDC04/IDC14
Internal absolute standard
voltage setting bit
R W
0: ID1 slice unused
1: ID1 slice operate
* Must always be set to "0" at ID1 slice unused.
When set to "1", be sure to set bits 4 to 0 = 10000b of
addresses 026616/030616.
525p:When ID1 data slice,
Set up bit 4-0 = 00001b at addresses 026616/030616.
Set bit 6 and 5 = 01b of addresses 026A16/030A16.
b4 b3 b2
1 0 0
Reserved bit
Must always be set to "0."
IDC0b/IDC1b
525i/p Selection bit
0:525i set up at CC21, CCX, and ID1 slice
0:525p set up at ID1 slice
Reserved bit
Must always be set to "0."
Figure 2.14.20 ID1 control register
ID1 reserved register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
IRSV0
IRSV1
1 1
Bit symbol
Address
When reset
0016
0016
031C16
031D16
Bit name
Function
The register only for read-out
The contents are unfixed when it reads.
IRSV06/IRSV16 Sync slice setting bit
Must always be set to "1."
IRSV07/IRSV17
Figure 2.14.21 ID1 reserved register
Line 40 at 525p
Line 20 at 525i
Hsep
ID1 reference bit
Composite
video signal
I
D
1
I
D
2
I
D
3
* ID1 to ID20 shows ID1 data
ID1 reference
detection timing signal
Figure 2.14.22 ID1 signal in vertial blanking interval
Rev.1.00
May 18, 2004
page 175 of 296
I
D
19
I
D
20
R W
–
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
2.15 HSYNC Counter
The synchronous signal counter counts HSYNC from HSYNC count input pins (HC0/P75, HC1/P77) as a
count source.
The count value in a certain time (T time; 1024 µs, 2048 µs, 4096 µs and 8192 µs) divided system clock is
stored into the 8-bit latch.
Accordingly, the latch value changes in the cycle of T time. When the count value exceeds “FF16,” “FF16”
is stored into the latch.
The latch value can be obtained by reading out the HSYNC counter latch (address 027F16). A count source
and count update cycle (T time) are selected by bits 0, 3 and 4 of the HSYNC counter register.
Figure 2.15.1 shows the HSYNC counter and Figure 2.15.2 shows the synchronous signal counter block
diagram.
Notes 1: When using the HSYNC counter, set bit 7 of the peripheral mode register (address 027D16)
according to the main clock frequency.
2: HSYNC counter latch is a register only for read-out.
HSYNC counter register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
HC
Address
026716
When reset
XXX00X0016
Bit symbol
Bit name
HCC0
Count source switch bit
0 : HC0/P75 pin input
1 : HC1/P77 pin input
HCC1
Input polarity
switch bit
0:
R
Function
1:
W
(Falling edge count)
(Rising edge count)
Nothing is assigned. In an attempt to write to this bit, write “0.”
The value, if read, turns out to be “0.”
HCC3
Count freguency
selection bits
HCC4
b4 b3 <Count freguency>
0 0 : 1024 µs
0 1 : 2048 µs
1 0 : 4096 µs
1 1 : 8192 µs
Nothing is assigned. In an attempt to write to these bits, write “0.”
The value, if read, turns out to be “0.”
Note: When HC0 and HC1 input are positive polarity (negetive polarity),
HIGH width (LOW width) needs 3 main clock cycles or more of system clock.
Figure 2.15.1 HSYNC counter register
1024 µs
System clock f32
2048 µs
Freguency divider
4096 µs
HCC3, HCC4
8192 µs
HC0/P75
HCC1
HC1/P77
Polarity switch
Reset
8-bit counter
Counter
Latch (8 bits)
HSYNC
counter latch
HCC0
Selection gate : connected to black
side when reset.
Figure 2.15.2 HSYNC counter block diagram
Rev.1.00
May 18, 2004
page 176 of 296
Data bus
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
2.16 OSD Functions
Table 2.16.1 outlines the OSD functions of this microcomputer. This OSD function can display the following: the block display (32 characters ✕ 16 lines or 42 characters ✕ 16 lines) and the SPRITE display, and
can display the both display at the same time. There are 3 display modes and they are selected by a block
unit. The display modes are selected by block control register i (i = 1 to 16). The features of each display are
described below.
Note: When using OSD function, select “No-division mode” as BCLK operating mode and set the main
clock frequency to f(XIN) = 16 MHz or 10 MHz. At this time, set bit 7 (SSCK) of the peripheral mode
register according to the XIN frequency to be used.
Table 2.16.1 Features of each display style
Block display
Display style
CC mode
(Closed caption mode)
Parameter
OSD mode
(On-screen display mode)
OSDS mode
Number of display characters
16 ✕ 20 dots
16 ✕ 20 dots
12 ✕ 20 dots
8 ✕ 20 dots
4 ✕ 20 dots
(Character display area:
16 ✕ 26 dots)
OSDL
enable mode
OSDL
disable mode
Kinds of character sizes
(See note 1) Pre-divide
ratio (Note)
Dot size
OSDL mode
32 characters ✕ 16 lines/42 characters ✕ 16 lines
Dot structure
Kinds of
character
ROM
OSDP mode
254 kinds
254 kinds
14 kinds
4 kinds
1 character ✕ 2 lines
24 ✕ 32 dots
16 ✕ 26 dots
32 ✕ 20 dots
254 kinds
126 kinds
2 kinds of RAM font
14 kinds
8 kinds
12 kinds
✕ 1, ✕ 2, ✕ 3
✕ 1, ✕ 2
1TC ✕ 1/2H,
1TC ✕ 1H,
1.5TC ✕ 1/2H,
1.5TC ✕ 1H,
2TC ✕ 2H,
3TC ✕ 3H
Attribute
Smooth italic,
under line, flash
Border
Character font
coloring
1 screen: 8 kinds
(a character unit)
1 screen: 16 kinds
(a character unit)
1TC ✕ 1/2H,
1TC ✕ 1H,
2TC ✕ 2H,
3TC ✕ 3H
Max. 512 kinds
Max. 512 kinds
Possible
Possible
(a character unit, 1 screen: 4 (a character unit,1 screen: 16 kinds,
kinds, Max. 512 kinds)
Max. 512 kinds)
Display layer
Layer 1
OSD output (See note 2)
1TC ✕ 1/2H,
1TC ✕ 1H,
1.5TC ✕ 1/2H,
1.5TC ✕ 1H,
2TC ✕ 2H,
3TC ✕ 3H
Layers 1, 2
Layer 1
Layers 1, 2
Analog R, G, B output (each 8 adjustment levels: 512 colors), Digital OUT1, OUT2 output
Raster coloring
Possible (a screen unit, max 512 kinds)
Auto solid space function
Triple layer OSD function, window function, blank function
Display expansion
(multiline display)
Possible
Notes 1: The character size is specified with dot size and pre-divide ratio (refer to “2.16.3 Dot Size”).
2: As for SPRITE display, OUT2 is not output.
3: As for SPRITE display, the window function does not operate.
4: The divide ratio of the frequency divider (the pre-divide circuit) is referred as “pre-divide ratio” hereafter.
May 18, 2004
page 177 of 296
✕ 1, ✕ 2
1TC ✕ 1/2H,
1TC ✕ 1H,
2TC ✕ 2H,
3TC ✕ 3H
1 screen: 16 kinds (a dot unit)
1 screen: 16 kinds
(only specified dots are colored (a dot unit)
by a character unit)
Max. 512 kinds
Max. 512 kinds
Character
background
coloring
Rev.1.00
SPRITE display
508 kinds
1TC ✕ 1/2H,
1TC ✕ 1H
Other function
(See note 3)
CDOSD mode
(Color dot on-screen
display mode)
Layer 3 (with highest priority)
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
The OSD circuit has an extended display mode. This mode allows multiple lines (16 lines or more) to be
displayed on the screen by interrupting the display each time one line is displayed and rewriting data in the
block for which display is terminated by software.
Figure 2.16.1 shows the display-enable fonts for each display style. Figure 2.16.2 shows the block diagram
of the OSD circuit. Figure 2.16.3 shows the OSD control register 1. Figure 2.16.4 shows the block control
register i.
Rev.1.00
May 18, 2004
page 178 of 296
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
Display Styles
Display-enable Fonts
16 dots
← Blank area
26 dots
CC Mode
← Underline area
← Blank area
16 dots
20 dots
OSDS Mode
20 dots
20 dots
8 dots
*
**
4 dots
**
20 dots
12 dots
20 dots
16 dots
OSDP Mode
* : Only character
codes
**: Blank font
24 dots
32 dots
OSDL Mode
26 dots
CDOSD Mode
32 dots
20 dots
SPRITE
Figure 2.16.1 Display-enable fonts for each display style
Rev.1.00
May 18, 2004
page 179 of 296
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
Clock for OSD
OSC1 OSC2
HSYNC VSYNC
Control register for OSD
Internally generated clock
Display
oscillation
circuit
OSD control circuit
OSD RAM (SPRITE)
32 dots ✕ 20 dots ✕ 4 planes ✕ 2 lines
SPRITE OSD control register
OSD control register 1
OSD control register 2
Horizontal position register
Clock control register i
I/O polarity control register
OSD control register 3
Raster color register
Top border control register
Bottom border control register
Block control register i
Vertical position register i
Color palette register i
OSD reserved register i
(address 020116)
(address 020216)
(address 020316)
(address 020416)
(addresses 020516, 020B16)
(address 020616)
(address 020716)
(addresses 020916, 020816)
(addresses 020D16, 020C16)
(addresses 020F16, 020E16)
(addresses 021016 to 021F16)
(addresses 022016 to 023F16)
(addresses 024016 to 025B16)
(addresses 020A16, 025D16,
027A16, 027B16, 027C16)
(address 025F16)
(addresses 027116, 027016)
(addresses 027316, 027216)
(addresses 027416 to 027716)
(addresses 027916, 027816)
(address 028016)
(address 028116)
(address 028216)
OSD control register 4
Left border control register
Right border control register
SPRITE vertical position register
SPRITE horizontal position register
Internal oscillation control register 1
Internal oscillation control register 2
Internal oscillation control register 3
Shift register
OSD RAM (See note 1)
19 bits ✕ 32 characters ✕ 16 lines
OSD ROM (character font) (See note 2)
16 dots ✕ 20 dots ✕ 254 characters
24 dots ✕ 32 dots ✕ 254 characters
Shift register
Output circuit
Shift register
R
G
B
OUT1
OUT2
OSD ROM (color dot font)
16 dots ✕ 26 dots ✕ 4 planes ✕
94 characters
Shift register
Data bus
Figure 2.16.2 Block diagram of OSD circuit
Rev.1.00
May 18, 2004
page 180 of 296
Notes 1: In 42 character-mode, 19 bits ✕ 42 characters ✕ 16 lines
2: In OSDL disable mode, 16 dots ✕ 20 dots ✕ 762 characters.
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
OSD control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
OC1
OC16 .
OC10
OC11
OC12
OC13
Address
020216
Bit name
OSD control bit
(See note 1)
Scan mode
selection bit
Border type
selection bit
Flash mode
selection bit
When reset
0016
Function
0 : All-blocks and SPRITE display OFF
1 : All-blocks and SPRITE display ON
0 : Normal scan mode
1 : Bi-scan mode
0 : All bordered
1 : Shadow bordered (See note 2)
0 : Color signal of character background
part does not flash
1 : Color signal of character background
part flashes
OC14
Automatic solid
space control bit
0 : OFF
1 : ON
OC15
Vertical window/blank
control bit
0 : OFF
1 : ON
OC16
OC17
Layer mixing
control bits
(See note 3)
b7 b6
0 0: Logic sum (OR) of layer 1’s
color and layer 2’s color
0 1: Layer 1’s color has priority
1 0: Layer 2’s color has priority
1 1: Do not set.
Notes 1 : When this bit is switched "1" from "0", the display screen remains
unchanged until a rising (falling) of the next VSYNC.
2 : Shadow border is output at right and bottom side of the font.
3 : OUT2 is always ORed, regardless of values of these bits.
Figure 2.16.3 OSD control register 1
Rev.1.00
May 18, 2004
page 181 of 296
R W
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
i
b7
4 b3 b2 b1 b0
Symbol
BCi (i = 1 to 16)
Bit symbol
BCi_0
Address
021016 to 021F16
Bit name
Display mode
selection bits
BCi_1
BCi_2
BCi_3
Dot size
selection bits
F unction
b2 b1
0
0
0
0
1
1
1
1
b6
0
0
1
1
0
0
1
1
Pre-divide ratio
selection bits
BCi_6
b0
0
1
0
1
0
1
0
1
b5 b4
Functions
Display OFF
OSDS mode (No bordered)
CC mode
CDOSD mode
OSDP mode (No bordered)
OSDS mode (Bordered)
OSDP mode (Bordered)
OSDL mode
b3 Pre-divide
Dot size
ratio
0
0
0
1
1
1
1
1
BCi_4
BCi_5
When reset
Indeterminate
0
0
1
1
0
0
1
1
0
0
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
✕ 1
✕ 2
✕3
1Tc ✕ 1/2H
1Tc ✕ 1H
2Tc ✕ 2H
3Tc ✕ 3H
1Tc ✕ 1/2H
1Tc ✕ 1H
2Tc ✕ 2H
3Tc ✕ 3H
1.5Tc ✕ 1/2H (See notes 3, 4)
1.5Tc ✕ 1H (See notes 3, 4)
1Tc ✕ 1/2H
1Tc ✕ 1H
2Tc ✕ 2H
3Tc ✕ 3H
Nothing is assigned. In an attempt to write to this bit, write “0.”
The value, if read, turns out to be indeterminate.
Notes 1: Tc is OSD clock cycle divided in pre-divide circuit
2: H is HSYNC
3: This character size is available only in Layer 2. At this time, set layer 1’s
pre-divide ratio = ✕ 2, layer 1’s horizontal dot size = 1Tc.
4: In OSDL and OSDP modes, 1.5Tc size cannot be used.
Figure 2.16.4 Block control register i (i = 0 to 16)
Rev.1.00
May 18, 2004
page 182 of 296
R
W
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
2.16.1 Triple Layer OSD
Three built-in layers of display screens accommodate triple display of channels, volume, etc., closed
caption, and sprite displays within layers 1 to 3.
The layer to be displayed in each block is selected by bit 0 or 1 of the OSD control register 2 for each
display mode (refer to Figure 2.16.7). Layer 3 always displays the sprite display.
When the layer 1 block and the layer 2 block overlay, the screen is composed with layer mixing by bit
6 or 7 of the OSD control register 1, as shown in Figure 2.16.5. Layer 3 always takes display priority of
layers 1 and 2.
Notes 1: When mixing layer 1 and layer 2, note Table 2.16.2.
2: OSDP mode is always displayed on layer 1. And also, it cannot be overlapped with layer 2’s block.
3: OUT2 is always ORed, regardless of values of bits 6, 7 of the OSD control register 1. And
besides, even when OUT2 (layer 1 and layer 2) overlaps with SPRITE display (layer 3),
OUT2 is output without masking.
Table 2.16.2 Mixing layer 1 and layer 2
Block
Block in Layer 1
Parameter
Display mode
Block in Layer 2
CC, OSDS/L, CDOSD mode
OSDS/L, CDOSD mode
✕ 1, ✕ 2 (CC mode)
Same as layer 1 (See note)
Pre-divide ratio
✕ 1 to ✕ 3 (OSD, CDOSD mode)
Dot size
1TC ✕ 1/2H, 1TC ✕ 1H
Pre-divide ratio = ✕ 1
Pre-divide ratio = ✕ 2
(CC mode)
1TC ✕ 1/2H
1TC ✕ 1/2H, 1.5TC ✕ 1/2H
1TC ✕ 1H
1TC ✕ 1H, 1.5TC ✕ 1H (See note)
1TC ✕ 1H, 1TC ✕ 1/2H, 2TC ✕ 2H, • Same size as layer 1
3TC ✕ 3H
(OSDS/L, CDOSD mode)
•1.5TC can be selected only when: layer 1’s pre-divide ratio =
✕ 2 AND layer 1’s horizontal dot size = 1TC.
As this time, vertical dot size is the same as layer 1.
Arbitrary
Horizontal display start position
Same position as layer 1
Arbitrary
Vertical display start position
However, when dot size is 2Tc ✕ 2H or 2Tc ✕ 3H, set difference between vertical display position
of layer 1 and that of layer 2 as follows.
•2Tc ✕ 2H: 2H units
•3Tc ✕ 3H: 3H units
Note: In the OSDL mode, 1.5TC size cannot be used.
Note : When layer 1/layer 2 and SPRITE display
overlay each other, only OUT2 in layer 1/layer 2
is output.
SPRITE
Layer 1/layer 2
(except transparent)
Block 9
Block 10
...
Sprite
A
Layer 3
Block 15
Block 16
...
Layer 2
Block 1
Block 2
Block 7
Block 8
SPRITE
R, G, B of layer 1/layer 2
OUT2 of layer 1/layer 2
Layer 1
Fig 2.16.5 Triple layer OSD
Rev.1.00
May 18, 2004
page 183 of 296
A'
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
Display example of layer 1 = “HELLO,” layer 2 = “CH5”
CH5
HELLO
CH5
HELLO
CH5
HELLO
Layer 1’s color has priority
OC17 = “0”, OC16 = “1”
Logical sum (OR) of
layer 1’s color and
layer 2’s color (See note)
OC17 = “0,” OC16 = “0”
Layer 2’s color has priority
OC17 = “1,” OC16 = “0”
Note: The logical sum (OR) of layer mixing is not OR of the color palette registers’ contents (color), but
that of color pallet registers’ numbers (i).
Example) When the logical sum (OR) is performed on the color palettes 1 and 4;
the number 1 (00012) and number 4 (01002) are ORed and it results in the number 5
(01012). That is, the contents (color) of color palette register 5 is output. The color of
color palette register 5 is output in the ORed part, regardless of colors of color palettes
registers 1 and 4.
Figure 2.16.6 Display example of triple layer OSD
OSD control register 2
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
OC2
Bit symbol
OC20
Address
020316
Display layer
selection bits
b1
0
0
1
1
b0
0
1
0
1
Layer 1
Layer 2
CC, OSDS/L/P, CDOSD
CC, OSDS/L/P
CDOSD
CC, OSDP, CDOSD
OSDS/L
CC, OSDP
CDOSD
OSDS/L
OC22
R, G, B signal output 0: Digital output
selection bit
1: Analog output (8 gradations)
OC23
Solid space output bit 0: OUT1 output
1: OUT2 output
OC24
Horizontal
window/blank control
bit
Window/blank
selection bit 1
(horizontal)
OC25
0: OFF
1: ON
0: Horizontal blank function
1: Horizontal window function
OC26
Window/blank
selection bit 2
(vertical)
0: Vertical blank function
1: Vertical window function
OC27
OSD interrupt
request selection bit
0: At completion of layer 1 block display
1: At completion of layer 2 block display
Figure 2.16.7 OSD control register 2
May 18, 2004
Function
Bit name
OC21
Rev.1.00
When reset
0016
page 184 of 296
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M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
2.16.2 Display Position
The display positions of characters are specified by a block. There are 16 blocks, blocks 1 to 16. Up to 32
characters (32-character mode)/42 characters (42-character mode)/ can be displayed in each block (refer to 2.16.6 Memory for OSD).
The display position of each block can be set in both horizontal and vertical directions by software.
The display position in the horizontal direction can be selected for all blocks in common from 256-step
display positions in units of 4 TOSC (TOSC = OSD oscillation cycle).
The display position in the vertical direction for each block can be selected from 1024-step display positions in units of 1 TH ( TH = HSYNC cycle).
Blocks are displayed in conformance with the following rules:
• When the display position is overlapped with another block in the same layer (Figure 2.16.8 (b)), a low
block number (1 to 16) is displayed on the front.
• When another block display position appears while one block is displayed in the same layer (Figure
2.16.8 (c)), the block with a larger set value as the vertical display start position is displayed. However,
do not display block with the dot size of 2TC ✕ 2H or 3TC ✕ 3H during display period (✽) of another block.
✽ In the case of OSDS/P mode block: 20 dots in vertical from the vertical display start position.
✽ In the case of OSDL mode block: 32 dots in vertical from the vertical display start position.
✽ In the case of CC or CDOSD mode block: 26 dots in vertical from the vertical display start position.
HP
VP1
Block 1
VP2
Block 2
VP3
Block 3
(a) Example when each block is separated
HP
VP1 = VP2
Block 1
(Block 2 is not displayed)
(b) Example when block 2 overlaps with block 1
HP
VP1
VP2
Block 1
Block 2
(c) Example when block 2 overlaps in process of block 1
Note: VPi (i = 1 to 16) indicates the vertical display start position of display block i.
Figure 2.16.8 Display position
Rev.1.00
May 18, 2004
page 185 of 296
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
The display position in the vertical direction is determined by counting the horizontal sync signal (HSYNC).
At this time, when VSYNC and HSYNC are positive polarity (negative polarity), it starts to count the rising
edge (falling edge) of HSYNC signal from after fixed cycle of rising edge (falling edge) of VSYNC signal. So
interval from rising edge (falling edge) of VSYNC signal to rising edge (falling edge) of HSYNC signal needs
enough time (2 ✕ BCLK cycles or more) for avoiding jitter. The polarity of HSYNC and VSYNC signals can
select with the I/O polarity control register (address 020616).
8 ✕ BCLK cycles or more
VSYNC signal input
VSYNC control
signal in
microcomputer
Period of counting
HSYNC signal
100 to 200 [ns]
(BCLK = 10 MHz)
62.5 to 125 [ns]
(BCLK = 16 MHz)
(Note 2)
HSYNC
signal input
26 ✕ BCLK cycles
or more
1
2
3
4
5
Not count
When bits 0 and 1 of the I/O polarity control register
(address 020616) are set to “1” (negative polarity)
Notes 1 : The vertical position is determined by counting falling edge of
HSYNC signal after rising edge of VSYNC control signal in the
microcomputer.
2 : Do not generate falling edge of HSYNC signal near rising edge
of V SYNC control signal in microcomputer to avoid jitter.
3 : The pulse width of HSYNC needs 26 ✕ BCLK cycles or more.
Figure 2.16.9 Supplement explanation for display position
Rev.1.00
May 18, 2004
page 186 of 296
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
The vertical position for each block can be set in 1024 steps (where each step is 1TH (TH: HSYNC cycle))
as values “00216” to “3FF16” in vertical position register i (i = 1 to 16) (addresses 022016 to 023F16). The
vertical position register i is shown in Figure 2.16.10.
Vertical position register i
(b15)
(b8)
b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0
Symbol
VPi (i = 1 to 16)
Bit symbol
Address
When reset
Even addresses within addresses 022016 to 023F16, Indeterminate
Odd addresses within addresses 022016 to 023F16
Bit name
VPi_9 to VPi_0 Vertical display start
position control bits of
SPRITE font
Function
R W
Vertical display start position = TH ✕ n
(n: setting value, TH: HSYNC cycle)
Nothing is assined.
In an attempt to write to this bit, write “0.”
The value, if read, turns out to be indeterminate.
Note : Do not set VPi ≤ “00116,” VPi ≥ “40016.”
Figure 2.16.10 Vertical position register i (i = 1 to 16)
The horizontal position is common to all blocks, and can be set in 256 steps (where 1 step is 4TOSC, TOSC
being OSD oscillation cycle) as values “0016” to “FF16” in bits 0 to 7 of the horizontal position register
(address 020416). The horizontal position register is shown in Figure 2.16.11.
Horizontal position register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
HP
Bit symbol
Address
020416
Bit name
HP_7 to HP_0 Horizontal display start
position control bits
Function
Horizontal display start position = 4TOSC ✕ n
(n: setting value, TOSC: OSD oscillation cycle)
Note : The setting value synchronizes with the VSYNC.
Figure 2.16.11 Horizontal position register
Rev.1.00
May 18, 2004
page 187 of 296
When reset
0016
R W
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
Note : 1TC (TC : OSD clock cycle divided in pre-divide circuit) gap occurs between the horizontal display
start position set by the horizontal position register and the most left dot of the 1st block. Accordingly, when 2 blocks have different pre-divide ratios, their horizontal display start position will not
match.
Ordinary, this gap is 1TC regardless of character sizes, however, the gap is 1.5TC only when the
character size is 1.5TC.
HSYNC
1TC
Note 1
Tdef
4TOSC ✕ N
Block 1 (Pre-divide ratio = 1)
1TC
Block 2 (Pre-divide ratio = 2)
1TC
1.5TC
Block 3 (Pre-divide ratio = 3)
Block 4 (Pre-divide ratio = 2, character size = 1.5Tc)
N = Value of horizontal position register (decimal notation)
Tc = OSD clock cycle divided in pre-divide circuit
Tosc = OSD oscillation cycle
Tdef = 50Tosc (When analog RGB output selected: 51Tosc)
Figure 2.16.12 Notes on horizontal display start position
Rev.1.00
May 18, 2004
page 188 of 296
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
2.16.3 Dot Size
The dot size can be selected by a block unit. The dot size in vertical direction is determined by dividing
HSYNC in the vertical dot size control circuit. The dot size in horizontal is determined by dividing the
following clock in the horizontal dot size control circuit : the clock gained by dividing the OSD clock source
(internally generated clock, OSC1, main clock) in the pre-divide circuit. The clock cycle divided in the predivide circuit is defined as 1TC.
The dot size is specified by bits 3 to 6 of the block control register.
Refer to Figure 2.16.4 (the block control register i), refer to Figure 2.16.15 (the clock control register).
The block diagram of dot size control circuit is shown in Figure 2.16.13.
Notes 1 : The pre-divide ratio = 3 cannot be used in the CC mode.
2 : The pre-divide ratio of the layer 2 must be same as that of the layer 1 by the block control
register i.
3 : In the bi-scan mode, the dot size in the vertical direction is 2 times as compared with the normal
mode. Refer to “2.16.18 Scan Mode” about the scan mode.
Clock cycle
= 1TC
OSC1
Synchronous
circuit
Internally generated
clock
Cycle✕2
Horizontal dot size
control circuit
Cycle✕3
Pre-divide circuit
Vertical dot size
control circuit
HSYNC
OSD control circuit
Figure 2.16.13 Block diagram of dot size control circuit
1 dot
1TC
1/2H
1TC
2TC
3TC
Scanning line of F1 (F2)
Scanning line of F2 (F1)
1H
2H
3H
In normal scan mode
Figure 2.16.14 Definition of dot sizes
Rev.1.00
May 18, 2004
page 189 of 296
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
2.16.4 Clock for OSD
As a clock for display to be used for OSD, it is possible to select one of the following 3 types.
• Internally generated clock (20 MHz to 40 MHz) output by the internal oscillator
• Clock from the LC oscillator supplied from the pins OSC1 and OSC2
• Clock from the ceramic resonator (or the quartz-crystal oscillator) from the pins OSC1 and OSC2
When the clock control register i (i=1-2) is set to choose an internally generated clock for the OSD clock,
use the internal oscillation control register i (i=1-3) to select the oscillation frequency.
Clock control register 1
b7 b6 b5 b4 b3 b2 b1 b0
0 0 1
0
Symbol
CS
Bit symbol
Address
020516
When reset
0016
Function
Bit name
CS0
Clock selection bit
0: Internally generated clock
1: OSC1 clock
CS1
OSC1 oscillating mode
selection bits
b2 b1
R, G, B analog signal
output control bit
0: Outputs 8 gray levels from the R, G
and B pins.
1: Converts the 8 gray levels output for
R, G and B each into 3-bit digital quantities
which are output from the respective ports.
CS2
0: Stopped
1: Do not set.
0: LC oscillating mode
1: Ceramic • quartz-crystal
oscillating mode
Must always be set to “0”
Reserved bit
CS4
0
0
1
1
R W
Reserved bit
Must always be set to “1”
Reserved bits
Must always be set to “0”
Note: Please refer to 2.5.2 OSD oscillation circuit about the pin connection at the time of the clock
use for OSD.
Figure 2.16.15 Clock control register 1
Clock control register 2
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0 0 0
0
Symbol
CG
Bit symbol
Address
020B16
Bit name
Clock adjustment bit
Reserved bits
CS27
Function
R W
Must always be set to “0”.
Reserved bit
CS21
When reset
0016
Set the value which is same as CS27.
Must always be set to “0”.
Clock devided bit
(Note)
0: Devided in 2
1: No-division
Note: At the time of internal oscillation use for clock display,
set this bit to “0” and set this bit the “1” at the time of ceramic resonator use.
This bit does not function at the time of LC oscillator use.
Figure 2.16.16 Clock control register 2
Rev.1.00
May 18, 2004
page 190 of 296
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
Internally generated clock
Internal oscillator
“0”
OSD control circuit
“10”
LC
Ceramic •
quartz-crystal
OSC1 clock
CS0
“1”
“11”
CS2, CS1
Oscillating mode for OSD
Figure 2.16.17 Block Diagram of OSD selection circuit
Rev.1.00
May 18, 2004
page 191 of 296
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
Internal oscillation control register 1 (Note)
b7 b6 b5 b4 b3 b2 b1 b0
0
0
Symbol
DIV0
Address
0280
BIt name
BIt symbol
DIV00
When reset
0016
Reference clock divide bit
DIV01
Function
R W
When f(XIN)=16MHz, set "001112"
When f(XIN)=10MHz, set "001002"
DIV02
DIV03
DIV04
DIV05
Internal oscillation adjustment
bit
Reserved bit
Please set up the same value as VCO00.
Must always be set to "0"
Internal oscillation control register 2 (Note)
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol
DIV1
Address
0281
BIt name
BIt symbol
DIV10
DIV11
When reset
0016
Internal oscillation frequency
select bit
Function
R W
Internal oscillation frequency
=(N+1)/2MHz
DIV12
N : Values that can be set by DIV16 to DIV10
DIV13
Set N as shown below:
DIV14
N="3B16"–"4F16" when VCO01="0"
DIV15
N="2716"–"3B16" when VCO01="1"
DIV16
Ex. Set 2716 at 20MHz
Set 4F16 at 40MHz
Reserved bit
Must always be set to "0"
Internal oscillation control register 3 (Note)
b7 b6 b5 b4 b3 b2 b1 b0
0
0
0
0
Symbol
VCO
Address
0282
BIt symbol
BIt name
VCO00
Internal oscillator operating bit
VCO01
Internal oscillator control bit
VCO02
Oscillation characteristic switch
bits
When reset
0016
Function
0 : OFF
1 : ON
0 : Selects oscillator for 30 to 40 MHz
1 : Selects oscillator for 20 to 30 MHz
VCO03
Reserved bit
Must be fixed to (b3, b2)=(0, 0)
Must always be set to "0"
Note : Since there is a possibility that jitter may occer, do not access these registers during display.
Figure 2.16.18 Internal oscillation control register i (i=1 to 3)
Rev.1.00
May 18, 2004
page 192 of 296
R W
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
2.16.5 Field Determination Display
To display the block with vertical dot size of 1/2H, whether an even field or an odd field is determined
through differences in a synchronizing signal waveform of interlacing system. The dot line 0 or 1 (refer to
Figure 2.16.20) corresponding to the field is displayed alternately.
In the following, the field determination standard for the case where both the horizontal sync signal and
the vertical sync signal are negative-polarity inputs will be explained. A field determination is determined
by detecting the time from a falling edge of the horizontal sync signal until a falling edge of the VSYNC
control signal (refer to Figure 2.16.9) in the microcomputer and then comparing this time with the time of
the previous field. When the time is longer than the comparing time, it is regarded as even field. When the
time is shorter, it is regarded as odd field.
The field determination flag changes at a rising edge of VSYNC control signal in the microcomputer .
The contents of this field can be read out by the field determination flag (bit 7 of the I/O polarity control
register at address 020616). A dot line is specified by bit 6 of the I/O polarity control register (refer to
Figure 2.16.19).
However, the field determination flag read out from the CPU is fixed to “0” at even field or “1” at odd field,
regardless of bit 6.
I/O polarity control register
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol
PC
Address
020616
Bit symbol
When reset
80 16
Bit name
Function
PC0
HSYNC input
polarity switch bit
0 : Positive polarity input
1 : Negative polarity input
PC1
VSYNC input
polarity switch bit
0 : Positive polarity input
1 : Negative polarity input
PC2
R, G, B output
polarity switch bit
0 : Positive polarity output
1 : Negative polarity output
Reserved bit
Must always be set to “0.”
PC4
OUT1 output
polarity switch bit
0 : Positive polarity output
1 : Negative polarity output
PC5
OUT2 output
polarity switch bit
0 : Positive polarity output
1 : Negative polarity output
PC6
Display dot line
selection bit
(See note)
0:“
“
1:“
“
PC7
May 18, 2004
page 193 of 296
” at odd field
” at even field
” at odd field
Field determination 0 : Even field
flag
1 : Odd field
Figure 2.16.19 I/O polarity control register
Rev.1.00
” at even field
R W
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
Both HSYNC signal and VSYNC signal are negative-polarity input
HSYNC
Field
VSYNC and
VSYNC
control
signal
in microcomputer
Upper :
VSYNC signal
(n - 1) field
(Odd-numbered)
Field
Display dot line
determination
selection bit
flag(Note)
Odd
T1
0.5 to 0.1 [ms] at
f(BCLK) = 10 MHz
(n) field
(Even-numbered)
Even
(n + 1) field
(Odd-numbered)
Odd
0
Dot line 1
1
Dot line 0
0
Dot line 0
1
Dot line 1
0 (T2 > T1)
T2
Lower :
VSYNC control
signal in
microcomputer
Display dot line
1 (T3 < T2)
T3
When using the field determination flag, set bit 7 of the peripheral mode register (address 027D16) according to the main clock frequency.
1
2 3 4 5
6 7 8 9 10 11 12 13 14 15 16
1 2
3 4 5
6 7 8 9 10 11 12 13 14 15 16
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
OSDS mode
24
25
26
CC mode · CDOSD mode
When the display dot line selection bit is “0,”
the “
” font is displayed at even field, the
“
” font is displayed at odd field. Bit 7 of the
I/O polarity control register can be read as the
field determination flag : “1” is read at odd field,
“0” is read at even field.
OSD ROM font configuration diagram
Note : The field determination flag changes at a rising edge of the VSYNC control signal (negative-polarity input) in
the microcomputer.
Figure 2.16.20 Relation between field determination flag and display font
Rev.1.00
May 18, 2004
page 194 of 296
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
2.16.6 Memory for OSD
There are 2 types of memory for OSD : OSD ROM (addresses 4000016 to 5FFFF16) used to store character dot data and OSD RAM (addresses 040016 to 13FF16) used to specify the kinds of display characters, display colors, and SPRITE display. The following describes each type of memory.
(1) ROM for OSD (addresses 4000016 to 5FFFF16)
The dot pattern data for OSD characters is stored in the character font area in the OSD ROM and the
CD font data for OSD characters is stored in the color dot font area in the OSD ROM. To specify the
kinds of the character font and the CD font, it is necessary to write the character code into the OSD
RAM.
For character font, there are the following 2 mode.
• OSDL enable mode
16 ✕ 20-dot font and 24 ✕ 32-dot font
• OSDL disable mode
16 ✕ 20-dot font
The modes are selected by bit 0 of the OSD control register 4 for each screen.
The conditions for each OSDL enable/disable mode are shown in Figure 2.16.22.
During OSDL enable mode, character codes 00016 through 1FF16 can be used. In this case, the
character codes 00016 through 0FF16 are turned to 16 ✕ 20-dot fonts, whereas the character codes
10016 through 1FF16 are turned to 24 ✕ 32- dot fonts. Of these, however, character codes 0FE16,
0FF16, 10016, and 18016 cannot be used.
During OSDL disable mode, character codes 00016 through 2FF16 can be used. In this case, all
characters are turned to 16 ✕ 20-dots. Of these, however, character codes 0FE16, 0FF16, 10016,
18016, 20016, and 0FE16 cannot be used.
CD codes 0016 through 7F16 can be used. In this case, all characters are turned to 16 ✕ 26-dot fonts.
Of these, however, CD codes 3F16 and 4016 cannot be used.
OSD control register 4
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
OC4
Bit symbol
OC40
OC41
Address
025F16
Bit name
When reset
XXXXX002
Function
OSDL mode
selection bit
0 : OSDL enable mode
1 : OSDL disable mode
Number of horizontal
display characters
selection bit
0 : 32 characters for each block
(32-character mode)
1 : 42 characters for each block
(42-character mode)
Nothing is assigned.
In an attempt to write to these bits, write “0.” The value, if read, turns out to be “0.”
Figure 2.16.21 OSD control register 4
Rev.1.00
May 18, 2004
page 195 of 296
RW
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
Depending on the relationship of OSDL enable/disable mode, display mode and character code, note the conditions below.
OSDL enable/
disable mode
Specified
character
code
CC
OSDS/P
OSDL
OSDL disable mode
Character size
Display mode
Character size
Display mode
& character code
OSDL enable mode
(Bit 0 of OSD control register 4 = “0”)
(Bit 0 of OSD control register 4 = “1”)
CC
S
Used
Used
Not used
(See note 3)
Used
Used
Display OFF
10016
to
1FF16
L
Used
(See note 1)
Used
(See note 1)
Used
Used
Used
Display OFF
Used
Display OFF
S
20016
to
27F16
Not used
(See note 3)
Not used
(See note 3)
30016
to
3FF16
Used
(No border ) Display OFF
(See note 2)
Not used
16
24
20
Figure 2.16.22 Conditions for each OSDL enable/disable mode
page 196 of 296
Display OFF
Notes 1: Part of 24 ✕ 32 font is displayed.
2: In OSDL disable mode, character
codes “28016” to “2FF16” are used
in OSDS/P mode (no border).
3: As setting this make output of
font data indeterminate, do not use.
However, “3FE16” and “3FF16” can
be used as character codes of
blank font output in OSDP mode.
32
May 18, 2004
OSDL
00016
to
0FF16
28016
to
2FF16
Rev.1.00
OSDS/P
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
(2) OSD RAM (OSD RAM for character, addresses 040016 to 0EFF16)
The OSD RAM for character is allocated at addresses 040016 to 0EFF16, and is divided into a display
character code specification part, color code 1 specification part, and color code 2 specification part
for each block. The number of characters for 1 block (32- or 42-character mode) is selected by bit 1 of
the OSD control register 4. Tables 2.16.3 to 2.16.7 show the address map.
For example, to display 1 character position (the left edge) in block 1, write the character code in
address 040016, write color code 1 at 040116, and write color code 2 at 048016. The structure of the
OSD RAM is shown in Figure 2.16.23.
Note : For blocks of the following dot sizes, the 3nth (n = 1 to 14) character is skipped as compared
with ordinary block.
■In OSDL mode: all dot size.
■In OSDS and CDOSD modes of layer 2: 1.5Tc ✕ 1/2H or 1.5Tc ✕ 1H
Accordingly, maximum 22 characters (32-character mode)/28 characters (42-character mode)
are only displayed in 1 block. Blocks with dot size of 1TC ✕ 1/2H and 1TC ✕ 1H, or blocks on the
layer 1. The RAM data for the 3nth character does not effect the display. Any character data can
be stored here. And also, note the following only in 32-character mode. As the character is
displayed in the 28th’s character area in 42-character mode, set ordinarily.
• In OSDS mode
The character is not displayed, and only the left 1/3 part of the 22nd character back
ground is displayed in the 22nd’s character area. When not displaying this background, set transparent for character background color.
• In OSDL mode
Set a blank character or a character of transparent color to the 22nd character.
• In CDOSD mode
The character is not displayed, and color palette color specified by bits 3 to 6 of color
code 1 can be output in the 22nd’s character area (left 1/3 part).
Display
sequence
RAM
address
order
1
2
3
4
5
6
1
2
4
5
7
8
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22
10 11 13 14 16 17 19 20 22 23 25 26 28 29 31 32
• 1.5Tc size block
• OSDL block
Display
sequence 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
RAM
address 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
order
Figure 2.16.23 RAM data for 3rd character (in 32-character mode)
Rev.1.00
May 18, 2004
page 197 of 296
• 1Tc size block
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
Table 2.16.3 Contents of OSD RAM (1st to 32nd character)
Block
Block 1
Block 2
Block 3
Block 4
Block 5
Block 6
Block 7
Block 8
Block 9
Block 10
Rev.1.00
Display Position (from left)
1st character
2nd character
:
31st character
32nd character
1st character
2nd character
:
31st character
32nd character
1st character
2nd character
:
31st character
32nd character
1st character
2nd character
:
31st character
32nd character
1st character
2nd character
:
31st character
32nd character
1st character
2nd character
:
31st character
32nd character
1st character
2nd character
:
31st character
32nd character
1st character
2nd character
:
31st character
32nd character
1st character
2nd character
:
31st character
32nd character
1st character
2nd character
:
31st character
32nd character
May 18, 2004
page 198 of 296
Character Code Specification
040016
040216
:
043C16
043E16
044016
044216
:
047C16
047E16
050016
050216
:
053C16
053E16
054016
054216
:
057C16
057E16
060016
060216
:
063C16
063E16
064016
064216
:
067C16
067E16
070016
070216
:
073C16
073E16
074016
074216
:
077C16
077E16
080016
080216
:
083C16
083E16
084016
084216
:
087C16
087E16
Color Code 1 Specification
040116
040316
:
043D16
043F16
044116
044316
:
047D16
047F16
050116
050316
:
053D16
053F16
054116
054316
:
057D16
057F16
060116
060316
:
063D16
Color Code 2 Specification
048016
048216
:
04BC16
04BE16
04C016
04C216
:
04FC16
04FE16
058016
058216
:
05BC16
05BE16
05C016
05C216
:
05FC16
05FE16
068016
068216
:
06BC16
063F16
064116
064316
:
067D16
067F16
070116
070316
:
073D16
073F16
074116
074316
:
077D16
077F16
080116
080316
:
083D16
083F16
084116
084316
:
087D16
087F16
06BE16
06C016
06C216
:
06FC16
06FE16
078016
078216
:
07BC16
07BE16
07C016
07C216
:
07FC16
07FE16
088016
088216
:
08BC16
08BE16
08C016
08C216
:
08FC16
08FE16
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
Table 2.16.4 Contents of OSD RAM (1st to 32nd character) (continued)
Block
Block 11
Block 12
Block 13
Block 14
Block 15
Block 16
Rev.1.00
Display Position (from left)
1st character
2nd character
:
31st character
32nd character
1st character
2nd character
:
31st character
32nd character
1st character
2nd character
:
31st character
32nd character
1st character
2nd character
:
31st character
32nd character
1st character
2nd character
:
31st character
32nd character
1st character
2nd character
:
31st character
32nd character
May 18, 2004
page 199 of 296
Character Code Specification
090016
090216
:
093C16
093E16
094016
094216
:
097C16
097E16
0A0016
0A0216
:
0A3C16
0A3E16
0A4016
0A4216
:
0A7C16
0A7E16
0B0016
0B0216
:
0B3C16
Color Code 1 Specification
090116
090316
:
093D16
093F16
094116
094316
:
097D16
097F16
0A0116
0A0316
:
0A3D16
0A3F16
0A4116
0A4316
:
0A7D16
0A7F16
0B0116
0B0316
:
0B3D16
Color Code 2 Specification
098016
098216
:
09BC16
09BE16
09C016
09C216
:
09FC16
09FE16
0A8016
0A8216
:
0ABC16
0ABE16
0AC016
0AC216
:
0AFC16
0AFE16
0B8016
0B8216
:
0BBC16
0B3E16
0B4016
0B4216
:
0B7C16
0B7E16
0B3F16
0B4116
0B4316
:
0B7D16
0B7F16
0BBE16
0BC016
0BC216
:
0BF016
0BFE16
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
Table 2.16.5 Contents of OSD RAM (33rd to 42nd character)
Block
Block 1
Block 2
Block 3
Block 4
Block 5
Block 6
Block 7
Rev.1.00
Display Position (from left)
33rd character
34th character
:
39th character
40th character
41st character
42nd character
33rd character
34th character
:
39th character
40th character
41st character
42nd character
33rd character
34th character
:
39th character
40th character
41st character
42nd character
33rd character
34th character
:
39th character
40th character
41st character
42nd character
33rd character
34th character
:
39th character
40th character
41st character
42nd character
33rd character
34th character
:
39th character
40th character
41st character
42nd character
33rd character
34th character
:
39th character
40th character
41st character
42nd character
May 18, 2004
page 200 of 296
Character Code Specification
0C0016
0C0216
:
0C0C16
0C0E16
0E0016
0E0216
0C1016
0C1216
:
0C1C16
Color Code 1 Specification
0C0116
0C0316
:
0C0D16
0C0F16
0E0116
0E0316
0C1116
0C1316
:
0C1D16
Color Code 2 Specification
0C8016
0C8216
:
0C8C16
0C8E16
0E8016
0E8216
0C9016
0C9216
:
0C9C16
0C1E16
0E0816
0E0A16
0C2016
0C2216
:
0C1F16
0E0916
0E0B16
0C2116
0C2316
:
0C9E16
0E8816
0E8A16
0CA016
0CA216
:
0C2C16
0C2D16
0CAC16
0C2E16
0E1016
0E1216
0C3016
0C3216
:
0C3C16
0C3E16
0E1816
0E1A16
0C4016
0C4216
:
0C4C16
0C4E16
0E2016
0E2216
0C2F16
0E1116
0E1316
0C3116
0C3316
:
0C3D16
0C3F16
0E1916
0E1B16
0C4116
0C4316
:
0C4D16
0C4F16
0E2116
0E2316
0CAE16
0E9016
0E9216
0CB016
0CB216
:
0CBC16
0CBE16
0E9816
0E9A16
0CC016
0CC216
:
0CCC16
0CCE16
0EA016
0EA216
0C5016
0C5216
:
0C5C16
0C5E16
0E2816
0E2A16
0C6016
0C6216
:
0C6C16
0C5116
0C5316
:
0C5D16
0C5F16
0E2916
0E2B16
0C6116
0C6316
:
0C6D16
0CD016
0CD216
:
0CDC16
0CDE16
0EA816
0EAA16
0CE016
0CE216
:
0CEC16
0C6E16
0E3016
0E3216
0C6F16
0E3116
0E3316
0CEE16
0EB016
0EB216
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
Table 2.16.6 Contents of OSD RAM (33rd to 42nd character) (continued)
Block
Block 8
Block 9
Display Position (from left)
33rd character
34th character
:
39th character
40th character
41st character
42nd character
33rd character
34th character
:
39th character
40th character
41st character
42nd character
33rd character
Block 10
34th character
:
39th character
40th character
41st character
42nd character
33rd character
Block 11
Block 12
Block 13
Block 14
Rev.1.00
May 18, 2004
34th character
:
39th character
40th character
41st character
42nd character
33rd character
34th character
:
39th character
40th character
41st character
42nd character
33rd character
34th character
:
39th character
40th character
41st character
42nd character
33rd character
34th character
:
39th character
40th character
41st character
42nd character
page 201 of 296
Character Code Specification
0C7016
0C7216
:
0C7C16
0C7E16
0E3816
0E3A16
0D0016
0D0216
:
0D0C16
0D0E16
0E4016
0E4216
0D1016
0D1216
:
0D1C16
0D1E16
0E4816
0E4A16
0D2016
0D2216
:
0D2C16
0D2E16
0E5016
0E5216
0D3016
0D3216
:
0D3C16
0D3E16
0E5816
0E5A16
0D4016
0D4216
:
0D4C16
0D4E16
0E6016
0E6216
0D5016
0D5216
:
0D5C16
0D5E16
0E6816
0E6A16
Color Code 1 Specification
0C7116
0C7316
:
0C7D16
0C7F16
0E3916
0E3B16
0D0116
0D0316
:
0D0D16
0D0F16
0E4116
0E4316
0D1116
0D1316
:
0D1D16
0D1F16
0E4916
0E4B16
0D2116
0D2316
:
0D2D16
0D2F16
0E5116
0E5316
0D3116
0D3316
:
0D3D16
0D3F16
0E5916
0E5B16
0D4116
0D4316
:
0D4D16
0D4F16
0E6116
0E6316
0D5116
0D5316
:
0D5D16
0D5F16
0E6916
0E6B16
Color Code 2 Specification
0CF016
0CF216
:
0CFC16
0CFE16
0EB816
0EBA16
0D8016
0D8216
:
0D8C16
0D8E16
0EC016
0EC216
0D9016
0D9216
:
0D9C16
0D9E16
0EC816
0ECA16
0DA016
0DA216
:
0DAC16
0DAE16
0ED016
0ED216
0DB016
0DB216
:
0DBC16
0DBE16
0ED816
0EDA16
0DC016
0DC216
:
0DCC16
0DCE16
0EE016
0EE216
0DD016
0DD216
:
0DDC16
0DDE16
0EE816
0EEA16
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
Table 2.16.7 Contents of OSD RAM (33rd to 42nd character) (continued)
Block
Block 15
Block 16
Rev.1.00
Display Position (from left)
33rd character
34th character
:
39th character
40th character
41st character
42nd character
33rd character
34th character
:
39th character
40th character
41st character
42nd character
May 18, 2004
page 202 of 296
Character Code Specification
0D6016
Color Code 1 Specification
0D6116
Color Code 2 Specification
0DE016
0D6216
:
0D6C16
0D6E16
0E7016
0E7216
0D7016
0D7216
:
0D7C16
0D7E16
0E7816
0E7A16
0D6316
:
0D6D16
0D6F16
0E7116
0E7316
0D7116
0D7316
:
0D7D16
0D7F16
0E7916
0E7B16
0DE216
:
0DEC16
0DEE16
0EF016
0EF216
0DF016
0DF216
:
0DFC16
0DFE16
0EF816
0EFA16
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
Blocks 1 to 16
b0
b7
C9 RC21 RC20 RC17 RC16 RC15 RC14 RC13 RC12 RC11 C8
C7
b2
b1
b0
b7
Color code 2
C6
C5
Color code 1
C4
C3
C2
C1
C0
Character code
OSDS/L/P mode
Bit name
Function
CC mode
Bit name
Function
Bit
b0
CDOSD mode
Bit name
Function
C0
C1
C2
Character
C3
code
C4
(Low-order 9 bits)
Character
Specify
character code in
code
(Low-order 9 bits)
OSD ROM
C5
CD code
Specify
(7 bits)
character code in
Specify
character code
in
OSD ROM
(color dot)
OSD ROM
C6
C7
C8
Not used
RC11
(See note 3)
Color palette
selection bit 1
Color palette
selection bit 2
RC13
0: Italic OFF
0: Flash OFF
1: Flash ON
RC16 Underline control 0: Underline OFF
1: Underline ON
RC17
C9
0: OUT2 output OFF
Color palette Specify color palette
for background
selection bit 0
(See note 3)
Color palette
selection bit 1
Color palette Specify color palette
selection bit 0
for character
Color palette
selection bit 1
OUT2 output
control
1: OUT2 output ON
Character background
RC21
Character background
RC20
OUT2 output
control
Color palette
selection bit 0
Color palette
selection bit 3
Character background
Flash control
(See note 3)
Color palette
selection bit 1
Color palette
selection bit 2
1: Italic ON
RC15
Color palette Specify color palette
selection bit 0
for character
(See note 3)
0: OUT2 output OFF
1: OUT2 output ON
Dot color
Italic control
RC14
Character
Character
RC12
Color palette Specify color palette
selection bit 0
for character
Color palette
selection bit 1
Color palette
selection bit 2
Specify a dot
which selects
color palette 0
by OSD ROM
(See note 4)
Color palette
selection bit 3
OUT2 output
control
0: OUT2 output OFF
1: OUT2 output ON
Color palette Specify color palette
for background
selection bit 2
(See note 3)
Not used
Specify character
code in OSD ROM
Not used
Color palette
selection bit 3
Character code
Specify character Character code
(High-order 1 bit) code in OSD ROM (High-order 1 bit)
Notes 1: Read value of bits 3 to 7 of the color code 2 is undefined.
2: For “not used” bits, the write value is read.
3: Refer to Figure 2.16.24.
4: Only in CDOSD mode, a dot which selects color palette 0 is colored to the color palette set by RC13 to RC16 of
OSD RAM in character units. When the character size is 1.5TC ✕ 1H or 1.5TC ✕ 1/2H, however, set RCI3 to RC16
and RC17 of all characters (including the 3nth character) within the same block to the same value.
Figure 2.16.24 Structure of OSD RAM
Rev.1.00
May 18, 2004
page 203 of 296
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
(3) OSD RAM (OSD RAM for SPRITE, addresses 100016 to 13E716)
The OSD RAM for SPRITE fonts 1 and 2, consisting of 4 planes for each font, is assigned to addresses 100016 to 13E716. Each plane corresponds to each color palette selection bit and the color
palette of each dot is determined from among 16 kinds.
Table 2.16.8 OSD RAM address (SPRITE font 1)
Planes
Plane 3
Plane 2
(Color paleltte selection bit 3)
9 to 16
Plane 1
(Color paleltte selection bit 2)
9 to 16
Plane 0
(Color paleltte selection bit 1)
9 to 16
(Color paleltte selection bit 0)
Dots
1 to 8
17 to 24
25 to 32
1 to 8
17 to 24
25 to 32
1 to 8
17 to 24 25 to 32
1 to 8
Bits
b7 to b0 b7 to b0 b7 to b0
b7 to b0
b7 to b0 b7 to b0 b7 to b0
b7 to b0
b7 to b0 b7 to b0
b7 to b0 b7 to b0
b7 to b0 b7 to b0
9 to 16
b7 to b0
17 to 24
25 to 32
Line 1
10C016
10C116
11C016
11C116
108016
108116
118016
118116
104016
104116
114016
114116
100016
100116
110016
110116
Line 2
•
•
•
Line 19
10C216
•
•
•
10E416
10C316
•
•
•
10E516
11C216
•
•
•
11E416
11C316
•
•
•
11E516
108216
•
•
•
10A416
108316
•
•
•
10A516
118216
•
•
•
11A416
118316
•
•
•
11A516
104216
•
•
•
106416
104316
•
•
•
106516
114216
•
•
•
116416
114316
•
•
•
116516
100216
•
•
•
102416
100316
•
•
•
102516
110216
•
•
•
112416
110316
•
•
•
112516
Line 20
10E616
10E716
11E616
11E716
10A616
10A716
11A616
11A716
106616
106716
116616
116716
102616
102716
112616
112716
b7 to b0
Table 2.16.9 OSD RAM address (SPRITE font 2)
Planes
Plane 3
Plane 2
(Color paleltte selection bit 3)
9 to 16
Plane 1
(Color paleltte selection bit 2)
9 to 16
Plane 0
(Color paleltte selection bit 1)
9 to 16
(Color paleltte selection bit 0)
Dots
1 to 8
17 to 24
25 to 32
1 to 8
17 to 24
25 to 32
1 to 8
17 to 24 25 to 32
1 to 8
Bits
b7 to b0 b7 to b0 b7 to b0
b7 to b0
b7 to b0 b7 to b0 b7 to b0
b7 to b0
b7 to b0 b7 to b0
b7 to b0 b7 to b0
b7 to b0 b7 to b0
b7 to b0
Line 1
12C016
12C116
13C016
13C116
128016
128116
138016
138116
124016
124116
134016
134116
120016
120116
130016
130116
Line 2
•
•
•
Line 19
12C216
•
•
•
12E416
12C316
•
•
•
12E516
13C216
•
•
•
13E416
13C316
•
•
•
13E516
128216
•
•
•
12A416
128316
•
•
•
12A516
138216
•
•
•
13A416
138316
•
•
•
13A516
124216
•
•
•
126416
124316
•
•
•
126516
134216
•
•
•
136416
134316
•
•
•
136516
120216
•
•
•
122416
120316
•
•
•
122516
130216
•
•
•
132416
130316
•
•
•
132516
Line 20
12E616
12E716
13E616
13E716
12A616
12A716
13A616
13A716
126616
126716
136616
136716
122616
122716
132616
132716
Plane 3
Dot structure of SPRITE font
Plane 2
Dot number
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
1
2
3
4
5
6
7
8
9
Line 10
number 11
12
13
14
15
16
17
18
19
20
Rev.1.00
May 18, 2004
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
page 204 of 296
Plane 1
Plane 0
9 to 16
17 to 24
25 to 32
b7 to b0
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
2.16.7 Character Color
As shown in Figure 2.16.25, there are 16 built-in color codes. Color palette 0 is fixed at transparent, and
color palette 8 is fixed at black. The remaining 14 colors can be set to any of the 512 colors available. The
setting procedure for character colors is as follows:
• CC mode ........................................ 8 kinds
Color palette selection range (color palettes 0 to 7 or 8 to 15) can be selected by bit 0 of the OSD control
register 3 (address 020716). Color palettes are set by bits RC11 to RC13 of the OSD RAM from among
the selection range.
• OSDS/L/P mode ........................... 16 kinds
Color palettes are set by bits RC11 to RC14 of the OSD RAM.
• CDOSD mode ............................... 16 kinds
Color palettes are set in dot units according to CD font data.
Only in CDOSD mode, a dot which selects color palette 0 or 8 is colored to the color palette set by RC13
to RC16 of OSD RAM in character units (refer to Figure 2.16.25).
• SPRITE display ............................ 16 kinds
Color palettes are set in dot units according to the CD font data.
Notes 1: Color palette 8 is always selected for bordering and solid space output (OUT 1 output) regardless
of the set value in the register.
2: Color palette 0 (transparent) and the transparent setting of other color palettes will differ. When
there are multiple layers overlapping (on top of each other, piled up), and the priority layer is color
palette 0 (transparent), the bottom layer is displayed, but if the priority layer is the transparent
setting of any other color palette, the background is displayed without displaying the bottom layer
(refer to Figure 2.16.27).
2.16.8 Character Background Color
The display area around the characters can be colored in with a character background color. Character
background colors are set in character units.
• CC mode ........................................ 4 kinds
Color palette selection range (color codes 0 to 3, 4 to 7, 8 to 11, or 12 to 15) can be selected by bits 1 and
2 of the OSD control register 3 (address 020716). Color palettes are set by bits RC20 and RC21 of the
OSD RAM from among the selection range.
• OSDS/L/P mode ........................... 16 kinds
Color palettes are set by bits RC15, RC16, RC20, and RC21 of the OSD RAM.
Note: The character background is displayed in the following part:
(character display area) – (character font) – (border).
Accordingly, the character background color and the color signal for these two sections cannot be
mixed.
Rev.1.00
May 18, 2004
page 205 of 296
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
CC mode
(background)
CC mode
(character)
OSDS/L/P mode (character, background)
CDOSD mode (character) (See note 2)
SPRITE display
Color palette 0 (Transparent)
Color palette 1
Color palette 2
Color palette 3
Color palette 4
Color palette 5
Color palette 6
Color palette 7
Color palette 8 (Black)
Color palette 9
Select one
palette in
screen units.
(See note 1)
Select either
palette in
screen units.
(See note 1)
Any palette
can be
selected.
Color palette 10
Color palette 11
Color palette 12
Color palette 13
Color palette 14
Color palette 15
Notes 1: Color palettes are selected by OSD control register 3 (address 0207 16).
2: Only in CDOSD mode, a dot which selects color palette 0 or 8 is colored to
of OSD RAM in character units.
Figure 2.16.25 Color palette selection
Rev.1.00
May 18, 2004
page 206 of 296
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
Dot area specified to color palette 1
Set values of OSD RAM (RC16 to RC13)
0001
0010
0000
Transparent
Black
Blue
Dot area specified to color palette 0
When setting black and blue to color palettes 1 and 2, respectively
(only in CDOSD mode).
Figure 2.16.26 Set of color palette 0 or 8 in CDOSD mode
Color palette 1 (Transparent)
Layer 1
(CC mode)
26 dots
Color palette 0 (Transparent)
Black
Layer 2
(OSDS/L mode)
20 dots
Color palette 2 (Blue)
26 dots
20 dots
Blue
Transparent
(video signal)
When layer 1 has priority.
Color palette 8 (Black)
Figure 2.16.27 Difference between color palette 0 (transparent) and transparent setting of other
color palettes
Rev.1.00
May 18, 2004
page 207 of 296
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
OSD control register 3
b7 b6 b5 b4 b3 b2 b1 b0
Address
020716
Symbol
OC3
0
Bit symbol
Bit name
OC30
CC mode character
color selection bit
OC31
CC mode character
background color
selection bits
(See note)
OC32
When reset
0016
Reserved bits
Function
R W
0: Color palettes 0 to 7
1: Color palettes 8 to 15
b2 b1
0
0
1
1
0: Color palettes 0 to 3
1: Color palettes 4 to 7
0: Color palettes 8 to 11
1: Color palettes 12 to 15
Must always be set to “0”
OC34
Flash cycle
selection bit
0: 1 cycle = VSYNC cycle ✕ 32
1: 1 cycle = VSYNC cycle ✕ 64
OC35
OSDS/L/P mode
window control bit
0: Window OFF
1: Window ON
OC36
CC mode window
control bit
0: Window OFF
1: Window ON
OC37
CDOSD mode
window control bit
0: Window OFF
1: Window ON
Note: Color palette 8 is always selected for solid space (when OUT1 output is
selected), regardless of value of this register.
Figure 2.16.28 OSD control register 3
Rev.1.00
May 18, 2004
page 208 of 296
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
Color palette register i
(b15)
(b8)
b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0
S
SymbolS
AddressesS
CRi (i = 1 to 7)SS Even addresses within addresses 0240 16 to 024D16, S
S
Odd addresses within addresses 0240 16 to 024D16
CRi (i = 8 to 15)SS Even addresses within addresses 024E 16 to 025B16, S
S
Odd addresses within addresses 024E 16 to 025B16
Bit symbol
Bit name
CRi_2 to CRi_0 R signal output
control bits
Function
b2S b1S b0
0SS
0SS
0SS
0SS
1SS
1SS
1SS
1SS
0S
0S
1S
1S
0S
0S
1S
1S
0 : V SS
1 : 1/7V
0 : 2/7V
1 : 3/7V
0 : 4/7V
1 : 5/7V
0 : 6/7V
1 : 7/7V
Nothing is assined.
In an attempt to write to this bit, write “0.”
The value, if read, turns out to be indeterminate.
CRi_6 to CRi_4 G signal output
control bits
b6S b5S b4
0SS
0SS
0SS
0SS
1SS
1SS
1SS
1SS
0S
0S
1S
1S
0S
0S
1S
1S
0 : V SS
1 : 1/7V
0 : 2/7V
1 : 3/7V
0 : 4/7V
1 : 5/7V
0 : 6/7V
1 : 7/7V
Nothing is assined.
In an attempt to write to this bit, write “0.”
The value, if read, turns out to be indeterminate.
CRi_10 to CRi_8 B signal output
control bits
b2S b1S b0
0SS
0SS
0SS
0SS
1SS
1SS
1SS
1SS
0S
0S
1S
1S
0S
0S
1S
1S
0 : V SS
1 : 1/7V
0 : 2/7V
1 : 3/7V
0 : 4/7V
1 : 5/7V
0 : 6/7V
1 : 7/7V
Nothing is assined.
In an attempt to write to this bit, write “0.”
The value, if read, turns out to be indeterminate.
CRi_12
OUT1 signal output
control bit
0: No output
1: Output
Nothing is assined.
In an attempt to write to this bit, write “0.”
The value, if read, turns out to be indeterminate.
Figure 2.16.29 Color palette register i (i = 1 to 7, 9 to 15)
Rev.1.00
May 18, 2004
page 209 of 296
When reset
Indeterminate
Indeterminate
R W
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
2.16.9 OUT1, OUT2 Signals
The OUT1, OUT2 signals are used to control the luminance of the video signal. The output waveform of
the OUT1, OUT2 signals is controlled by bit 6 of the color palette register i (refer to Figure 2.16.29), bits
0 to 2 of the block control register i (refer to Figure 2.16.4) and RC17 of OSD RAM. The setting values for
controlling OUT1, OUT2 and the corresponding output waveform is shown in Figure 2.16.30.
Conditions
OUT2 output
control
(RC 17 of
OSD RAM)
Border output
OUT1 signal output control bit
(See note 2)
bit12(CRi12) of color pallet
Output
register i
Background
Character
waveform
0
H
L
1
H
L
0
H
L
1
H
L
0
H
L
1
H
L
0
H
L
1
H
L
H
L
0
No output
1
OUT1
signal
✕
0
Output
(See note 1)
1
0
✕
✕
✕
1
✕
✕
✕
OUT2
signal
H
L
Notes 1: This control is only valid in the OSDS/P mode. It is invalid in CC/CDOSD/OSDL mode .
2: In the CDOSD mode, coloring is performed for each dot. Accordingly, OUT1 outputs to dots
which bit 12 (CRi12) of the color pallet register i is set to “0.”
3: OUT2 cannot be output in sprite OSD.
4: ✕ is an arbitrary value.
Figure 2.16.30 Setting value for controlling OUT1, OUT2 and corresponding output waveform
Rev.1.00
May 18, 2004
page 210 of 296
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
2.16.10 Attribute
The attributes (flash, underline, italic fonts) are controlled to the character font. The attributes for each character are specified
by RC14 to RC16 of OSD RAM (refer to Figure 2.16.26). The attributes to be controlled are different depending on each
mode.
CC mode ................... Flash, underline, italic for each character
OSDS/P mode .......... Border (all bordered, shadow bordered can be selected) for each block
(1) Under line
The underline is output at the 23rd and 24th lines in vertical direction only in the CC mode. The
underline is controlled by RC16 of OSD RAM. The color of underline is the same color as that of the
character font.
(2) Flash
The parts of the character font, the underline, and the character background are flashed only in the CC mode.
The flash for each character is controlled by RC15 of OSD RAM. The ON/OFF for flash is controlled by bit 3 of the
OSD control register 1 (refer to Figure 2.16.3). When this bit is “0, ” only character font and underline flash. When
“1,” for a character without solid space output, R, G, B and OUT1 (all display area) flash, for a character with solid
space output, only R, G, and B (all display area) flash. The flash c ycle bases on the VSYNC count and is
selected by bit 4 of OSD control register 3.
<NTSC method>
■ When bit 4 = “0”
· VSYNC cycle ✕ 24 ≈ 400 ms (at flash ON)
· VSYNC cycle ✕ 8 ≈ 133 ms (at flash OFF)
■ When bit 4 = “1”
· VSYNC cycle ✕ 48 ≈ 800 ms (at flash ON)
· VSYNC cycle ✕ 8 ≈ 133 ms (at flash OFF)
(3) Italic
The italic is made by slanting the font stored in OSD ROM to the right only in the CC mode. The italic
is controlled by RC14 of OSD RAM.
The
display example attribute is shown in Figure 2.16.30. In this case, “R” is displayed.
Notes 1: When setting both the italic and the flash, the italic character flashes.
2: When a flash character (with flash character background) adjoin on the right side of a non-flash italic
character, parts out of the non-flash italic character is also flashed.
3: OUT2 is not flashed.
4: When the pre-divide ratio = 1, the italic character with slant of 1 dot ✕ 5 steps is displayed ; when the
pre-divide ratio = 2, the italic character with slant of 1/2 dot ✕ 10 steps is displayed (refer to Figure
2.16.30 (c), (d)). However, when displaying the italic character with the pre-divide ratio = 1, set the
OSD clock frequency to 11 MHz to 14 MHz.
5: The boundary of character color is displayed in italic. However, the boundary of character background
color is not affected by the italic (refer to Figure 2.16.31).
6: The adjacent character (one side or both side) to an italic character is displayed in italic even when the
character is not specified to display in italic (refer to Figure 2.16.31).
7: When displaying the 32nd character (in 32-character mode)/42nd character (in 42-character mode) in
the italic and when solid space is off (OC14 = “0”), parts out of character area is not displayed (refer to
Figure 2.16.31).
8: When use the italic character which the pre-divide ratio = 1, do not use the character in which dot data
exists for the right end of a font.
Rev.1.00
May 18, 2004
page 211 of 296
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
Color code 1
Color code 1
Bit 6
Bit 4
Bit 6
0
0
1
(a) Ordinary
Bit 4
0
(b) Underline
Color code 1
Color code 1
Bit 6
Bit 4
Bit 6
Bit 4
0
1
0
1
(c) Italic (pre-divide ratio = 1)
(d) Under line and Italic (pre-divide ratio = 2)
Color code
Bit 4
Bit 5
Bit 6
(RC 16) (RC 15) (RC 16)
flash
flash
flash
ON
OFF
ON
OFF
(e) Under line and Italic and flash
Figure 2.16.31 Example of attribute display (in CC mode)
Rev.1.00
May 18, 2004
page 212 of 296
1
1
1
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
26th chracter
32nd chracter
(Refer to “12.16.10 Notes 6, 7”)
(Refer to “12.16.10 Notes 5, 6”)
Bit 4 of color
code 1
1
0
0
Notes 1 : The dotted line is the boundary of character color.
2 : When bit 4 of OSD control register 1 is “0.”
Figure 2.16.32 Example of italic display
Rev.1.00
May 18, 2004
page 213 of 296
1
1
0
1
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
(4) Border
The border is output in the OSDS/P mode. The all bordered (bordering around of character font) and
the shadow bordered (bordering right and bottom sides of character font) are selected (refer to Figure
2.16.33) by bit 2 of the OSD control register 1 (refer to Figure 2.16.3). The ON/OFF switch for borders
can be controlled in block units by bits 0 to 2 of the block control register i (refer to Figure 2.16.4).
The OUT1 signal is used for border output. The border color is fixed at color palette 8 (block). The
border color for each screen is specified by the border color register i.
The horizontal size (x) of border is 1TC (OSD clock cycle divided in the pre-divide circuit) regardless of
the character font dot size. However, only when the pre-divide ratio = 2 and character size = 1.5TC, the
horizontal size is 1.5TC. The vertical size (y) different depending on the screen scan mode and the
vertical dot size of character font.
Notes 1 : The border dot area is the shaded area as shown in Figure 2.16.35.
2 : When the border dot overlaps on the next character font, the character font has priority
(refer to Figure 2.16.36 A). When the border dot overlaps on the next character back
ground, the border has priority (refer to Figure 2.16.36 B).
3 : The border in vertical out of character area is not displayed (refer to Figure 2.16.36).
All bordered
Shadow bordered
Figure 2.16.33 Example of border display
y
x
Scan mode
Border
dot size
Vertical dot size of
character font
Normal scan mode
1/2H
1/2H
Figure 2.16.34 Horizontal and vertical size of border
Rev.1.00
May 18, 2004
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1/2H, 1H, 2H, 3H
1TC (OSD clock cycle divided in pre-divide circuit)
1.5TC when selecting 1.5TC for character size.
Horizontal size (x)
Vertical size (y)
1H, 2H, 3H
Bi-scan mode
1H
1H
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
OSDS/L/P mode
16 dots
12 dots
20 dots
20 dots
Character
font area
1 dot width of border
1 dot width of border
1 dot width of border
Figure 2.16.35 Border area
Character boundary
B
Figure 2.16.36 Border priority
Rev.1.00
May 18, 2004
page 215 of 296
Character boundary
A
Character boundary
B
1 dot width of border
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
2.16.11 Automatic Solid Space Function
This function generates automatically the solid space (OUT1 or OUT2 blank output) of the character area
in the CC mode.
The solid space is output in the following area :
• the character area except character code “00916 ”
•the character area on the left and right sides
This function is turned on and off by bit 4 of the OSD control register 1 (refer to Figure 2.16.3).
OUT1 or OUT2 output is selected by bit 3 of the OSD control register 2.
Notes 1: When selecting OUT1 as solid space output, character background color with solid space
output is fixed to color palette 8 (black) regardless of setting.
2: When selecting any font except blank font as the character code “00916,” the set font is output.
Table 2.16.10 Setting for automatic solid space
0
Bit 4 of OSD control register 1
1
0
Bit 3 of OSD control register 2
0
RC17 of OSD RAM
OUT1 output signal
1
1
•Character font area
•Character background
area
0
0
1
0
1
1
•Character font area
•Solid space area
•Character background
area
0
1
•Character font area
•Character background
area
OUT2 output signal
OFF
•Character
display area
OFF
•Character
display area
OFF
•Solid space
•Character
•Solid space •Character
display area
display area
When setting the character code “00516” as the character A, “00616” as the character B.
(OSD RAM)
005 009 009 009 006 006 •
16
16
16
16
16
• •
16
006
16
(Display screen)
• • •
1st
2nd
character character
No solid space
output
Figure 2.16.37 Display screen example of automatic solid space
Rev.1.00
May 18, 2004
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32nd character (in 32-character mode)
42nd character (in 42-character mode)
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
2.16.12 Particular OSD Mode Block
This function can display with mixing the fonts below within the OSDP mode block.
<horizontal dot structure with vertical dot structure of 20 dots>
• 16 dots
• 12 dots
• 8 dots
• 4 dots
Each font is selected by a character code. Figure 2.16.38 shows the display example of particular OSD
mode block and Table 2.16.11 shows the corresponding between character codes and display fonts.
Note: As for 8 ✕ 20-dot and 4 ✕ 20-dot fonts, only these character background color can be displayed.
And also, any character is not displayed on the right side area nor any following areas of these
fonts.
Any character is not displayed on the right side area nor any following areas of this font.
16 dots
12 dots
16 dots
16 dots
16 dots
16 dots
12 dots
16 dots
16 dots
16 dots
16 dots
12 dots
4 dots
OSDP mode
12 dots
16 dots
16 dots
12 dots
16 dots
16 dots
16 dots
16 dots
OSDP mode
16 dots
16 dots
16 dots
16 dots
16 dots
16 dots
16 dots
16 dots
16 dots
8 dots
OSDP mode
Any character is not displayed on the right side area nor any following areas of this font.
Figure 2.16.38 Display example of OSD mode block
Rev.1.00
May 18, 2004
page 217 of 296
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
Table 2.16.11 Corresponding between character codes and display fonts
Character code
Display fonts
Notes
16 dots
(except 10016, 18016,
20016, 28016)
20 dots
00016 to 0EF16,
10016 to 2FF16
12 dots
0F016 to 0FD16
Not displayed
• The left 12-dot part (16 ✕ 12 dots) of set
font is displayed.
20 dots
• In CC and OSDS modes, entire part
(16 ✕ 20 dots) of set font is displayed.
8 dots
• The blank font (only character background)
is displayed.
• Any character is not displayed on the right
side area nor any following areas of this
font.
20 dots
3FE16
• Do not set this font for the 1st character
(left edge) of a block.
4 dots
• The blank font (only character background)
is displayed.
20 dots
3FF16
• Any character is not displayed on the right
side area nor any following areas of this
font.
• Do not set this font for the 1st character
(left edge) of a block.
Rev.1.00
May 18, 2004
page 218 of 296
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
2.16.13 Multiline Display
This microcomputer can ordinarily display 16 lines on the CRT screen by displaying 16 blocks at different
vertical positions. In addition, it can display up to 16 lines by using OSD1 interrupts.
An OSD1 interrupt request occurs at the point at which display of each block has been completed. In
other words, when a scanning line reaches the point of the display position (specified by the vertical
position registers) of a certain block, the character display of that block starts, and an interrupt occurs at
the point at which the scanning line exceeds the block. The mode in which an OSD1 interrupt occurs is
different depending on the setting of the OSD control register 2 (refer to Figure 2.16.7).
• When bit 7 of the OSD control register 2 is “0”
An OSD1 interrupt request occurs at the completion of layer 1 block display.
• When bit 7 of the OSD control register 2 is “1”
An OSD1 interrupt request occurs at the completion of layer 2 block display.
Notes 1: An OSD1 interrupt does not occur at the end of display when the block is not displayed. In other
words, if a block is set to off display by the display control bit of the block control register i
(addresses 021016 to 021F16), an OSD1 interrupt request does not occur (refer to Figure
2.16.38 (A)).
2: When another block display appears while one block is displayed, an OSD1 interrupt request
occurs only once at the end of the another block display (refer to Figure 2.16.38 (B)).
3: On the screen setting window, an OSD1 interrupt occurs even at the end of the CC mode block
(off display) out of window (refer to Figure 2.16.38 (C)).
Block 1 (on display)
Block 2 (on display)
“OSD1 interrupt request”
“OSD1 interrupt request”
Block 3 (on display)
Block 1 (on display)
“OSD1 interrupt request”
Block 2 (on display)
“OSD1 interrupt request”
Block 3 (off display)
No
“OSD1 interrupt request”
“OSD1 interrupt request”
Block 4 (on display)
Block 4 (off display)
No
“OSD1 interrupt request”
“OSD1 interrupt request”
On display (OSD1 interrupt request occurs
at the end of block display)
Off display (OSD1 interrupt request does
not occur at the end of block display)
(A)
Block 1
“OSD1 interrupt request”
Block 1
Block 2
No
“OSD1 interrupt request”
Block 2
“OSD1 interrupt request”
“OSD1 interrupt request”
Block 3
“OSD1 interrupt request”
Window
(B)
(C)
Figure 2.16.39 Note on occurrence of OSD1 interrupt
Rev.1.00
May 18, 2004
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M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
2.16.14 SPRITE OSD Function
This is especially suitable for cursor and other displays as its function allows for display in any position,
regardless of the validity of block OSD displays or display positions. SPRITE font consists of 2 characters: SPRITE fonts 1 and 2. Each SPRITE font is a RAM font consisting of 32 horizontal dots ✕ 20 vertical
dots, 4 planes, and 4 bits of data per dot. Each plane has corresponding color palette selection bit, and
16 kinds of color palettes can be selected by the plane bit combination (three bits) for each dot. The color
palette is set in dot units according to the OSD RAM (SPRITE) contents from among the selection range.
It is possible to add arbitrary font data by software as the SPRITE fonts consist of RAM font.
The SPRITE OSD control register can control SPRITE display and dot size. The display position can
also be set independently of the block display by the SPRITE horizontal position registers and the sprite
horizontal vertical position registers. The vertical fonts 1 and 2 can be set independently. OSD2 interrupt
request occurs at each completion of font display. The horizontal position is set in 2048 steps in 2TOSC
units, and the vertical position is set in 1024 steps in 1TH units.
When SPRITE display overlaps with other OSD displays, SPRITE display is always given priority. However, the SPRITE display overlaps with the display which includes OUT2 output, OUT2 in the OSD is
output without masking.
Notes 1: The SPRITE OSD function cannot output OUT2.
2: When using SPRITE OSD, do not set HS ≤ “00316”, HS ≥ “80016.”
3: When using SPRITE OSD, do not set VSi = “00016,” VSi ≥ “40016.”
4: When displaying with SPRITE fonts 1 and 2 overlapped, the SPRITE font with a larger set value
as the vertical display start position is displayed. When the set values of the vertical display
start position are the same, the SPRITE font 1 is displayed.
dot
1
......
dot dot
16 17
......
dot
32
Line 1
......
SPRITE font 1
Video adjustment
Tint
Contrast
Color tone
Picture
Brightness
Line 20
Line 1
–••|••+
–••|••+
–••|••+
–••|••+
–••|••+
......
SPRITE font 2
Example of SPRITE display
Line 20
Example of SPRITE font
Figure 2.16.40 SPRITE OSD display example
Rev.1.00
May 18, 2004
page 220 of 296
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
SPRITE OSD control register
Symbol
SC
b7 b6 b5 b4 b3 b2 b1 b0
Bit symbol
Address
020116
When reset
XXX000002
Bit name
Function
SC0
SPRITE font 1
control bit
0: Do not display
1: Display
SC1
Pre-divide ratio
selection bit
0: Pre-divide ratio 1
1: Pre-divide ratio 2
SC2
Dot size selection
bits
b3
SC3
SC4
SPRITE font 2
control bit
0
0
1
1
b2
0: 1Tc ✕ 1/2H
1: 1Tc ✕ 1H
0: 2Tc ✕ 1H
1: 2Tc ✕ 2H
0: Do not display
1: Display
Nothing is assigned.
In an attempt to write to these bits, write “0.”
The value, if read, turns out to be “0.”
Notes 1: Tc is OSD clock cycle divided in pre-divide circuit.
2: H is HSYNC
Figure 2.16.41 SPRITE OSD control register
Rev.1.00
May 18, 2004
page 221 of 296
R W
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
SPRITE horizontal position register
(b15)
(b8)
b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0
Symbol
HS
Address
027916, 027816
Bit symbol
Bit name
HS10 to HS0
Horizontal display start
position control bits of
SPRITE font
When reset
Indeterminate
Function
R W
Horizontal display start position = 2TOSC ✕ n
(n: setting value, TOSC: OSD oscillation cycle)
Nothing is assined.
In an attempt to write to this bit, write “0.”
The value, if read, turns out to be indeterminate.
Note : Do not set HS ≤ “00316,” HS ≥ “80016.”
Figure 2.16.42 SPRITE horizontal position register
SPRITE vertical position register i
(b15)
(b8)
b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0
Symbol
VS1
VS2
Bit symbol
VSi9 to VSi0
Address
027516, 027416
027716, 027616
Bit name
Vertical display start
position control bits of
SPRITE font i (i = 1, 2)
Function
Vertical display start position = TH ✕ n
(n: setting value, TH: HSYNC cycle)
Nothing is assined.
In an attempt to write to this bit, write “0.”
The value, if read, turns out to be indeterminate.
Note : Do not set VSi = “00016,” VSi ≥ “40016” (i = 1, 2).
Figure 2.16.43 SPRITE vertical position register i (i = 1, 2)
Rev.1.00
May 18, 2004
page 222 of 296
When reset
Indeterminate
Indeterminate
R W
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
2.16.15 Window Function
The window function can be set windows on-screen and output OSD within only the area where the
window is set.
The ON/OFF for vertical window function is performed by bit 5 of the OSD control register 1 and is used
to select vertical window function or vertical blank function by bit 6 of the OSD control register 2. Accordingly, the vertical window function cannot be used simultaneously with the vertical blank function. The
display mode to validate the window function is selected by bits 5 to 7 of the OSD control register 3. The
top border is set by the top border control register (TBR) and the bottom border is set by the bottom
border control register (BBR).
The ON/OFF for horizontal window function is performed by bit 4 of the OSD control register 2 and is
used interchangeably for the horizontal blank function with bit 5 of the OSD control register 2. Accordingly, the horizontal blank function cannot be used simultaneously with the horizontal window function.
The display mode to validate the window function is selected by bits 5 to 7 of the OSD control register 3.
The left border is set by the left border control register (LBR), and the right border is set by the right
border control register (RBR).
Notes 1: Horizontal blank and horizontal window, as well as vertical blank and vertical window can not be
used simultaneously.
2: When the window function is ON by OSD control registers 1 and 2, the window function of
OUT2 is valid in all display mode regardless of setting value of the OSD control register 3 (bits
5 to 7). For example, even when make the window function valid in only CC mode, the function
of OUT2 is valid in OSDS/L/P and CDOSD modes.
3: As for SPRITE display, the window function does not operate.
Left border
of window
Right border
of window
Window
Top border
of window
A B C D E
F
G H
K L
I
CDOSD mode
J
M N O
CC mode
Window
P Q R S T
U V W X Y
OSDS/L/P mode
Screen
Figure 2.16.44 Example of window function (When CC mode is valid)
Rev.1.00
May 18, 2004
page 223 of 296
Bottom border
of window
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
2.16.16 Blank Function
The blank function can output blank (OUT1) area on all sides (vertical and horizontal) of the screen. This
provides the blank signal, wipe function, etc., when outputting a 3 : 4 image on a wide screen.
The ON/OFF for vertical blank function is performed by bit 5 of the OSD control register 1 and is used to
select vertical window function or vertical blank function by bit 6 of the OSD control register 2. Accordingly, the vertical blank function cannot be used simultaneously with the vertical window function. The top
border is set by the top border control register (TBR), and the bottom border is set by the bottom border
control register (BBR), in 1H units.
The ON/OFF for horizontal blank function is performed by bit 4 of the OSD control register 2 and is used
interchangeably for the horizontal window function with bit 5 of the OSD control register 2 . Accordingly,
the horizontal blank function cannot be used simultaneously with the horizontal window function. The left
border is set by the left border control register (LBR) and the right border is set by the right border control
register (RBR), in 4TOSC units.
The OSD output (except raster) in area with blank output is not deleted.
These blank signals are not output in the horizontal/vertical blanking interval.
Notes 1. Horizontal blank and horizontal window, as well as vertical blank and vertical window can not be
used simultaneously.
2. When using the window function, be sure to set “1” to bit 0 of OSD control register 1.
A
OUT1 B
4
A
Blank output
signal in
microcomputer
4
A'
H
OUT1
L
H
B
L
Blank output
signal in
microcomputer
H
A'
L
Output example of horizontal blank
Output example of top and vertical blank
Figure 2.16.45 Blank output example (when OSD output is B + OUT1)
Rev.1.00
May 18, 2004
page 224 of 296
L H L H
L H
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
Top border control register
(b15)
(b8)
b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TBR
Bit symbol
Address
020D16, 020C16
Bit name
When reset
Indeterminate
Function
TBR_9 to TBR_0 Top border control bits
R W
Top border position = TH ✕ n
(n: setting value, TH: HSYNC cycle)
Nothing is assined.
In an attempt to write to this bit, write “0.”
The value, if read, turns out to be indeterminate.
Notes 1 : Do not set TBR ≤ “00116,” TBR ≥ “40016.”
2 : Set as TBR < BBR.
Figure 2.16.46 Top border control register
Bottom border control register
(b15)
(b8)
b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0
Symbol
BBR
Bit symbol
Address
020F16, 020E16
Bit name
When reset
Indeterminate
Function
BBR_9 to BBR_0 Bottom border control bits Bottom border position = TH ✕ n
(n: setting value, TH: HSYNC cycle)
Nothing is assined.
In an attempt to write to this bit, write “0.”
The value, if read, turns out to be indeterminate.
Notes 1 : Do not set BBR ≥ “40016.”
2 : Set as TBR < BBR.
Figure 2.16.47 Bottom border control register
Rev.1.00
May 18, 2004
page 225 of 296
R W
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
Left border control register
(b15)
(b8)
b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0
Symbol
LBR
Bit symbol
Address
027116, 027016
Bit name
When reset
XXXXX000000000012
Function
LBR_10 to LBR_0 Left border control bits
R W
Left border position = 4TOSC ✕ n
(n: setting value, TOSC: OSD oscillation cycle)
Nothing is assined.
In an attempt to write to this bit, write “0.”
The value, if read, turns out to be indeterminate.
Notes 1 : Do not set LBR ≤ “00316,” LBR ≥ “80016.”
2 : Set as LBR < RBR.
Figure 2.16.48 Left border control register
Right border control register
(b15)
(b8)
b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0
Symbol
RBR
Bit symbol
Address
027316, 027216
Bit name
RBR_10 to RBR_0 Right border control bits
Function
Left border position = 4TOSC ✕ n
(n: setting value, TOSC: OSD oscillation cycle)
Nothing is assined.
In an attempt to write to this bit, write “0.”
The value, if read, turns out to be indeterminate.
Notes 1 : Do not set RBR ≥ “80016.”
2 : Set as LBR < RBR.
Figure 2.16.49 Right border control register
Rev.1.00
May 18, 2004
page 226 of 296
When reset
XXXXX000000000002
R W
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
2.16.17 Raster Coloring Function
An entire screen (raster) can be colored by setting the bits 6 to 0 of the raster color register. Since each of
the R, G, B, OUT1, and OUT2 pins can be switched to raster coloring output, 512 raster colors can be
obtained.
When the character color/the character background color overlaps with the raster color, the color (R, G,
B, OUT1, OUT2), specified for the character color/the character background color, takes priority of the
raster color. This ensures that the character color/the character background color is not mixed with the
raster color.
The raster color register is shown in Figure 2.16.50, the example of raster coloring is shown in Figure
2.16.51.
Note: Raster is not output to the area which includes blank area.
Raster color register
(b15)
(b8)
b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0
Symbol
RSC
Bit symbol
Address
020916, 020816
Bit name
RSC2 to RSC0 R singnal output
control bits
Function
b2 b1 b0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0 : VSS
1 : 1/7V
0 : 2/7V
1 : 3/7V
0 : 4/7V
1 : 5/7V
0 : 6/7V
1 : 7/7V
Nothing is assined.
In an attempt to write to this bit, write “0.”
The value, if read, turns out to be “0.”
RSC6 to RSC4 G singnal output
control bits
b6 b5 b4
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0 : VSS
1 : 1/7V
0 : 2/7V
1 : 3/7V
0 : 4/7V
1 : 5/7V
0 : 6/7V
1 : 7/7V
Nothing is assined.
In an attempt to write to this bit, write “0.”
The value, if read, turns out to be “0.”
RSC10 to RSC8 B singnal output
control bits
b2 b1 b0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0 : VSS
1 : 1/7V
0 : 2/7V
1 : 3/7V
0 : 4/7V
1 : 5/7V
0 : 6/7V
1 : 7/7V
Nothing is assined.
In an attempt to write to this bit, write “0.”
The value, if read, turns out to be “0.”
RSC12
OUT1 singnal output
control bit
0: No output
1: Output
RSC13
OUT2 singnal output
control bit
0: No output
1: Output
Nothing is assined.
In an attempt to write to this bit, write “0.”
The value, if read, turns out to be “0.”
Figure 2.16.50 Raster color register
Rev.1.00
May 18, 2004
page 227 of 296
When reset
000016
R W
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
: Character color “RED” (R and OUT1)
: Border color “BLACK” (OUT1)
: Background color “MAGENTA” (R, B and OUT1)
: Raster color “BLUE” (B and OUT1)
A'
A
HSYNC
OUT1
Signals
across
A-A'
R
G
B
<At horizontal blank output>
: Character color “RED” (R and OUT1)
: Border color “BLACK” (OUT1)
: Background color “MAGENTA” (R, B and OUT1)
: Raster color “BLUE” (B and OUT1)
: Horizontal blank (OUT1)
A'
A
HSYNC
OUT1
Signals
across
A-A'
R
G
B
Blank control
signal in
microcomputer
Figure 2.16.51 Example of raster coloring
Rev.1.00
May 18, 2004
page 228 of 296
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
2.16.18 Scan Mode
This microcomputer has the bi-scan mode for corresponding to HSYNC of double speed frequency. In the
bi-scan mode, the vertical start display position and the vertical size is two times as compared with the
normal scan mode. The scan mode is selected by bit 1 of the OSD control register 1 (refer to Figure
2.16.3).
Table 2.16.12 Setting for scan mode
Scan Mode
Parameter
Bit 1 of OSD control register 1
Vertical display start position
Normal Scan
Bi-Scan
0
1
Value of vertical position register ✕ 1H
Value of vertical position register ✕ 2H
1TC ✕ 1/2H
1TC ✕ 1H
1TC ✕ 1H
1TC ✕ 2H
2TC ✕ 2H
2TC ✕ 4H
3TC ✕ 3H
3TC ✕ 6H
Vertical dot size
2.16.19 R, G, B Signal Output Control
The form of R, G, B signal output is controlled by bit 4 of the clock register and bit 2 of the OSD control
register 2 as the table below.
Table 2.16.13 R, G, B signal output control
Bit 4 of clock
Bit 2 of OSD
control register
control register 2
0
0
1
1
0
Rev.1.00
May 18, 2004
page 229 of 296
Form of R, G, B signal output
Each R, G, B pin outputs 2 values (digital output).
Each R, G, B pin outputs 8 values (analog output).
DIGR0 (P92), DIGR1 (R), DIGR2 (P107)
DIGG0 (P87), DIGG1 (G), DIGG2 (P106)
DIGB0 (P86), DIGB1 (B), DIGB2 (P105)
Each of these pins output two-level values.
(Corresponding to each signal output control bit in color palette register i)
DIGR0~2 correspond to CRi0~2, respectively.
DIGG0~2 correspond to CRi4~6, respectively.
DIGB0~2 correspond to CRi8~10, respectively.
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
2.16.20 OSD Reserved Register
OSD reserved register 1
b7
b6
0
0
b5
b4
b3
0 0
b2
b1
0 0
b0
Symbol
Address
When reset
0
OR1
025D16
0016
Bit symbol
Bit name
Description
Reserved bits
Must always be set to “0”
Reserved bit
Must always be set to “0” or “1”
Reserved bits
Must always be set to “0”
R
W
R
W
R
W
Figure 2.16.52 OSD reserved register 1
OSD reserved register i (i=2, 3, 5)
b7
0
b6
b5
0 0
b4
0
b3
0
b2
b1
0 0
b0
0
Symbol
Address
OR2
OR3
OR5
027C16
027B16
020A 16
Bit symbol
When reset
0016
0016
0016
Bit name
Reserved bits
Description
Must always be set to “0”
Figure 2.16.53 OSD reserved register i (i=2, 3, 5)
OSD reserved register 4
b7
b6
0 0
b5
b4
b3
0 0 0
b2
b1
0 0
b0
0
Symbol
Address
When reset
OR4
027A16
XX0000002
Bit symbol
Bit name
Reserved bits
Description
Must always be set to “0”
Figure 2.16.54 OSD reserved register 4
TEST reserved register 0
b7
b6
b5
b4
1 0 1 0
b3
b2
b1
b0
0
0
0 0
Symbol
IDT0
Bit symbol
May 18, 2004
Bit name
When reset
0016
Function
Reserved bits
Must always be set to “0”
Reserved bit
Must always be set to “1”
Reserved bit
Must always be set to “0”
Reserved bit
Must always be set to “1”
Figure 2.16.55 TEST reserved register 0
Rev.1.00
Address
026E16
page 230 of 296
R W
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
2.17 Programmable I/O Ports
There are 76 programmable I/O ports: P0–P5, P60–P63, P67, P7, P82, P83, P86, P87, P90–P94, P102–
P107. Each port can be set independently for input or output using the direction register. A pull-up resistance for each block of 4 ports can be set.
Figures 2.17.1 to 2.17.4 show the programmable I/O ports.
Each pin functions as a programmable I/O port and as the I/O for the built-in peripheral devices.
To use the pins as the inputs for the built-in peripheral devices, set the direction register of each pin to input
mode. When the pins are used as the outputs for the built-in peripheral devices (other than the D-A converter), they function as outputs regardless of the contents of the direction registers. When pins are to be
used as the outputs for the D-A converter, do not set the direction registers to output mode. See the
descriptions of the respective functions for how to set up the built-in peripheral devices.
2.17.1 Direction Registers
Figures 2.17.6 to 2.17.10 show the direction registers.
These registers are used to choose the direction of the programmable I/O ports. Each bit in these registers corresponds one for one to each I/O pin.
(1) Effect of the protection register
Data written to the direction register of P9 is affected by the protection register. The direction register
of P9 cannot be easily written.
2.17.2 Port Registers
Figures 2.17.11 to 2.17.15 show the port registers.
These registers are used to write and read data for input and output to and from an external device. A
port register consists of a port latch to hold output data and a circuit to read the status of a pin. Each bit
in port registers corresponds one for one to each I/O pin.
(1) Reading a port register
With the direction register set to output, reading a port register takes out the content of the port register, not the content of the pin. With the direction register set to input, reading the port register takes out
the content of the pin.
(2) Writing to a port register
With the direction register set to output, the level of the written values from each relevant pin is output
by writing to a port register. Writing to the port register, with the direction register set to input, inputs a
value to the port register, but nothing is output to the relevant pins. The output level remains floating.
Rev.1.00
May 18, 2004
page 231 of 296
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
2.17.3 Pull-up Control Registers
Figures 2.17.17 to 2.17.19 show the pull-up control registers.
The pull-up control register can be set to apply a pull-up resistance to each block of 4 ports. When ports
are set to have a pull-up resistance, the pull-up resistance is connected only when the direction register is
set for input.
However, in memory expansion mode and microprocessor mode, pull-up control register of P0 to P5 is
invalid.
2.17.4 Port Control Register
Figure 2.17.16 shows the port control register.
The bit 0 of port control register is used to read port P1 as follows:
0: When port P1 is input port, port input level is read.
When port P1 is output port, the contents of port P1 register is read.
1: The contents of port P1 register is read through port P1 is input/output port.
When external bus width is 8 bits in microprocessor mode or memory expansion mode, this register is
valid.
Rev.1.00
May 18, 2004
page 232 of 296
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
Pull-up selection
VCCI
Direction register
VCCI
VCCI
P00–P07,
P20–P27,
P30–P37,
P40–P43
Data bus
Port latch
(Note)
Pull-up selection
VCCI
VCCI
Direction register
P10–P14
VCCI
Port P1 control register
Port latch
Data bus
(Note)
Pull-up selection
P15–P17
VCCI
Direction register
VCCI
VCCI
Port P1 control register
Data bus
Port latch
(Note)
Input to respective peripheral functions
Pull-up selection
Direction register
P55,
P62,
P75, P77,
P87,
P90–P92,
VCCI
VCCI
VCCI
Port latch
Data bus
(Note)
Input to respective peripheral functions
Note :
symbolizes a parasitics diode.
Do not apply a voltage higher than VCCI each port.
Figure 2.17.1 Programmable I/O ports (1)
Rev.1.00
May 18, 2004
page 233 of 296
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
Pull-up selection
P82, P83
VCCI
Direction register
VCCI
VCCI
Port latch
Data bus
(Note)
Input to respective pefipheral functions
Pull-up selection
VCCI
Direction register
VCCI
VCCI
P44–P47,
P50–P54,P56,
P63,
P86
“1”
Output
Data bus
Port latch
(Note)
Pull-up selection
Direction register
VCCI
VCCI
VCCI
P57,
P60, P61,
P73, P74, P76
“1”
Output
Port latch
Data bus
(Note)
Input to respective peripheral functions
Direction register
VCCE
P70, P71
“1”
Output
Data bus
Port latch
(Note)
Input to respective peripheral functions
Note:
symbolizes a parasitics diode.
Do not apply a voltage higher than VCCI/VCCE each port.
Figure 2.17.2 Programmable I/O ports (3)
Rev.1.00
May 18, 2004
page 234 of 296
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
Pull-up selection
P102–P107
VCCI
Direction register
VCCI
VCCI
Port latch
Data bus
(Note)
Analog input
SDA3, SCL3 select
Pull-up selection
D-A output enabled
VCCE
Direction register
VCCE
VCCE
P93,P94
“1”
Output
Data bus
Port latch
(Note)
Input to respective peripheral functions
Analog output
D-A output enabled
SCL2, SDA2 select
P67, P72
Pull-up selection
VCCE
VCCE
Direction register
VCCE
“1”
Output
Data bus
Port latch
(Note)
Input to respective peripheral functions
VCCI
R, G, B
VCCI
OUT1, OUT2
VCCI
Internal circuit
Analog RGB control
VCCI
Internal circuit
(Note)
VCCI
(Note)
Note:
Figure 2.17.3 Programmable I/O ports (2)
Rev.1.00
May 18, 2004
page 235 of 296
symbolizes a parasitics diode.
Do not apply a voltage higher than VCCI/VCCE each port.
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
Pull-up selection
VCCI
Direction register
VCCI
VCCI
P87
Data bus
Port latch
(Note)
fc
Rf
Pull-up selection
VCCI
Direction register
P86
"1"
Data bus
Port latch
VCCI
Rd
VCCI
Output
(Note)
Note :
symbolizes a parasitic diode.
Don't apply a voltage higher than VCCI to each port.
Figure 2.17.4 Programmable I/O ports (4)
VCCI
CNVSS
RESET
Signal input
(Note 1)
VCCI
HSYNC
VSYNC
Signal input
(Note 1)
Note :
symbolizes a parasitic diode.
Don't apply a voltage higher than VCCI to each pin.
Figure 2.17.5 I/O pins
Rev.1.00
May 18, 2004
page 236 of 296
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
Port Pi direction register
b7
b6
b5
b4
b3
b2
b1
Symbol
PDi (i = 0 to 7, except 6)
b0
Bit symbol
Address
03E216, 03E316, 03E616, 03E716,
03EA16, 03EB16, 03EF16
Bit name
PDi_0
Port Pi0 direction register
PDi_1
Port Pi1 direction register
PDi_2
Port Pi2 direction register
PDi_3
Port Pi3 direction register
PDi_4
Port Pi4 direction register
PDi_5
Port Pi5 direction register
PDi_6
Port Pi6 direction register
PDi_7
Port Pi7 direction register
Function
When reset
0016
0016
RW
0 : Input mode
(Functions as an input port)
1 : Output mode
(Functions as an output port)
(i = 0 to7, except 6)
Figure 2.17.6 Port Pi direction register (i = 0 to 7, except 6)
Port P6 direction register
b7
b6
b5
b4
b3
1 1 1
b2
b1
b0
Symbol
PD6
Bit symbol
Address
03EE 16
When reset
00 16
Bit name
Function
PD6_0
Port P6 0 direction register
PD6_1
Port P6 1 direction register
PD6_2
Port P6 2 direction register
0 : Input mode
(Functions as an input port)
1 : Output mode
(Functions as an output port)
PD6_3
Port P6 3 direction register
Must always be set to “1”
Reserved bits
PD6_7
Port P6 7 direction register
Figure 2.17.7 Port P6 direction register
Rev.1.00
May 18, 2004
page 237 of 296
0 : Input mode
(Functions as an input port)
1 : Output mode
(Functions as an output port)
RW
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
Port P8 direction register
b7
b6
b5
b4
b3
b2
b1
1
b0
0 0
Symbol
Address
03F2 16
PD8
Bit symbol
When reset
00X00000 2
Bit name
Reserved bits
Function
RW
Must always be set to “0”
PD8_2
Port P8 2 direction register
PD8_3
Port P8 3 direction register
Reserved bit
0 : Input mode
(Functions as an input port)
1 : Output mode
(Functions as an output port)
Must always be set to “1”
Nothing is assigned.
In an attempt to write to this bit, write “0.”
The value, if read, turns out to be indeterminate.
PD8_6
Port P8 6 direction register
PD8_7
Port P8 7 direction register
0 : Input mode
(Functions as an input port)
1 : Output mode
(Functions as an output port)
Figure 2.17.8 Port P8 direction register
Port P9 direction register
b7
b6
b5
b4
b3
1 1 1
b2
b1
b0
Symbol
PD9
Bit symbol
PD9_0
Address
03F3 16
When reset
0016
Bit name
Function
Port P9 0 direction register
PD9_2
0 : Input mode
(Functions as an input port)
Port P9 1 direction register 1 : Output mode
(Functions as an output port)
Port P9 2 direction register
PD9_3
Port P9 3 direction register
PD9_4
Port P9 4 direction register
PD9_1
Reserved bits
RW
Must always be set to “1”
Note: Set bit 2 of protect register (address 000A 16) to “1” before rewriting to
the port P9 direction register.
Figure 2.17.9 Port P9 direction register
Rev.1.00
May 18, 2004
page 238 of 296
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
Port P10 direction register
b7
b6
b5
b4
b3
b2
b1
b0
1 1
Symbol
PD10
Bit symbol
Address
03F6 16
When reset
0016
Bit name
Function
Reserved bits
PD10_2
Must always be set to “1”
PD10_4
Port P102 direction register 0 : Input mode
(Functions as an input port)
Port P103 direction register 1 : Output mode
(Functions as an output port)
Port P104 direction register
PD10_5
Port P105 direction register
PD10_6
Port P106 direction register
PD10_7
Port P107 direction register
PD10_3
Figure 2.17.10 Port P10 direction register
Rev.1.00
May 18, 2004
page 239 of 296
RW
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
Port Pi register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
Pi (i = 0 to 7, except 6)
Bit symbol
Address
03E016, 03E116, 03E416, 03E516,
03E816, 03E916, 03ED16
Bit name
Pi_0
Port Pi0 register
Pi_1
Port Pi1 register
Pi_2
Port Pi2 register
Pi_3
Port Pi3 register
Pi_4
Pi_5
Port Pi4 register
Port Pi5 register
Pi_6
Port Pi6 register
Pi_7
Port Pi7 register
Function
When reset
Indeterminate
Indeterminate
RW
Data is input and output to and from
each pin by reading and writing to
and from each corresponding bit
0 : “L” level data
1 : “H” level data
(i = 0 to 7 except 6)
Note: Since P70 and P71 are N-channel open-drain ports, the data is high-impedance.
Figure 2.17.11 Port Pi register (i = 0 to 7, except 6)
Port P6 register
b7
b6
b5
b4
0
0
0
b3
b2
b1
b0
Symbol
P6
Bit symbol
P6_0
Address
03EC 16
Bit name
Port P6 0 register
P6_1
Port P6 1 register
P6_2
Port P6 2 register
P6_3
Port P6 3 register
Reserved bits
P6_7
Figure 2.17.12 Port P6 register
Rev.1.00
May 18, 2004
page 240 of 296
When reset
Indeterminate
Function
Data is input and output to and from
each pin by reading and writing to
and from each corresponding bit
0 : “L” level data
1 : “H” level data
Must always be set to “0”
Port P6 7 register
Data is input and output to and from
each pin by reading and writing to
and from each corresponding bit
0 : “L” level data
1 : “H” level data
R W
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
Port P8 register
b7
b6
b5
b4
0
0
b3
b2
b1
b0
0
0
Symbol
P8
Bit symbol
Address
03F0 16
Bit name
When reset
Indeterminate
Function
R W
Must always be set to “0”
Reserved bits
P8_2
Port P8 2 register
P8_3
Port P8 3 register
Data is input and output to and from
each pin by reading and writing to
and from each corresponding bit
0 : “L” level data
1 : “H” level data
Must always be set to “0”
Reserved bits
P8_6
Port P8 6 register
P8_7
Port P8 7 register
Data is input and output to and from
each pin by reading and writing to
and from each corresponding bit
0 : “L” level data
1 : “H” level data
Figure 2.17.13 Port P8 register
Port P9 register
b7
b6
b5
0
0
0
b4
b3
b2
b1
b0
Symbol
P9
Bit symbol
Port P9 0 register
P9_1
Port P9 1 register
P9_2
Port P9 2 register
P9_3
Port P9 3 register
P9_4
Port P9 4 register
Figure 2.17.14 Port P9 register 0
May 18, 2004
Bit name
P9_0
Reserved bits
Rev.1.00
Address
03F1 16
page 241 of 296
When reset
Indeterminate
Function
Data is input and output to and from
each pin by reading and writing to
and from each corresponding bit
0 : “L” level data
1 : “H” level data
Must always be set to “0”
R W
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
Port P10 register
b7
b6
b5
b4
b3
b2
b1
b0
0 0
Symbol
P10
Bit symbol
Address
03F4 16
Bit name
Reserved bits
Rev.1.00
May 18, 2004
Port P102 register
PD10_3
Port P103 register
PD10_4
Port P104 register
PD10_5
Port P105 register
PD10_6
Port P106 register
PD10_7
Port P107 register
page 242 of 296
Function
Must always be set to “0”
PD10_2
Figure 2.17.15 Port P10 register
When reset
Indeterminate
0 : Input mode
(Functions as an input port)
1 : Output mode
(Functions as an output port)
RW
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
Port control register
b7
b6
b5
b4
b3
b2
b1
b0
Symbpl
PCR
Address
03FF 16
Bit symbol
PCR0
Bit name
Port P1 control register
When reset
0016
Function
R W
0: When port P1 is input port, port
input level is read. When port P1 is
output port, the contents of port P1
register is read.
1: The contents of port P1 register is
read through port P1 is input/output
port.
Nothing is assigned.
In an attempt to write to this bit, write “0.” The value, if read, turns out to be “0.”
Figure 2.17.16 Port control register
Pull-up control register 0
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
PUR0
Address
03FC 16
Bit symbol
Bit name
PU00
P00 to P0 3 pull-up
PU01
P04 to P0 7 pull-up
PU02
P10 to P1 3 pull-up
PU03
P14 to P1 7 pull-up
PU04
P20 to P2 3 pull-up
PU05
P24 to P2 7 pull-up
PU06
P30 to P3 3 pull-up
PU07
P34 to P3 7 pull-up
Figure 2.17.17 Pull-up control register 0
Rev.1.00
May 18, 2004
page 243 of 296
When reset
0016
Function
The corresponding port is pulled
high with a pull-up resistor
0 : Not pulled high
1 : Pulled high
RW
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
Pull-up control register 1
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
PUR1
Address
03FD 16
Bit symbol
When reset
00 16 (Note 3)
Bit name
PU10
P40 to P4 3 pull-up
PU11
P44 to P4 7 pull-up
PU12
PU13
P50 to P5 3 pull-up
P54 to P5 7 pull-up
PU14
P60 to P6 3 pull-up
PU15
P67 pull-up(Note 2)
PU16
P72 and P7 3 pull-up (Note 1)
Function
R W
The corresponding port is pulled
high with a pull-up resistor
0 : Not pulled high
1 : Pulled high
PU17
P74 to P7 7 pull-up
Notes 1: Since P7 0 and P7 1 are N-channel open drain ports, pull-up is not available for them.
2: Pull-up is not available for P6 7 and P7 2, when they are used as I 2C bus interface ports.
3: When the VCCI level is being impressed to the CNVSS terminal, the reset value of this
register becomes to 0216 (PU11 becomes to “1”).
Figure 2.17.18 Pull-up control register 1
Pull-up control register 2
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
PUR2
Address
03FE 16
Bit symbol
Bit name
PU20
P82 and P8 3 pull-up
PU21
P86 and P8 7 pull-up
PU22
P90 to P9 3 pull-up
PU23
P94 pull-up
PU24
P100 to P103 pull-up
PU25
P104 to P107 pull-up
Nothing is assigned.
In an attempt to write to these bits, write “0.”
The value, if read, turns out to be “0.”
Figure 2.17.19 Pull-up control register 2
Rev.1.00
May 18, 2004
page 244 of 296
When reset
00 16
Function
The corresponding port is pulled
high with a pull-up resistor
0 : Not pulled high
1 : Pulled high
The corresponding port is pulled
high with a pull-up resistor
0 : Not pulled high
1 : Pulled high
R W
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
Table 2.17.1 Example connection of unused pins in single-chip mode
Pin name
Connection
Ports P0 to P10
After setting for input mode, connect every pin to VSS or VCC via a
resistor; or after setting for output mode, leave these pins open.
XOUT (Note)
Open
BYTE
Connect to VSS
CNVSS
Connect via resistor to VSS (pull-down)
Note: With external clock input to XIN pin.
Table 2.17.2 Example connection of unused pins in memory expansion mode and microprocessor
mode
Pin name
Connection
Ports P6 to P10
After setting for input mode, connect every pin to VSS or VCC via a
resistor; or after setting for output mode, leave these pins open.
P45/CS1 to P47/CS3
Sets ports to input mode, sets bits CS1 through CS3 to “0,” and
connects to VCCI via resistors (pull-up).
BHE, ALE, HLDA,
XOUT(Note), BCLK
Open
HOLD, RDY
Connect via resistor to VCCI (pull-up)
CNVSS
Connect via resistor to VSS (pull-down) in the memory expansion mode.
Connect via resistor to VCCI (pull-up) in the microprocessor mode.
Note: With external clock input to XIN pin.
Microcomputer
Microcomputer
Port P0 to P10
(Input mode)
·
·
·
(Input mode)
(Output mode)
XOUT
Port P6 to P10
(Input mode)
·
·
·
(Input mode)
·
·
·
VCCI
Open
(Output mode)
Port P45/CS1
to P47/CS3
Open
VCC
BHE
HLDA
ALE
XOUT
BCLK
HOLD
RDY
BYTE
·
·
·
Open
Open
VCCI
0.47 µF
CNVSS (microprocessor mode)
CNVSS
CNVSS (memory expansion mode)
VSS
VSS
In single-chip mode
Figure 2.17.20 Example connection of unused pins
Rev.1.00
May 18, 2004
page 245 of 296
In memory expansion mode or
in microprocessor mode
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
3. USAGE PRECAUTION
3.1 Timer A (timer mode)
(1) Reading the timer Ai register while a count is in progress allows reading, with arbitrary timing, the
value of the counter. Reading the timer Ai register with the reload timing gets “FFFF16”. Reading
the timer Ai register after setting a value in the timer Ai register with a count halted but before the
counter starts counting gets a proper value.
3.2 Timer A (event counter mode)
(1) Reading the timer Ai register while a count is in progress allows reading, with arbitrary timing, the
value of the counter. Reading the timer Ai register with the reload timing gets “FFFF16” by underflow or “000016” by overflow. Reading the timer Ai register after setting a value in the timer Ai
register with a count halted but before the counter starts counting gets a proper value.
(2) When stop counting in free run type, set timer again.
3.3 Timer A (one-shot timer mode)
(1) Setting the count start flag to “0” while a count is in progress causes as follows:
• The counter stops counting and a content of reload register is reloaded.
• The TAiOUT pin outputs “L” level.
• The interrupt request generated and the timer Ai interrupt request bit goes to “1”.
(2) The timer Ai interrupt request bit goes to “1” if the timer's operation mode is set using any of the
following procedures:
• Selecting one-shot timer mode after reset.
• Changing operation mode from timer mode to one-shot timer mode.
• Changing operation mode from event counter mode to one-shot timer mode.
Therefore, to use timer Ai interrupt (interrupt request bit), set timer Ai interrupt request bit to “0”
after the above listed changes have been made.
3.4 Timer A (pulse width modulation mode)
(1) The timer Ai interrupt request bit becomes “1” if setting operation mode of the timer in compliance
with any of the following procedures:
• Selecting PWM mode after reset.
• Changing operation mode from timer mode to PWM mode.
• Changing operation mode from event counter mode to PWM mode.
Therefore, to use timer Ai interrupt (interrupt request bit), set timer Ai interrupt request bit to “0”
after the above listed changes have been made.
(2) Setting the count start flag to “0” while PWM pulses are being output causes the counter to stop
counting. If the TAiOUT pin is outputting an “H” level in this instance, the output level goes to “L”,
and the timer Ai interrupt request bit goes to “1”. If the TAiOUT pin is outputting an “L” level in this
instance, the level does not change, and the timer Ai interrupt request bit does not becomes “1”.
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M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
3.5 Timer B (timer mode, event counter mode)
(1) Reading the timer Bi register while a count is in progress allows reading , with arbitrary timing, the
value of the counter. Reading the timer Bi register with the reload timing gets “FFFF16”. Reading the
timer Bi register after setting a value in the timer Bi register with a count halted but before the counter
starts counting gets a proper value.
3.6 Timer B (pulse period, pulse width measurement mode)
(1) If changing the measurement mode select bit is set after a count is started, the timer Bi interrupt
request bit goes to “1”.
(2) When the first effective edge is input after a count is started, an indeterminate value is transferred to
the reload register. At this time, timer Bi interrupt request is not generated.
3.7 A-D Converter
(1) Write to each bit (except bit 6) of A-D control register 0, to each bit of A-D control register 1, and to bit
0 of A-D control register 2 when A-D conversion is stopped (before a trigger occurs).
In particular, when the Vref connection bit is changed from “0” to “1”, start A-D conversion after an
elapse of 1 µs or longer.
(2) When changing A-D operation mode, select analog input pin again.
(3) When using A-D converter in the one-shot mode and in the single sweep mode
After confirming the completion of A-D conversion, read the A-D register (the completion of A-D conversion is determined by A-D interrupt request bit).
(4) When using A-D converter in the repeat mode and in the repeat sweep mode
Use the main clock without dividing as the internal clock of CPU.
(5) The A-D conversion in the sweep mode needs the time as follows; (number of sweep pins + 2 pins) ✕
repeat times ✕ A-D conversion time for 1 pin.
(6) When operating OSD or operating data slicer using the HSYNC and VSYNC input, do not use the A-D
sweap mode (single sweap mode, repeat sweap mode 0, and repeat sweap mode 1).
3.8 Stop Mode and Wait Mode
____________
(1) When returning from stop mode by hardware reset, RESET pin must be set to “L” level until main clock
oscillation is stabilized.
(2) When switching to either wait mode or stop mode, instructions occupying four bytes either from the
WAIT instruction or from the instruction that sets the every-clock stop bit to “1“ within the instruction
queue are perfected and then the program stops. So put at least four NOPs in succession either to the
WAIT instruction or to the instruction that sets the every-clock stop bit to “1.”
(3) When operating in low speed or low power consumption mode, do not go to wait mode by setting the
peripheral function clock stop bit (CM02) to 1.
(4) When shift to wait mode and stop mode, set the OSD control bit OC10 of the OSD control register 1 as
“0.”
Rev.1.00
May 18, 2004
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M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
3.9 Interrupts
(1) Reading address 0000016
• When maskable interrupt is occurred, CPU read the interrupt information (the interrupt number
and interrupt request level) in the interrupt sequence.
The interrupt request bit of the certain interrupt written in address 0000016 will then be set to “0”.
Reading address 0000016 by software sets enabled highest priority interrupt source request bit to
“0”.
Though the interrupt is generated, the interrupt routine may not be executed.
Do not read address 0000016 by software.
(2) Setting the stack pointer
• The value of the stack pointer immediately after reset is initialized to 000016. Accepting an
interrupt before setting a value in the stack pointer may become a factor of runaway. Be sure to
set a value in the stack pointer before accepting an interrupt.
(3) External interrupt
_______
_______
• When the polarity of the INT0 and INT1 pins is changed, the interrupt request bit is sometimes set
to “1.” After changing the polarity, set the interrupt request bit to “0.”
(4) Rewrite the interrupt control register
• To rewrite the interrupt control register, do so at a point that does not generate the interrupt
request for that register. If there is possibility of the interrupt request occur, rewrite the interrupt
control register after the interrupt is disabled. The program examples are described as follow:
Example 1:
INT_SWITCH1:
FCLR
I
AND.B #00h, 0055h
NOP
NOP
FSET
I
; Disable interrupts.
; Clear TA0IC int. priority level and int. request bit.
; Four NOP instructions are required when using HOLD function.
; Enable interrupts.
Example 2:
INT_SWITCH2:
FCLR
I
AND.B #00h, 0055h
MOV.W MEM, R0
FSET
I
; Disable interrupts.
; Clear TA0IC int. priority level and int. request bit.
; Dummy read.
; Enable interrupts.
Example 3:
INT_SWITCH3:
PUSHC FLG
FCLR
I
AND.B #00h, 0055h
POPC FLG
; Push Flag register onto stack
; Disable interrupts.
; Clear TA0IC int. priority level and int. request bit.
; Enable interrupts.
The reason why two NOP instructions (four when using the HOLD function) or dummy read are inserted
before FSET I in Examples 1 and 2 is to prevent the interrupt enable flag I from being set before the
interrupt control register is rewritten due to effects of the instruction queue.
• When a instruction to rewrite the interrupt control register is executed but the interrupt is disabled, the
interrupt request bit is not set sometimes even if the interrupt request for that register has been generated. This will depend on the instruction. If this creates problems, use the below instructions to change
the register.
Instructions : AND, OR, BCLR, BSET
Rev.1.00
May 18, 2004
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M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
(5) Notes
When clearing interrupt request bit of interrupt control register, depending on the instruction to be
used, it interrupts and interrupt request bit may not be cleared. Use MOV command, when clear
interrupt request bit, and change interrupt control register. When change interrupt control register in
M16C/60 series and M16C/20 series, interrupt control register be sure to change in the part which
corresponding interrupt request does not generate, and change interrupt control register after changing interruption into a prohibition state.
The example of a program which clears interrupt request bit in M16C/60 series.
Example 1: The case where interrupt control register is rewritten with a immediate value
FCLR
I
; Interrupt is forbidden
MOV.B
#00H,0055H
; Timer A0 interrupt request bit clear
MOV.W MEM,R0
; Dummy read
FSET
I
; Interrupt is permitted
Example 2: The case where only interrupt request bit is cleared
FCLR
I
; Interrupt is forbidden
MOV.B
0055H,R0L
; Timer A0 interrupt control register read-out
AND.B
#0F7H,R0L
; Only timer A0 interruption request bit is clear
MOV.B
R0L,0055H
; Timer A0 interrupt control register writing
MOV.W MEM,R0
; Dummy read
FSET
I
; Interrupt is permitted
There is a dummy read in Example 1 and Example 2 for preventing the set of interrupt permission flag
(I flag) interrupting under the influence of command cue, and performing before the writing of interrupt
control register.
3.10 About Flash memory version and mask ROM
Characteristic value, margin of operation, etc. of versions with built-in Flash memory, and built-in mask
ROM may differ from each other within the limits of an electrical characteristics by manufacture process,
built-in ROM, difference of a layout pattern, etc.
Carry out and check an examination equivalent to the system evaluation examination carried out with the
version with built-in Flash memory at the time of a change for a version with built-in mask ROM.
Rev.1.00
May 18, 2004
page 249 of 296
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
4. ITEMS TO BE SUBMITTED WHEN ORDERING MASKED ROM VERSION
Please submit the following when ordering masked ROM products.
(1) Mask ROM confirmation form
(2) Mark specification sheet
(3) ROM data
Rev.1.00
May 18, 2004
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M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
5. ELECTRICAL CHARACTERISTICS
5.1. Absolute Maximum Ratings
Table 5.1.1 Absolute maximum ratings
Symbol
VccI
VccE
VI1
Parameter
Condition
Internal logic supply voltage
External I/O buffer voltage(P93/P94/P72/P71/P70/P67)
Unit
–0.3 to 4.0
–0.3 to 6.0
V
V
–0.3 to VccI+0.3
V
–0.3 to VccE+0.3
V
Input voltage
P00 to P07, P10 to P17, P20 to P27,
P30 to P37, P40 to P47, P50 to P57,
P60 to P63, P73 to P77, P82, P83,
P86, P87, P90–P92, P102 to P107,
XIN, OSC1, RESET, CNVSS, BYTE, Hsync, Vsync
VI2
P6, P70 , P71, P72,7P93, P94 (Note)
VI3
TVSETB
VO1
Output voltage
–0.3 to 0.3
P00 to P07, P10 to P17, P20 to P27,
P30 to P37, P40 to P47, P50 to P57,
P60 to P63, P73 to P77, P82, P83,
P86, P87, P90 to P92, P102 to P107,
R, G, B, OUT1, OUT2, OSC2, XOUT
VO2
P67, P70, P71, P72, P93, P94
Pd
Topr
Tstg
Power dissipation (In the single chip mode)
Operating ambient temperature
–0.3 to VccI+0.3
Ta=25°C
Storage temperature
Note. When using P93 and P94 as DA pin, VI2 is set to -0.3 to VCCI + 0.3(V).
Rev.1.00
Rated value
May 18, 2004
page 251 of 296
V
V
–0.3 to VccE+0.3
V
415
mW
°C
°C
–20 to 70
–40 to 125
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
5.2 Recommended Operating Conditions
Table 5.2.1 Recommended operating conditions (referenced to VCCI=3.3V±0.15V, VCCE=5.0V±0.25V,
Ta = – 20 oC to 70 oC unless otherwise specified)
Parameter
Symbol
Min
Standard
Typ.
Max.
Unit
VccI
Internal logic supply voltage (Note 3)
3.15
3.30
3.45
V
VccE
External I/O buffer voltage (Note 3) P93, P94, P72, P71, P70, P67
4.75
5.00
5.25
V
Vss
Supply voltage
VIH
HIGH Input voltage P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P63,
P73 to P77, P82, P83, P86, P87, P90 to P92, P102 to P107,
XIN, OSC1, RESET, CNVSS, BYTE, Hsync, Vsync, XCIN
0.8VccI
VccI
V
VIH
HIGH Input voltage P67, P70, P71, P72, P93, P94
0.8VccE
VccE
V
VIH
HIGH Input voltage P00 to P07, P10 to P17 (In the single-chip mode)
0.8VccI
VccI
V
VIH
HIGH Input voltage P00 to P07, P10 to P17 (data input function during memory
expansion and microprocessor modes)
0.5VccI
VccI
V
LOW Input voltage P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P63,
P73 to P77, P82, P83, P86, P87, P90 to P92, P102 to P107,
XIN, OSC1, RESET, CNVSS, BYTE, Hsync, Vsync, XCIN
0
0.2VccI
V
V IL
LOW Input voltage P67, P70, P71, P72, P93, P94
0
0.2VccE
V
V IL
LOW Input voltage P00 to P07, P10 to P17 (In the single-chip mode)
0
0.2VccI
V
V IL
LOW Input voltage P00 to P07, P10 to P17 (data input function during memory
expansion and microprocessor modes)
0
0.16VccI
V
IOH (peak)
High peak output current
P00 to P07, P10 to P17,P20 to P27, P30 to P37, P40 to P47,
P50 to P57,P60 to P63, P67, P72 to P77,P82, P83, P86, P87,
P90 to P94, P102 to P107, R, G, B, OUT1, OUT2
–10.0
mA
P00 to P07, P10 to P17,P20 to P27, P30 to P37, P40 to P47,
P50 to P57,P60 to P63, P67, P72 to P77, P82, P83, P86, P87,
P90 to P94, P102 to P107, R, G, B, OUT1, OUT2
–5.0
mA
P00 to P07, P10 to P17,P20 to P27, P30 to P37, P40 to P47,
P50 to P57,P60 to P63, P67, P70 to P77, P82, P83, P86, P87,
P90 to P94, P102 to P107, R, G, B, OUT1, OUT2
10.0
mA
P00 to P07, P10 to P17,P20 to P27, P30 to P37, P40 to P47,
P50 to P57,P60 to P63, P73 to P77, P82, P83, P86, P87,
P90 to P92, P102 to P107, R, G, B, OUT1, OUT2
5.0
mA
6.0
mA
16.1
MHz
50.0
kHz
V IL
IOH (avg)
High average output current
IOL (peak)
IOL (avg)
0
LOW peak output current
LOW average output current
IOL (avg)
LOW average output current
f (XIN)
Main clock input oscillation frequency (Note 4)
f (XcIN)
Sub-clock oscillation frequency
f OSC
Oscillation frequency (for OSD)
P67, P70 to P72, P93, P94
(Note 5)
32.768
LC oscillating mode
7.9
30.1
Ceramic oscillating mode
14.9
30.1
19.9
40.1
Internal oscillation mode
f CVIN
Input frequency
V
Horizontal sync. signal of 525i video signal
15.262
15.734
MHz
16.206
kHz
Horizontal sync. signal of 525p video signal
VI
Input amplitude video signal
CVIN1, CVIN2
–
31.47
1.5
1.75
–
2.00
V
Notes1: The mean output current is the mean value within 100 ms.
2: The total IOH (peak) must be 80 mA max.
3: Connect 0.1 µF or more capacitor externally between the power source pins VCCI-VSS, VCCI-CNVSS, VCCI-TVSETB, and
VCCE-Vss so as to reduce power source noise.
4: It is necessary to satisfy a timing necessary condition and the switching characteristic (after-mentioned).
5: It is necessary to satisfy fOSC≤f(XIN)✕3.1
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M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
5.3 Electrical Characteristics
Table 5.3.1 Electrical characteristics (referenced to VCCI=3.3V, VCCE=5.0V, VSS = 0 V at Ta = 25 oC,
f(XIN) = 16 MHz unless otherwise specified)
Symbol
VOH
Parameter
Measuring condition
Min.
HIGH output voltage P00 to P07, P10 to P17, P20 to P27, IOH= –5mA
Standard
Typ.
Max.
VCCI -1.5
P30 to P37, P40 to 47, P50 to P57,
P60 to P63, P73 to P77,
P82, P83, P86, P87,
P90 to P92, P102 to P107,
R, G, B, OUT1, OUT2
V
(Note 1)
VOH
HIGH output voltageP67, P72, P93,P94
VOL
LOW output voltage P00 to P07, P10 to P17, P20 to P27, IOL=5mA
VCCE-1.5
(Note 2)
IOH= –5mA
V
P30 to P37, P40 to 47, P50 to P57,
P60 to P63, P73 to P77,
P82, P83, P86, P87,
P90 to P92, P102 to P107,
R, G, B, OUT1, OUT2
VOL
LOW output voltage P67, P70,P71, P72 ,P93 ,P94
VT+-VT-
Hysteresis
Unit
IOL=6mA
HOLD, RDY, TB0IN to TB2IN,
INT0, INT1, CTS0, CTS2,
CLK0, R XD0, HSYNC, VSYNC,
HC0, HC1, XIN
1.5
(Note 3)
V
0.6
(Note 4)
V
0.2
0.6
V
VT+-VT-
Hysteresis
SCL1, SCL2, SCL3, CLK2,
SDA1, SDA 2, SDA 3, RXD2
0.2
0.8
V
VT+-VT-
Hysteresis
1.2
V
HIGH input
current
RESET
P00 to P07, P10 to P17, P20 to P27,
P30 to P37, P40 to 47, P50 to P57, VI=3.3V
P60 to P63, P73 to P77,P82,
P83, P86, P87, P90 to P92,
P102 to P107, XIN, RESET, CNVSS,
BYTE, OSC1, Hsync, Vsync
0.2
IIH
10.0
µA
10.0
µA
–10.0
µA
50.0
167.0
kΩ
OSD (40MHz)ON,
Data slicer ON
90
120
mA
OSD OFF,
Data slicer OFF
40
60
IIH
HIGH input
current
P67, P70, P71,
P72, P93, P94
I IL
LOW input
current
P00 to P07, P10 to P17, P20 to P27,
P30 to P37, P40 to P47, P50 to P57,
VI=0V
P60 to P63, P67, P70 to P77,P82,
P83, P86, P87, P90 to P94,
P102 to P107, XIN, RESET, CNVSS,
BYTE, OSC1, Hsync, Vsync
RPULLUP
VI=5.0V
Pull-up resistor P00 to P07, P10 to P17, P20 to P27,
P30 to P37, P40 to P47, P50 to P57,
VI=0V
P60 to P63, P67, P72 to P77,P82,
P83, P86, P87, P90 to P94,
P102 to P107,
Icc
Power supply current
In single-chip
mode, the
output pins
are open and
other pins are
VSS
30.0
f(XIN) = 16 MHz
Square wave,
no division
f(XIN) = 16 MHz OSD OFF,
mA
15
Square wave, division by 8 Data slicer OFF
f(XCIN) = 32kHz
In the weight
100
400
µA
Ta=25 °C when
clock is stopped
50
200
µA
Ta = 70 °C when
clock is stopped
0.5
2
mA
VCCE=5.0V
Ω
RBS
I2C-BUS • BUS switch connection resistor
(between SCL1 and SCL2, SDA1 and SDA2)
RfXIN
Feedback resistor XIN
3.0
MΩ
RfXCIN
Feedback resistor XCIN
6.0
MΩ
130
Notes1: The minimum value standard for every VOH serves as a straight line which connected (IOH = -5 mA, VOH = VCCI-1.5 V) and (IOH = 0 mA, VOH = VCCI).
2: The minimum value standard for every VOH serves as a straight line which connected (IOH = -5 mA, VOH = VCCE-1.5 V) and (IOH = 0 mA, VOH = VCCE).
3: The maximum value standard for every VOL serves as a straight line which connected (IOH = 5 mA, VOL = 1.5 V) and (IOL = 0 mA, VOL = 0.0 V).
4: The maximum value standard for every VOL serves as a straight line which connected (IOH = 6 mA, VOL = 0.6 V) and (IOL = 0 mA, VOL = 0.0 V).
Rev.1.00
May 18, 2004
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M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
5.4 A-D Conversion Characteristics
Table 5.4.1 A-D conversion characteristics (referenced to VCCI = 3.3V, VSS = 0V at Ta = 25 oC, f(XIN)
= 16 MHz unless otherwise specified)
Standard
Symbol
Parameter
Measuring condition
Unit
Min. Typ. Max.
—
VREF = VCCI
8 Bits
Resolution
Absolute
accuracy
—
tCONV
tSAMP
Sample & hold function not available
VREF = V CCI = 3.3 V
Sample & hold function available (8 bit)
VREF = V CCI = 3.3 V
Conversion time
Sampling time
Reference voltage
Analog input voltage
VREF
VIA
±5
±5
LSB
LSB
µs
µs
2.8
0.3
V
VCCI
0
VCCI
V
5.5 D-A Conversion Characteristics
Table 5.5.1 D-A conversion characteristics (referenced to VCCI=3.3V, VSS = 0V, at Ta = 25 oC, f(XIN)
= 16 MHz unless otherwise specified)
Symbol
—
—
Parameter
Measuring condition
Resolution
Absolute accuracy
Setup time
Output resistance
tsu
RO
Min.
Standard
Typ. Max.
8
10
3
4
10
20
Unit
Bits
%
µs
kΩ
5.6 Analog R, G, B Output Characteristics
Table 5.6.1 Analog R, G, B output characteristics (VCCI = 3.3V, VSS = 0V at Ta = 25 oC, Load register
RI = No, Load capacity CI = No)
Symbol
Parameter
Vppm
Maximum output amplitude
Voe
Io
Output deviation
Ro
Output register
Tst
Settling time
Rev.1.00
Maximum output supply voltage
May 18, 2004
page 254 of 296
Measuring condition
Min.
Standard
Typ. Max.
RGB each output control bit
=111b setting
0.9
1.0
RGB each output control bit
=111b setting
2.2
4.0
190
30 % → 70 % or
70 % → 30 %
1.2
Unit
V
±20
%
5.8
mA
400
Ω
ns
33
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
V 0E
2/7(V)
7 0 %V P -P
V P -P
3 0 %V P-P
1/7(V)
V0E
TST
No t e. 0/ 7 = V ss , 1 / 7 , 2 / 7 i s i n d i c a t e d a s m a x i m u m o u t p u t a m p l i t u d e V ppm = 7 / 7 ( V ) .
Figure 5.6.1 Analog R, G, B output characteristics
Rev.1.00
May 18, 2004
page 255 of 296
VSS
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
5.7 Timing Requirements
Table 5.7.1 External clock input (referenced to VCCI=3.3V, VCCE=5.0V, VSS = 0 V at Ta = 25 oC
unless otherwise specified)
Symbol
tc
Parameter
External clock input cycle time
External clock input HIGH pulse width
External clock input LOW pulse widthJ
External clock rise time
External clock fall timeJ
tw(H)
tw(L)
tr
tf
Standard
Min.
Max.
Unit
62
ns
28
28
ns
ns
15
ns
15
ns
Table 5.7.2 Memory expansion and microprocessor modes (referenced to VCCI=3.3V, VCCE=5.0V,
VSS = 0 V at Ta = 25 oC unless otherwise specified)
Symbol
Parameter
Standard
Min.
Max.
Unit
tac1(RD-DB)
Data input access time (no wait)
(Note)
ns
tac2(RD-DB)
Data input access time (with wait)
(Note)
ns
tsu(DB-RD)
tsu(RDY-BCLK )
Data input setup time
RDY input setup time
HOLD input setup time
Data input hold time
RDY input hold time
HOLD input hold time
HLDA output delay time
tsu(HOLD-BCLK )
th(RD-DB)
th(BCLK -RDY)
th(BCLK-HOLD )
td(BCLK-HLDA )
Note. According to BCLK frequency, it is computed in the following formula.
Rev.1.00
tac1(RD-DB)=JJ
109
- 45 (ns)
f(BCLK)✕2
tac2(RD-DB)=JJ
3✕109
- 45 (ns)
f(BCLK)✕2
May 18, 2004
page 256 of 296
30
ns
ns
40
ns
0
ns
0
0
ns
40
ns
40
ns
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
Table 5.7.3 Timer B input (counter input in event counter mode)
(referenced to VCCI=3.3V, VSS = 0 V at Ta = 25 oC unless otherwise specified)
Symbol
Parameter
Standard
Min.
Max.
Unit
tc(TB)
TBiIN input cycle time (counted on one edge)
100
ns
tw(TBH)
TBiIN input HIGH pulse width (counted on one edge)
40
ns
tw(TBL)
TBiIN input LOW pulse width (counted on one edge)
40
200
ns
ns
tc(TB)
TBiIN input cycle time (counted on both edges)
tw(TBH)
TBiIN input HIGH pulse width (counted on both edges)
80
ns
tw(TBL)
TBiIN input LOW pulse width (counted on both edges)
80
ns
Table 5.7.4 Timer B input (pulse period measurement mode)
(referenced to VCCI=3.3V, VSS = 0 V at Ta = 25 oC unless otherwise specified)
Symbol
Parameter
Standard
Min.
Max.
Unit
tc(TB)
TBiIN input cycle time
400
ns
tw(TBH)
tw(TBL)
TBiIN input HIGH pulse width
TBiIN input LOW pulse width
200
200
ns
ns
Table 5.7.5 Timer B input (pulse width measurement mode)
(referenced to VCCI=3.3V, VSS = 0 V at Ta = 25 oC unless otherwise specified)
Symbol
Parameter
Standard
Min.
Max.
Unit
tc(TB)
TBiIN input cycle time
400
ns
tw(TBH)
TBiIN input HIGH pulse width
200
ns
tw(TBL)
TBiIN input LOW pulse width
200
ns
Table 5.7.6 Serial I/O (referenced to VCCI=3.3V, VCCE=5.0V, VSS = 0 V at Ta = 25 oC unless otherwise specified)
Symbol
Parameter
Standard
Min.
Max.
Unit
tc(CK)
CLKi input cycle time
200
ns
tw(CKH)
CLKi input HIGH pulse width
100
ns
tw(CKL)
CLKi input LOW pulse width
100
ns
td(C-Q)
TxDi output delay time
th(C-Q)
TxDi hold time
tsu(D-C)
RxDi input setup time
RxDi input hold time
th(C-D)
80
ns
0
30
ns
90
ns
ns
_______
Table 5.7.7 External interrupt INTi inputs (referenced to VCCI=3.3V, VSS = 0 V at Ta = 25 oC unless
otherwise specified)
Symbol
Parameter
Standard
Min.
Max.
Unit
tw(INH)
INTi input HIGH pulse width
250
ns
tw(INL)
INTi input LOW pulse width
250
ns
Rev.1.00
May 18, 2004
page 257 of 296
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
5.8 Switching Characteristics
Table 5.8.1 Memory expansion mode and microprocessor mode (no wait) (referenced to
VCCI=3.3V, VCCE=5.0V, VSS = 0 V at Ta = 25 oC, CM15 = “1” unless otherwise specified)
Parameter
Symbol
td(BCLK-AD)
th(BCLK-AD)
th(RD-AD)
th(WR-AD)
td(BCLK-CS)
th(BCLK-CS)
td(BCLK-RD)
th(BCLK-RD)
td(BCLK-WR)
th(BCLK-WR)
td(BCLK-DB)
th(BCLK-DB)
td(DB-WR)
th(WR-DB)
Address output delay time
Address output hold time (BCLK standard)
Address output hold time (RD standard)
Address output hold time (WR standard)
Chip select output delay time
Chip select output hold time (BCLK standard)
RD signal output delay time
RD signal output hold time
WR signal output delay time
WR signal output hold time
Data output delay time (BCLK standard)
Data output hold time (BCLK standard)
Data output delay time (WR standard)
Data output hold time (WR standard)(Note 2)
Measuring condition
Standard
Min.
Max.
35
4
0
0
35
4
35
Figure 5.9.1
0
35
0
40
4
(Note1)
0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes1. According to BCLK frequency, it is computed in the following formula.
td(DB-WR)=
109
- 40 (ns)
f(BCLK)✕2
2. This standard shows the timing which an output turns off and does not show the maintenance time of a data bus.
Rev.1.00
May 18, 2004
page 258 of 296
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
Table 5.8.2 Memory expansion mode and microprocessor mode
(with wait, accessing external memory)
(referenced to VCCI=3.3V, VCCE=5.0V, VSS = 0 V at Ta = 25 oC, CM15 = “1” unless otherwise specified)
td(BCLK-AD)
th(BCLK-AD)
th(RD-AD)
th(WR-AD)
td(BCLK-CS)
th(BCLK-CS)
td(BCLK-RD)
th(BCLK-RD)
td(BCLK-WR)
th(BCLK-WR)
td(BCLK-DB)
th(BCLK-DB)
td(DB-WR)
th(WR-DB)
Measuring condition
Parameter
Symbol
Address output delay time
Address output hold time (BCLK standard)
Address output hold time (RD standard)
Address output hold time (WR standard)
Chip select output delay time
Chip select output hold time (BCLK standard)
RD signal output delay time
RD signal output hold time
WR signal output delay time
WR signal output hold time
Data output delay time (BCLK standard)
Data output hold time (BCLK standard)
Data output delay time (WR standard)
Data output hold time (WR standard)
Standard
Min.
Max.
35
4
0
0
35
4
Figure 5.9.1
35
0
35
0
40
4
(Note1)
0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes1. According to BCLK frequency, it is computed in the following formula.
td(DB-WR)=
109
- 40 (ns)
f(BCLK)✕2
2. This standard shows the timing which an output turns off and does not show the maintenance time of a data bus.
5.9 Measurement Circuit
P0
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
Figure 5.9.1 Port P0 to P10 measurement circuit
Rev.1.00
May 18, 2004
page 259 of 296
10pF
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
5.10 Timing Diagram
tc(TB)
tw(TBH)
TBiIN input
tw(TBL)
tc(CK)
tw(CKH)
CLKi
tw(CKL)
th(C-Q)
TxD i
tsu(D-C)
td(C-Q)
RxDi
tw(INL)
INT i input
tw(INH)
Figure 5.10.1 Timing diagram
Rev.1.00
May 18, 2004
page 260 of 296
th(C-D)
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
Memory Expansion Mode and Microprocessor Mode
(Valid only with wait)
BCLK
RD
RDY input
tsu(RDY-BCLK)
th(BCLK-RDY)
(Valid with or without wait)
BCLK
th(BCLK-HOLD)
tsu(HOLD-BCLK)
HOLD input
HLDA output
td(BCLK-HLDA)
P0, P1, P2,
P3, P4,
P50~P5 2
td(BCLK-HLDA)
Hi-Z
Note: The above pins are set to high-impedance regardless of the input level of the
BYTE pin and bit (PM06) of processor mode register 0 selects the function of ports P40 to P43.
Measuring conditions
• Input timing voltage
• Output timing voltage
VIL /VIH
VOL /VOH
VCCI=3.3 V
VCCE=5.0 V
0.66 V/2.64 V
1.65 V/1.65 V
1.0 V/4.0 V
2.5 V/2.5 V
Figure 5.10.2 Timing diagram in memory expansion mode and microprocessor mode (1)
Rev.1.00
May 18, 2004
page 261 of 296
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
Memory Expansion Mode and Microprocessor Mode
(With no wait)
Read timing
BCLK
td(BCLK–CS)
th(BCLK–CS)
35ns.max
4ns.min
CSi
tcyc
th(RD–CS)
0ns.min
td(BCLK–AD)
th(BCLK–AD)
35ns.max
ADi
4ns.min
BHE
td(BCLK–ALE)
th(BCLK–ALE)
th(RD–AD)
0ns.min
td(BCLK–RD)
35ns.max
RD
th(BCLK–RD)
0ns.min
tac1(RD–DB)
Hi–Z
DB
tSU(DB–RD)
40ns.min
th(RD–DB)
0ns.min
Write timing
BCLK
td(BCLK–CS)
th(BCLK–CS)
35ns.max
4ns.min
CSi
th(WR–CS)
tcyc
0ns.min
td(BCLK–AD)
ADi
th(BCLK-AD)
35ns.max
4ns.min
BHE
td(BCLK–ALE)
th(WR–AD)
0ns.min
td(BCLK–WR)
35ns.max
WR,WRL,
W RH
td(BCLK–DB)
40ns.max
DB
th(BCLK–WR)
0ns.min
th(BCLK–DB)
4ns.min
Hi-Z
td(DB–WR)
(tcyc/2–40)ns.min
th(WR–DB)
0ns.min
Figure 5.10.3 Timing diagram in memory expansion mode and microprocessor mode (2)
Rev.1.00
May 18, 2004
page 262 of 296
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
Memory Expansion Mode and Microprocessor Mode
(When accessing external memory area with wait)
Read timing
BCLK
td(BCLK–CS)
th(BCLK–CS)
35ns.max
4ns.min
CSi
th(RD–CS)
tcyc
0ns.min
td(BCLK–AD)
th(BCLK–AD)
35ns.max
4ns.min
ADi
BHE
th(RD–AD)
0ns.min
td(BCLK–RD)
th(BCLK–RD)
35ns.max
0ns min
RD
tac2(RD–DB)
Hi–Z
DB
th(RD–DB)
tSU(DB–RD)
0ns.min
40ns.min
Write timing
BCLK
td(BCLK–CS)
th(BCLK–CS)
35ns.max
4ns.min
CSi
tcyc
th(WR–CS)
0ns.min
td(BCLK–AD)
th(BCLK–AD)
35ns.max
4ns.min
ADi
BHE
th(WR–AD)
0ns.min
td(BCLK–WR)
WR WRL,
th(BCLK–WR)
35ns.max
0 ns.min
td(BCLK–DB)
th(BCLK–DB)
40ns.max
4ns.min
WRH
DBi
td(DB–WR)
(tcyc–40)ns.min
Measuring conditions
Input timing voltage
Output timing voltage
VIL /VIH
VOL /VOH
th(WR–DB)
0ns.min
VCCI=3.3 V
VCCE=5.0 V
0.52 V/1.65 V
1.65 V
1.0 V/4.0 V
1.65 V
Figure 5.10.4 Timing diagram in memory expansion mode and microprocessor mode (3)
Rev.1.00
May 18, 2004
page 263 of 296
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
6. PACKAGE OUTLINE
100P6S-A
MMP
EIAJ Package Code
QFP100-P-1420-0.65
Plastic 100pin 14✕20mm body QFP
Weight(g)
1.58
Lead Material
Alloy 42
MD
e
JEDEC Code
–
81
1
b2
100
ME
HD
D
80
I2
Recommended Mount Pad
E
30
HE
Symbol
51
50
A
L1
c
A2
31
A
A1
A2
b
c
D
E
e
HD
HE
L
L1
x
y
b
x
y
Rev.1.00
May 18, 2004
page 264 of 296
M
A1
F
e
L
Detail F
b2
I2
MD
ME
Dimension in Millimeters
Min
Nom
Max
3.05
–
–
0.1
0.2
0
2.8
–
–
0.25
0.3
0.4
0.13
0.15
0.2
13.8
14.0
14.2
19.8
20.0
20.2
0.65
–
–
16.5
16.8
17.1
22.5
22.8
23.1
0.4
0.6
0.8
1.4
–
–
–
–
0.13
0.1
–
–
0°
10°
–
0.35
–
–
1.3
–
–
14.6
–
–
20.6
–
–
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
7. Flash Memory
7.1 Description
The M306V7 (flash memory version) contains the DINOR (DIvided bit line NOR) type of flash memory that
can be rewritten with a single voltage of 3.3 V. For this flash memory, three flash memory modes are
available in which to read, program, and erase: parallel I/O and standard serial I/O modes in which the flash
memory can be manipulated using a programmer and a CPU rewrite mode in which the flash memory can
be manipulated by the Central Processing Unit (CPU). Each mode is detailed in the pages to follow.
The flash memory is divided into several blocks as shown in Figure 7.1.1, so that memory can be erased
one block at a time.
In addition to the ordinary user ROM area to store a microcomputer operation control program, the flash
memory has a boot ROM area that is used to store a program to control rewriting in CPU rewrite and
standard serial I/O modes. This boot ROM area has had a standard serial I/O mode control program stored
in it when shipped from the factory. However, the user can write a rewrite control program in this area that
suits the user’s application system. This boot ROM area can be rewritten in only parallel I/O mode.
Table 7.1.1 is a performance outline.
04000016
04FFFF16
05000016
Block4 : 64K bytes
Block3 : 32K bytes
Block2 : 8K bytes
Block1 : 8K bytes
Block0 : 16K bytes
05FFFF16
OSD ROM area
08000016
09000016
0A000016
Block10 : 64K bytes
Block9 : 64K bytes
Block8 : 64K bytes
M306V7FJ/FJA
Flash memory
capacity
Flash memory
start address
USER
512K bytes
08000016
OSD
128K bytes
04000016
M306V7FH
Flash memory
capacity
0B000016
Block7 : 64K bytes
0C000016
Block6 : 64K bytes
0D000016
Block5 : 64K bytes
0E000016
Block4 : 64K bytes
0F000016
Block3 : 32K bytes
Flash memory
start address
USER
384K bytes
0A000016
OSD
128K bytes
04000016
M306V7FG
Flash memory
capacity
Flash memory
start address
0F800016
Block2 : 8K bytes
USER
256K bytes
0C000016
0FA00016
Block1 : 8K bytes
OSD
128K bytes
04000016
0FC00016
0FFFFF16
Block0 : 16K bytes
Figure 7.1.1. Block diagram of flash memory version
May 18, 2004
page 265 of 296
Note 3: The area from address A000016 to address
0BFFFF16 exists in M306V7FH/FJ/FJA.
The area to address 9FFFF16 exists only in M306V7FJ/FJA.
0FC00016
0FFFFF16
user ROM area
Rev.1.00
Note 1: The boot ROM area can be rewritten in
only parallel input/output mode. (Access
to any other areas is inhibited.)
Note 2: To specify a block, use the maximum
address in the block that is an even
address.
16K bytes
Boot ROM area
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
Table 7.1.1. Outline Performance of the M306V7 (flash memory version)
Item
Performance
Power supply voltage
f(XIN)=16MHz, without wait, 3.15V to 3.45V
Program/erase voltage
3.15V to 3.45V : f(BCLK)=6.25MHz, without wait
Flash memory operation mode
Three modes (parallel I/O, standard serial I/O, CPU rewrite)
User ROM area
See Figure 7.1.1
OSD ROM area
See Figure 7.1.1
Boot ROM area
One division (16 Kbytes) (Note 1)
Erase block
division
Program method
In units of pages (in units of 256 bytes)
Erase method
Collective erase/block erase
Program/erase control method
Program / erase control by software command
Number of commands
6 commands
Program/erase count
100 times
Program/erase peripheral
temperature
10°C to 40°C
ROM code protect
Standard serial mode
Note: The boot ROM area contains a standard serial I/O mode control program which is stored in
it when shipped from the factory. This area can be erased and programmed in only parallel
I/O mode.
Rev.1.00
May 18, 2004
page 266 of 296
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
7.2 CPU Rewrite Mode
In CPU rewrite mode, the on-chip flash memory can be operated on (read, program, or erase) under control
of the Central Processing Unit (CPU).
In CPU rewrite mode, only the user ROM area shown in Figure 1.28.1 can be rewritten; the boot ROM area
cannot be rewritten. Make sure the program and block erase commands are issued for only the user ROM
area and each block area.
The control program for CPU rewrite mode can be stored in either user ROM or boot ROM area. In the CPU
rewrite mode, because the flash memory cannot be read from the CPU, the rewrite control program must
be transferred to any area other than the internal flash memory before it can be executed.
7.2.1 Microcomputer Mode and Boot Mode
The control program for CPU rewrite mode must be written into the user ROM or boot ROM area in
parallel I/O mode beforehand. (If the control program is written into the boot ROM area, the standard
serial I/O mode becomes unusable.)
See Figure 1.28.1 for details about the boot ROM area.
Normal microcomputer mode is entered when the microcomputer is reset with pulling CNVSS pin low. In
this case, the CPU starts operating using the control program in the user ROM area.
When the microcomputer is reset by pulling the P55 pin low, the CNVSS pin high, and the P50 pin high, the
CPU starts operating using the control program in the boot ROM area. This mode is called the “boot”
mode. The control program in the boot ROM area can also be used to rewrite the user ROM area.
7.2.2 Block Address
Block addresses refer to the maximum even address of each block. These addresses are used in the
block erase command.
Rev.1.00
May 18, 2004
page 267 of 296
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
7.2.3 Outline Performance (CPU Rewrite Mode)
In the CPU rewrite mode, the CPU erases, programs and reads the internal flash memory as instructed
by software commands. Operations must be executed from a memory other than the internal flash
memory, such as the internal RAM.
When the CPU rewrite mode select bit (bit 1 at address 031316 for USER area/031716 for OSD area) is
set to “1”, transition to CPU rewrite mode occurs and software commands can be accepted.
In the CPU rewrite mode, write to and read from software commands and data into even-numbered
address (“0” for byte address A0) in 16-bit units. Always write 8-bit software commands into even-numbered address. Commands are ignored with odd-numbered addresses.
Use software commands to control program and erase operations. Whether a program or erase operation has terminated normally or in error can be verified by reading the status register.
Figure 7.2.1 shows the flash memory control register and the flash memory switch register.
_____
Bit 0 of the flash memory control register is the RY/BY status flag used exclusively to read the operating
status of the flash memory. During programming and erase operations, it is “0”. Otherwise, it is “1”.
Bit 1 of the flash memory control register is the CPU rewrite mode select bit. The CPU rewrite mode is
entered by setting this bit to “1”, so that software commands become acceptable. In CPU rewrite mode,
the CPU becomes unable to access the internal flash memory directly. Therefore, write bit 1 in an area
other than the internal flash memory. To set this bit to “1”, it is necessary to write “0” and then write “1” in
succession. The bit can be set to “0” by only writing a “0” .
Bit 3 of the flash memory control register is the flash memory reset bit used to reset the control circuit of
the internal flash memory. This bit is used when exiting CPU rewrite mode and when flash memory
access has failed. When the CPU rewrite mode select bit is “1”, writing “1” for this bit resets the control
circuit. To release the reset, it is necessary to set this bit to “0”.
Bit 5 of the flash memory control register is a user ROM area select bit which is effective in only boot
mode. If this bit is set to “1” in boot mode, the area to be accessed is switched from the boot ROM area to
the user ROM area. When the CPU rewrite mode needs to be used in boot mode, set this bit to “1”. Note
that if the microcomputer is booted from the user ROM area, it is always the user ROM area that can be
accessed and this bit has no effect. When in boot mode, the function of this bit is effective regardless of
whether the CPU rewrite mode is on or off. Use the control program except in the internal flash memory
to rewrite this bit.
The bit 1 of flash memory change register is a change bit of USER domain and OSD domain. An access
domain changes according to the contents of a setting of this bit. Access to the domain which is not
chosen cannot be performed including a memory lead. Moreover, after changing this bit before access of
an object domain is attained, the waiting time of 50 clock cycle is required.
Figure 7.2.2 shows a flowchart for setting/releasing the CPU rewrite mode. Always perform operation as
indicated in this flowchart.
Rev.1.00
May 18, 2004
page 268 of 296
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
Flash memory (USER) control register
b7
b6
b5
b4
b3
b2
b1
b0
0
0
Symbol
Address
When reset
FMRU
031316
XX000001 2
Bit name
Bit symbol
Function
FMRU0
RY/BY status flag
0: Busy (being written or erased)
1: Ready
FMRU1
CPU rewrite mode
select bit (Note 1)
0: Normal mode
(Software commands invalid)
1: CPU rewrite mode
(Software commands acceptable)
Must always be set to “0”
Reserved bit
FMRU3
Flash memory reset bit
(Note 2)
Reserved bit
FMRU5
R WW
R
0: Normal operation
1: Reset
Must always be set to “0”
User ROM area select bit
(Note 3) (Effective in only
boot mode)
0: Boot ROM area is accessed
1: User ROM area is accessed
Nothing is assigned.
When write, set "0". When read, values are indeterminate.
Note 1: For this bit to be set to “1”, the user needs to write a “0” and then a “1” to
it in succession. When it is not this procedure, it is not enacted in “1”.
This is necessary to ensure that no interrupt or DMA transfer will be
executed during the interval. Use the control program except in the
internal flash memory for write to this bit.
Note 2: Effective only when the CPU rewrite mode select bit = 1. Set this bit to 0
subsequently after setting it to 1 (reset).
Note 3: Use the control program except in the internal flash memory for write to
this bit.
Flash memory (USER) control register
b7
b6
b5
b4
1
0
b3
b2
b1
b0
0
Symbol
Address
When reset
FMRD
031716
XX000001 2
Bit name
Bit symbol
Function
FMRD0
RY/BY status flag
0: Busy (being written or erased)
1: Ready
FMRD1
CPU rewrite mode
select bit (Note 1)
0: Normal mode
(Software commands invalid)
1: CPU rewrite mode
(Software commands acceptable)
Reserved bit
FMRD3
R W
Must always be set to “0”
Flash memory reset
bit (Note 2)
0: Normal operation
1: Reset
Reserved bit
Must always be set to “0”
Reserved bit
Must always be set to “1”
Nothing is assigned.
When write, set "0". When read, values are indeterminate.
Flash memory (USER/OSD) switch register (note1)
b7
b6
b5
b4
b3
b2
0
0
0
0
0 0
b1
b0
Symbol
Address
When reset
FMSEL
0318 16
X0000000 2
Bit symbol
Bit name
Function
OSELBIT USER/OSD switch
(note 2)
0: Select USER ROM area
1: Select OSD ROM area
Reserved bit
Must always be set to “0”
OSDCONN OSD ROM connection
(note 2)
Reserved bit
Set the same value as OSELBIT
Must always be set to “0”
Nothing is assigned.
When write, set "0". When read, values are indeterminate.
Note 1: Perform the writing to this register in byte size.
(Example : MOV.B #021h, FMSEL)
2: Must always be set to “0” when CPU writing is not performed.
(OSD display operation may be affected)
Figure 7.2.1. Flash memory control register, Flash memory switch register
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M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
Program in ROM
Program in RAM
Start
*1
(Boot mode only)
Set user ROM area select bit to “1”
Single-chip mode, memory expansion
mode, or boot mode
Set processor mode register (Note 1)
Set CPU rewrite mode select bit to “1” (by
writing “0” and then “1” in succession)(Note 2)
Transfer CPU rewrite mode control
program to internal RAM
Jump to transferred control program in RAM
(Subsequent operations are executed by control
program in this RAM)
Using software command execute erase,
program, or other operation
Execute read array command or reset flash
memory by setting flash memory reset bit (by
writing “1” and then “0” in succession) (Note 3)
*1
Write “0” to CPU rewrite mode select bit
(Boot mode only)
Write “0” to user ROM area select bit (Note 4)
End
Note 1: During CPU rewrite mode, set the main clock frequency as 6.25MHz or less using the main clock divide
ratio select bit (bit 6 at address 000616 and bits 6 and 7 at address 000716)
Note 2: For CPU rewrite mode select bit to be set to “1”, the user needs to write a “0” and then a “1” to it in
succession. When it is not this procedure, it is not enacted in “1”. This is necessary to ensure that no
interrupt or DMA transfer will be executed during the interval.
Note 3: Before exiting the CPU rewrite mode after completing erase or program operation, always be sure to
execute a read array command or reset the flash memory.
Note 4: “1” can be set. However, when this bit is “1”, user ROM area is accessed.
Figure 7.2.2. CPU Rewrite Mode Set/Reset Flowchart
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7.2.4 Precautions on CPU Rewrite Mode
Described below are the precautions to be observed when rewriting the flash memory in CPU rewrite
mode.
(1) Operation speed
During CPU rewrite mode, set the main clock frequency 6.25 MHz using the main clock divide ratio
select bit (bit 6 at address 000616 and bits 6 and 7 at address 000716.)
(2) Instructions inhibited against use
The instructions listed below cannot be used during CPU rewrite mode because they refer to the
internal data of the flash memory:
UND instruction, INTO instruction, JMPS instruction, JSRS instruction, and BRK instruction
(3) Interrupts inhibited against use
The address match interrupt cannot be used during CPU rewrite mode because they refer to the
internal data of the flash memory. If interrupts have their vector in the variable vector table, they can be
used by transferring the vector into the RAM area. The watchdog timer interrupts each can be used to
change the flash memory’s operation mode forcibly to read array mode upon occurrence of the interrupt. Since the rewrite operation is halted when the watchdog timer interrupts occur, the erase/program operation needs to be performed over again.
Disabling erase or rewrite operations for address FC00016 to address FFFFF16 in the user ROM block
disables these operations for all subsequent blocks as well. Therefore, it is recommended to rewrite
this block in the standard serial I/O mode.
(4) Reset
Reset input is always accepted. After a reset, the addresses 06000016 through (flash memory start
address-1) are made a reserved area and cannot be accessed. Therefore, if your product has this
area in the user ROM area, do not write any address of this area to the reset vector.
(5) Access disable
Write CPU rewrite mode select bit, user ROM area select bit and USER/OSD change bit in an area
other than the internal flash memory.
(6) How to access
For CPU rewrite mode select bit to be set to “1”, the user needs to write a “0” and then a “1” to it in
succession. When it is not this procedure, it is not enacted in “1”. This is necessary to ensure that no
interrupt or DMA transfer will be executed during the interval.
(7) Change time
When change an access area from USER/OSD change bit's, insert the waiting time about 50 clock
cycle until access of an object area is attained.
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7.2.5 Software Commands
Table 7.2.1 lists the software commands available with the M16C/62 (flash memory version).
After setting the CPU rewrite mode select bit to 1, write a software command to specify an erase or
program operation. Note that when entering a software command, the upper byte (D8 to D15) is ignored.
The content of each software command is explained below.
Table 7.2.1. List of Software Commands (CPU Rewrite Mode)
First bus cycle
Command
Mode
Address
Second bus cycle
Data
(D0 to D 7)
Mode
Address
Read
X
Read array
Write
Read status register
Write
X
7016
Clear status register
Write
X
5016
Page program
Write
X
4116
X
2016
Write
X
A716
Write
(Note 3)
Block erase
Erase all unlock block
X
(Note 5)
Write
Write
Third bus cycle
Data
(D0 to D7)
Mode
Data
Address (D 0 to D7)
FF16
Write
SRD
(Note 2)
WA0 (Note 3) WD0 (Note 3) Write
BA
(Note 4)
D016
X
D016
WA1
WD1
Note 1: When a software command is input, the high-order byte of data (D 8 to D15) is ignored.
Note 2: SRD = Status Register Data
Note 3: WA = Write Address, WD = Write Data
WA and WD must be set sequentially from 00 16 to FE16 (byte address; however, an even address). The page size is
256 bytes.
Note 4: BA = Block Address (Enter the maximum address of each block that is an even address.)
Note 5: X denotes a given address in the user ROM area (that is an even address).
Read Array Command (FF16)
The read array mode is entered by writing the command code “FF16” in the first bus cycle. When an
even address to be read is input in one of the bus cycles that follow, the content of the specified
address is read out at the data bus (D0–D15), 16 bits at a time.
The read array mode is retained intact until another command is written.
Read Status Register Command (7016)
When the command code “7016” is written in the first bus cycle, the content of the status register is
read out at the data bus (D0–D7) by a read in the second bus cycle.
The status register is explained in the next section.
Clear Status Register Command (5016)
This command is used to clear the bits SR3 to 5 of the status register after they have been set. These
bits indicate that operation has ended in an error. To use this command, write the command code
“5016” in the first bus cycle.
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Page Program Command (4116)
Page program allows for high-speed programming in units of 256 bytes. Page program operation
starts when the command code “4116” is written in the first bus cycle. In the second bus cycle through
the 129th bus cycle, the write data is sequentially written 16 bits at a time. At this time, the addresses
A0-A7 need to be incremented by 2 from “0016” to “FE16.” When the system finishes loading the data,
it starts an auto write operation (data program and verify operation).
Whether the auto write operation is completed can be confirmed by reading the status register or the
flash memory control register. At the same time the auto write operation starts, the read status register
mode is automatically entered, so the content of the status register can be read out. The status
register bit 7 (SR7) is set to 0 at the same time the auto write operation starts and is returned to 1 upon
completion of the auto write operation. In this case, the read status register mode remains active until
the Read Array command (FF16) is written or the flash memory is reset using its reset bit.
____
The RY/BY status flag of the flash memory control register 0 is 0 during auto write operation and 1
when the auto write operation is completed as is the status register bit 7.
After the auto write operation is completed, the status register can be read out to know the result of the
auto write operation. For details, refer to the section where the status register is detailed.
Figure 7.2.3 shows an example of a page program flowchart.
And, Additional writes to the already programmed pages are prohibited.
Start
Write 4116
n=0
Write address n and
data n
n = FE16
n=n+2
NO
YES
RY/BY status flag
= 1?
YES
Check full status
Page program
completed
Figure 7.2.3. Page program flowchart
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M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
Block Erase Command (2016/D016)
By writing the command code “2016” in the first bus cycle and the confirmation command code “D016”
in the second bus cycle that follows to the block address of a flash memory block, the system initiates
an auto erase (erase and erase verify) operation.
Whether the auto erase operation is completed can be confirmed by reading the status register or the
flash memory control register. At the same time the auto erase operation starts, the read status
register mode is automatically entered, so the content of the status register can be read out. The
status register bit 7 (SR7) is set to 0 at the same time the auto erase operation starts and is returned
to 1 upon completion of the auto erase operation. In this case, the read status register mode remains
active until the Read Array command (FF16) is written or the flash memory is reset using its reset bit.
____
The RY/BY status flag of the flash memory control register is 0 during auto erase operation and 1
when the auto erase operation is completed as is the status register bit 7.
After the auto erase operation is completed, the status register can be read out to know the result of
the auto erase operation. For details, refer to the section where the status register is detailed.
Figure 7.2.4 shows an example of a block erase flowchart.
Start
Write 2016
Write D016
Block address
RY/BY status flag
= 1?
YES
Check full status check
Block erase
completed
Figure 7.2.4. Block erase flowchart
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M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
Erase All Unlock Blocks Command (A716/D016)
By writing the command code “A716” in the first bus cycle and the confirmation command code “D016”
in the second bus cycle that follows, the system starts erasing blocks successively.
Whether the erase all unlock blocks command is terminated can be confirmed by reading the status
register or the flash memory control register 0, in the same way as for block erase. Also, the status
register can be read out to know the result of the auto erase operation.
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7.2.6 Status Register
The status register indicates the operating status of the flash memory and whether an erase or program
operation has terminated normally or in an error. The content of this register can be read out by only
writing the read status register command (7016). Table 7.2.2 details the status register.
The status register is cleared by writing the Clear Status Register command (5016).
After a reset, the status register is set to “8016.”
Each bit in this register is explained below.
Write state machine (WSM) status (SR7)
After power-on, the write state machine (WSM) status is set to 1.
The write state machine (WSM) status indicates the operating status of the device, as for output on the
____
RY/BY pin. This status bit is set to 0 during auto write or auto erase operation and is set to 1 upon
completion of these operations.
Erase status (SR5)
The erase status informs the operating status of auto erase operation to the CPU. When an erase
error occurs, it is set to 1.
The erase status is reset to 0 when cleared.
Program status (SR4)
The program status informs the operating status of auto write operation to the CPU. When a write
error occurs, it is set to 1.
The program status is reset to 0 when cleared.
When an erase command is in error (which occurs if the command entered after the block erase
command (2016) is not the confirmation command (D016), both the program status and erase status
(SR5) are set to 1.
When the program status or erase status = 1, the following commands entered by command write are
not accepted.
Also, when the valid command is not entered correctly, both SR4 and SR5 are set to 1 (command
sequence error).
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Block status after program (SR3)
If excessive data is written (phenomenon whereby the memory cell becomes depressed which results
in data not being read correctly), “1” is set for the program status after-program at the end of the page
write operation. In other words, when writing ends successfully, “8016” is output; when writing fails,
“9016” is output; and when excessive data is written, “8816” is output.
Table 7.2.2. Definition of each bit in status register
Definition
Each bit of
SRD
Status name
"1"
"0"
Ready
Busy
-
-
SR7 (bit7)
Write state machine (WSM) status
SR6 (bit6)
Reserved
SR5 (bit5)
Erase status
Terminated in error
Terminated normally
SR4 (bit4)
Program status
Terminated in error
Terminated normally
SR3 (bit3)
Block status after program
Terminated in error
Terminated normally
SR2 (bit2)
Reserved
-
-
SR1 (bit1)
Reserved
-
-
SR0 (bit0)
Reserved
-
-
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7.2.7 Full Status Check
By performing full status check, it is possible to know the execution results of erase and program operations. Figure 7.2.5 shows a full status check flowchart and the action to be taken when each error occurs.
Read status register
SR4=1 and SR5
=1 ?
YES
Command
sequence error
Execute the clear status register command (50 16)
to clear the status register. Try performing the
operation one more time after confirming that the
command is entered correctly.
Block erase error
Should a block erase error occur, the block in error
cannot be used.
Page program error
Should a page program error occur, the page in
error cannot be used.
NO
SR5=0?
NO
YES
SR4=0?
NO
YES
SR3=0?
NO
YES
Program error
(block)
After erasing the block in error, execute write
operation one more time. If the same error still
occurs, the block in error cannot be used.
End (block erase, program)
Note: When one of SR5 to SR3 is set to 1, none of the page program, block erase and
erase all unlock blocks commands is accepted. Execute the clear status register
command (50 16) before executing these commands.
Figure 7.2.5. Full status check flow chart and the solution at the time of each error generating
7.2.8 Built-in flash memory rewriting prohibition function
For standard serial I/O mode, the ID code check function is built-in so that the contents of a built-in flash
memory cannot be rewritten easily.
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7.3 Parallel I/O Mode
In this mode, the M306V7 (flash memory version) operates in a manner similar to the flash memory
M5M29FB/T800 from Mitsubishi. Since there are some differences with regard to the functions not available with the microcomputer and matters related to memory capacity, the M16C/62 cannot be programed
by a programer for the flash memory.
Use an exclusive programer supporting M306V7 (flash memory version).
Refer to the instruction manual of each programer maker for the details of use.
7.3.1 User ROM and Boot ROM Areas
In parallel I/O mode, the user ROM and boot ROM areas shown in Figure 7.1.1 can be rewritten. Both
areas of flash memory can be operated on in the same way.
Program and block erase operations can be performed in the user ROM area. The user ROM area and its
blocks are shown in Figure 7.1.1.
The boot ROM area is 16 Kbytes in size. In parallel I/O mode, it is located at addresses 0FC00016 through
0FFFFF16. Make sure program and block erase operations are always performed within this address
range. (Access to any location outside this address range is prohibited.)
In the boot ROM area, an erase block operation is applied to only one 16 Kbyte block. The boot ROM area
has had a standard serial I/O mode control program stored in it when shipped from the Mitsubishi factory.
Therefore, using the device in standard serial input/output mode, you do not need to write to the boot
ROM area.
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7.4 Standard Serial I/O Mode
Pin functions (Flash memory standard serial I/O mode)
Name
Pin
Description
I/O
VCCI,VSS
Power input
CNV SS
CNV SS
I
Connect to VCCI pin.
RESET
Reset input
I
Reset input pin. While reset is "L" level, a 20 cycle or longer clock
must be input to XIN pin.
XIN
Clock input
I
XOUT
Clock output
O
Connect a ceramic resonator or crystal oscillator between XIN and
XOUT pins. To input an externally generated clock, input it to XIN pin
and open X OUT pin.
BYTE
BYTE
I
Connect this pin to VCCI or Vss.
VCCE
Analog power supply input
TVSETB
Set input
I
Connect a VSS.
P00 to P0 7
Input port P0
I
Input "H" or "L" level signal or open.
P10 to P1 7
Input port P1
I
Input "H" or "L" level signal or open.
P20 to P2 7
Input port P2
I
Input "H" or "L" level signal or open.
P30 to P3 7
Input port P3
I
Input "H" or "L" level signal or open.
P40 to P4 7
Input port P4
I
Input "H" or "L" level signal or open.
P51 to P5 4,
P56, P57
Input port P5
I
Input "H" or "L" level signal or open.
P50
CE input
I
Input "H" level signal.
P55
EPM input
I
Input "L" level signal.
P64 to P6 7
Input port P6
I
Input "H" or "L" level signal or open.
P60
BUSY output
O
BUSY signal output pin
P61
SCLK input
I
Serial clock input pin
P62
RxD input
I
Serial data input pin
P63
TxD output
O
Serial data output pin
P70 to P7 7
Input port P7
I
Input "H" or "L" level signal or open.
P82, P83, P86,
P87
Input port P8
I
Input "H" or "L" level signal or open.
P90 to P9 4
Input port P9
I
Input "H" or "L" level signal or open.
P102–P107
Input port P10
I
Input "H" or "L" level signal or open.
HLF, VHOLD, CVIN
I
Input "H" or "L" level signal or open.
HLF2, VHOLD2, CVIN2
I
Input "H" or "L" level signal or open.
VSYNC, HSYNC
I
Input "H" or "L" level signal or open.
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Apply program/erase protection voltage to VCCI pin and 0 V to Vss pin.
Apply protection voltage to VCCE.
P43 /A 19
P42 /A 18
P41 /A 17
P40 /A 16
P37 /A 15
P36 /A 14
P35 /A 13
P34 /A 12
P33 /A 11
P32 /A 10
P31 /A 9
HSYNC
P30 /A 8
VSYNC
P27 /A 7
P26 /A 6
P25 /A 5
P24 /A 4
P23 /A 3
P22 /A 2
P21 /A 1
P20 /A 0
P17 /D 15
P16 /D 14
P15 /D 13
P14 /D 12
P13 /D 11
P12 /D 10
P11/D9
P10/D8
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
Mode setup method
Signal
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
CNVss
VCCE
P07 /D 7
81
50
P44 /CS 0
EPM
P06 /D 6
82
49
P45 /CS 1
RESET
P05 /D 5
83
48
P46 /CS 2
CE
P04 /D 4
84
47
P47 /CS 3
P03 /D 3
85
46
P50 /WRL/WR
P02 /D 2
86
45
P51 /WRH/BHE
P01 /D 1
87
44
P52 /RD
P00 /D 0
88
43
P53 /BCLK
P10 7 /AN 5 /DIGR2
89
42
P54 /HLDA
P10 6 /AN 4 /DIGG2
90
41
P55 /HOLD
P10 5 /AN 3 /DIGB2
91
40
P56 /ALE
M306V7FG/FH/FJ/FJAFP
P10 4 /AN
2
92
39
P57 /RDY/CLK OUT
P10 3 /AN
1
P10 2 /AN
CE
EPM
93
38
P60 /CTS 0 /RTS 0
BUSY
0
94
37
P61 /CLK 0
SCLK
VHOLD2
95
36
P62 /RxD 0
RxD
HLF2
96
35
P63 /TxD 0
TxD
CVIN2
TVSETB
97
34
98
33
B/DIGB1
G/DIGG1
99
32
R/DIGR1
100
31
P67 /SDA2*
VCCE (5V)
CVIN
Figure 7.4.1. Pin connections for serial I/O mode (1)
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*P70 /SDA 1 ,TxD 2
*P71 /SCL 1 ,RxD2
*P72 /SCL 2 ,CLK2
OUT
P74 /TA2
P73 /CTS 2 ,RTS2
OUT
Connect oscillator circuit.
P75 /HC0
P76 /TA3
P77 /HC1
OUT2
OUT1
P82 /INT 0
P83 /INT 1
OSC2
OSC1/OSCHLF
VCCI (3.3V)
XIN
VSS
XOUT
P86 /XCOUT/DIGB0
RESET
RESET
is the VCCE voltage correspondence.
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
CNVSS
6
P87 /XCIN/DIGG0
P92 /TB2
IN
*P93 /DA0/SDA3/TXD2D
BYTE
HLF
8
P90 /TB0
VHOLD
7
IN
5
P91 /TB1
4
IN/ DIGR0
3
CNVss
Note) The pin with
2
*P94 /DA1/SCL3 /RXD2D
Vss
1
Vcc(3.3V)
Value
VCCI
Vss
Vss
VCCI
VCCI
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
7.4.1 Standard Serial I/O Mode
The standard serial I/O mode serially inputs and outputs the software commands, addresses and data
necessary for operating (read, program, erase, etc.) the internal flash memory. It uses a purpose-specific
peripheral unit.
The standard serial I/O mode differs from the parallel I/O mode in that the CPU controls operations like
rewriting (uses the CPU rewrite mode) in the flash memory or serial input for rewriting data. The standard
_____
serial I/O mode is started by clearing the reset with an “H” level signal at the P50 (CE) pin, an “L” signal at
________
the P55 (EPM) pin and an “H” level at the CNVss pin. (For the normal microprocessor mode, set CNVss
to “L”.)
This control program is written in the boot ROM area when shipped from Mitsubishi Electric. Therefore, if
the boot ROM area is rewritten in the parallel I/O mode, the standard serial I/O mode cannot be used.
Figures 7.4.1 shows the pin connections for the standard serial I/O mode. Serial data I/O uses four
UART1 pins: CLK0, RxD0, TxD0 and RTS0 (BUSY).
The CLK0 pin is the transfer clock input pin and it inputs the external transfer clock. The TxD0 pin outputs
the CMOS signal. The RTS0 (BUSY) pin outputs an “L” level when reception setup ends and an “H” level
when the reception operation starts. Transmission and reception data is transferred serially in 8-byte
blocks.
In the standard serial I/O mode, only the user ROM area shown in Figure 7.1.1 can be rewritten, the boot
ROM area cannot.
Function Overview (Standard Serial I/O Mode)
In the standard serial I/O mode, software commands, addresses and data are input and output between
the flash memory and an external device (peripheral unit, etc.) using a 4-wire clock synchronized serial I/
O (UART0). In reception, the software commands, addresses and program data are synchronized with
the rise of the transfer clock input to the CLK0 pin and input into the flash memory via the RxD0 pin.
In transmission, the read data and status are synchronized with the fall of the transfer clock and output to
the outside from the TxD0 pin.
The TxD0 pin is CMOS output. Transmission is in 8-bit blocks and LSB first.
When busy, either during transmission or reception, or while executing an erase operation or program,
the RTS0 (BUSY) pin is “H” level. Accordingly, do not start the next transmission until the RTS0 (BUSY)
pin is “L” level.
Also, data in memory and the status register can be read after inputting a software command. It is possible to check flash memory operating status or whether a program or erase operation ended successfully
or in error by reading the status register.
Software commands and the status register are explained here following.
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Software Commands
Table 7.4.1 lists software commands. In the standard serial I/O mode, erase operations, programs and
reading are controlled by transferring software commands via the RxD pin. Software commands are
explained here below.
Table 7.4.1. Software commands (Standard serial I/O mode)
Control command
Transmission
of the 1st byte
2rd byte 3rd byte 4rd byte
5rd byte 6rd byte
........
When ID is
not verificate
1
Page read
FF16
Address
(middle)
Address
(high)
Data output Data output
Data output
Data output to
259th byte
Not acceptable
2
Page program
4116
Address
(middle)
Address
(high)
Data input
Data input
Data output to
259th byte
Not acceptable
3
Block erase
2016
Address
(middle)
Address
(high)
D016
A716
D016
4 Erase all unlocked blocks
Not acceptable
Not acceptable
5
Read status register
7016
6
Clear status register
5016
7
ID check function
F5 16
Address
(high)
Address
(middle)
Address
(low)
8
Download function
FA 16
Size
(low)
Size
(high)
Check
-sum
9 Version data output function
FB16
10 Boot area output function
FC16
User ROM area selection
11 function
OSD ROM area selection
12 function
Data input
SRDoutput SRD1output
Not acceptable
ID size
ID1
To required
number of times
Version data Version data Version data Version data Version data
output
output
output
output
output
Address
(middle)
Address
(high)
Data output Data output
to ID7
Data output
Not acceptable
Version data output to
9th byte
Acceptable
Data output to 259th byte
Not acceptable
E0 16
Acceptable
E1 16
Acceptable
Notes1: Shading indicates transfer from flash memory microcomputer to peripheral unit.
All other data is transferred from the peripheral unit to the flash memory microcomputer.
2: SRD refers to status register data. SRD1 refers to status register 1 data.
3: All commands can be accepted when the flash memory is totally blank.
4: All commands can be accepted when the flash memory is totally blank.
* In page lead, page program, and block erase, a domain is automatically changed before
command execution.
* With all erase unlocks, only the domain chosen serves as a candidate for execution.
* After boot ROM domain output execution is ended where USER ROM domain is chosen.
Rev.1.00
May 18, 2004
Acceptable
page 283 of 296
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
Page Read Command
This command reads the specified page (256 bytes) in the flash memory sequentially one byte at a
time. Execute the page read command as explained here following.
(1) Send the “FF16” command code in the 1st byte of the transmission.
(2) Send addresses A8 to A15 and A16 to A23 in the 2nd and 3rd bytes of the transmission respectively.
(3) From the 4th byte onward, data (D0–D7) for the page (256 bytes) specified with addresses A8 to
A23 will be output sequentially from the smallest address first in sync with the rise of the clock.
CLK0
RxD0
(M16C reception data)
FF16
A8 to
A15
A16 to
A23
TxD0
(M16C transmit data)
data0
data255
RTS0(BUSY)
Figure 7.4.2. Timing for page read
Read Status Register Command
This command reads status information. When the “7016” command code is sent in the 1st byte of the
transmission, the contents of the status register (SRD) specified in the 2nd byte of the transmission
and the contents of status register 1 (SRD1) specified in the 3rd byte of the transmission are read.
CLK0
RxD0
(M16C reception data)
7016
TxD0
(M16C transmit data)
RTS0(BUSY)
Figure 7.4.3. Timing for reading the status register
Rev.1.00
May 18, 2004
page 284 of 296
SRD
output
SRD1
output
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
Clear Status Register Command
This command clears the bits (SR3–SR5) which are set when the status register operation ends in
error. When the “5016” command code is sent in the 1st byte of the transmission, the aforementioned
bits are cleared. When the clear status register operation ends, the RTS0 (BUSY) signal changes
from the “H” to the “L” level.
CLK0
RxD0
(M16C reception data)
50 16
TxD0
(M16C transmit data)
RTS0(BUSY)
Figure 7.4.4. Timing for clearing the status register
Page Program Command
This command writes the specified page (256 bytes) in the flash memory sequentially one byte at a
time. Execute the page program command as explained here following.
(1) Send the “4116” command code in the 1st byte of the transmission.
(2) Send addresses A8 to A15 and A16 to A23 in the 2nd and 3rd bytes of the transmission respectively.
(3) From the 4th byte onward, as write data (D0–D7) for the page (256 bytes) specified with addresses
A8 to A23 is input sequentially from the smallest address first, that page is automatically written.
When reception setup for the next 256 bytes ends, the RTS0 (BUSY) signal changes from the “H” to
the “L” level. The result of the page program can be known by reading the status register. For more
information, see the section on the status register.
Each block can be write-protected with the lock bit. For more information, see the section on the data
protection function. Additional writing is not allowed with already programmed pages.
CLK0
RxD0
(M16C reception data)
4116
TxD0
(M16C transmit data)
RTS0(BUSY)
Figure 7.4.5. Timing for the page program
Rev.1.00
May 18, 2004
page 285 of 296
A8 to
A15
A16 to
A23
data0
data255
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
Block Erase Command
This command erases the data in the specified block. Execute the block erase command as explained
here following.
(1) Send the “2016” command code in the 1st byte of the transmission.
(2) Send addresses A8 to A15 and A16 to A23 in the 2nd and 3rd bytes of the transmission respectively.
(3) Send the verify command code “D016” in the 4th byte of the transmission. With the verify command code, the erase operation will start for the specified block in the flash memory. Write the
highest address of the specified block for addresses A16 to A23.
When block erasing ends, the RTS0 (BUSY) signal changes from the “H” to the “L” level. After block
erase ends, the result of the block erase operation can be known by reading the status register. For
more information, see the section on the status register.
Each block can be erase-protected with the lock bit. For more information, see the section on the data
protection function.
CLK0
RxD0
(M16C reception data)
2016
TxD0
(M16C transmit data)
RTS0(BUSY)
Figure 7.4.6. Timing for block erasing
Rev.1.00
May 18, 2004
page 286 of 296
A8 to
A15
A16 to
A23
D016
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
Erase All Unlocked Blocks Command
This command erases the content of all blocks. Execute the erase all unlocked blocks command as
explained here following.
(1) Send the “A716” command code in the 1st byte of the transmission.
(2) Send the verify command code “D016” in the 2nd byte of the transmission. With the verify command code, the erase operation will start and continue for all blocks in the flash memory.
When block erasing ends, the RTS0 (BUSY) signal changes from the “H” to the “L” level. The result of the
erase operation can be known by reading the status register. Each block can be erase-protected with the
lock bit. For more information, see the section on the data protection function.
CLK0
RxD0
(M16C reception data)
A716
D016
TxD0
(M16C transmit data)
RTS0(BUSY)
Figure 7.4.7. Timing for erasing all unlocked blocks
ROM area selection function
This is a command for switching of USER ROM area and OSD ROM area. If command code "E0" or
"E1" is transmitted at the 1st byte transmission, USER ROM area or OSD ROM area is chosen.
When end change operation, RTS0 (BUSY) signal changes from "H" to "L."
In addition, the area under selection can be known by reading a status register. Refer to the paragraph
of a status register for details.
CLK0
RxD0
(M16C reception data)
TxD0
(M16C transmit data)
RTS0(BUSY)
Figure 7.4.8. Timing for download
Rev.1.00
May 18, 2004
page 287 of 296
E016/E116
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
Download Command
This command downloads a program to the RAM for execution. Execute the download command as
explained here following.
(1) Send the “FA16” command code in the 1st byte of the transmission.
(2) Send the program size in the 2nd and 3rd bytes of the transmission.
(3) Send the check sum in the 4th byte of the transmission. The check sum is added to all data sent
in the 5th byte onward.
(4) The program to execute is sent in the 5th byte onward.
When all data has been transmitted, if the check sum matches, the downloaded program is executed.
The size of the program will vary according to the internal RAM.
Rev.1.00
May 18, 2004
page 288 of 296
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
Version Information Output Command
This command outputs the version information of the control program stored in the boot area. Execute
the version information output command as explained here following.
(1) Send the “FB16” command code in the 1st byte of the transmission.
(2) The version information will be output from the 2nd byte onward. This data is composed of 8
ASCII code characters.
CLK0
RxD0
(M16C reception data)
Check
sum
FA 16
Program
data
Program
data
Data size (low)
TxD0
(M16C transmit data)
Data size (high)
RTS0(BUSY)
Figure 7.4.9. Timing for version information output
Boot Area Output Command
This command outputs the control program stored in the boot area in one page blocks (256 bytes).
Execute the boot area output command as explained here following.
(1) Send the “FC16” command code in the 1st byte of the transmission.
(2) Send addresses A8 to A15 and A16 to A23 in the 2nd and 3rd bytes of the transmission respectively.
(3) From the 4th byte onward, data (D0–D7) for the page (256 bytes) specified with addresses A8 to
A23 will be output sequentially from the smallest address first, in sync with the rise of the clock.
CLK0
RxD0
(M16C reception data)
FB16
TxD0
(M16C transmit data)
RTS0(BUSY)
Figure 7.4.10. Timing for boot area output
Rev.1.00
May 18, 2004
page 289 of 296
'6'
'V'
'7'
'X'
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
ID Check
This command checks the ID code. Execute the boot ID check command as explained here following.
(1) Send the “F516” command code in the 1st byte of the transmission.
(2) Send addresses A0 to A7, A8 to A15 and A16 to A23 of the 1st byte of the ID code in the 2nd, 3rd
and 4th bytes of the transmission respectively.
(3) Send the number of data sets of the ID code in the 5th byte.
(4) The ID code is sent in the 6th byte onward, starting with the 1st byte of the code.
CLK0
RxD0
(M16C reception data)
A8 to
A15
FC16
A16 to
A23
TxD0
(M16C transmit data)
data0
data255
RTS0(BUSY)
Figure 7.4.11. Timing for the ID check
ID Code
When the flash memory is not blank, the ID code sent from the peripheral unit and the ID code written
in the flash memory are compared to see if they match. If the codes do not match, the command sent
from the peripheral unit is not accepted. An ID code contains 8 bits of data. Area is, from the 1st byte,
addresses 0FFFDF16, 0FFFE316, 0FFFEB16, 0FFFEF16, 0FFFF316, 0FFFF716 and 0FFFFB16. Write
a program into the flash memory, which already has the ID code set for these addresses.
CLK0
RxD0
(M16C reception
data)
F516
DF16
FF16
TxD0
(M16C transmit
data)
RTS0(BUSY)
Figure 7.4.12. ID code storage addresses
Rev.1.00
May 18, 2004
page 290 of 296
0F16
ID size
ID1
ID7
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
Status Register (SRD)
The status register indicates operating status of the flash memory and status such as whether an erase
operation or a program ended successfully or in error. It can be read by writing the read status register
command (7016). Also, the status register is cleared by writing the clear status register command (5016).
Table 7.4.2 gives the definition of each status register bit. After clearing the reset, the status register
outputs “8016”.
Table 7.4.2. Status register (SRD)
SRD0 bits
Status name
SR7 (bit7)
Write state machine (WSM) status
SR6 (bit6)
Reserved
SR5 (bit5)
Definition
"1"
"0"
Ready
Busy
-
-
Erase status
Terminated in error
Terminated normally
SR4 (bit4)
Program status
Terminated in error
Terminated normally
SR3 (bit3)
Block status after program
Terminated in error
Terminated normally
SR2 (bit2)
Reserved
-
-
SR1 (bit1)
Reserved
-
-
SR0 (bit0)
Reserved
-
-
Write State Machine (WSM) Status (SR7)
The write state machine (WSM) status indicates the operating status of the flash memory. When
power is turned on, “1” (ready) is set for it. The bit is set to “0” (busy) during an auto write or auto erase
operation, but it is set back to “1” when the operation ends.
Erase Status (SR5)
The erase status reports the operating status of the auto erase operation. If an erase error occurs, it is
set to “1”. When the erase status is cleared, it is set to “0”.
Program Status (SR4)
The program status reports the operating status of the auto write operation. If a write error occurs, it is
set to “1”. When the program status is cleared, it is set to “0”.
Rev.1.00
May 18, 2004
page 291 of 296
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
Block Status After Program (SR3)
If excessive data is written (phenomenon whereby the memory cell becomes depressed which results
in data not being read correctly), “1” is set for the program status after-program at the end of the page
write operation. In other words, when writing ends successfully, “8016” is output; when writing fails,
“9016” is output; and when excessive data is written, “8816” is output.
If “1” is written for any of the SR5, SR4 or SR3 bits, the page program, block erase, erase all unlocked
blocks and lock bit program commands are not accepted. Before executing these commands, execute
the clear status register command (5016) and clear the status register.
Rev.1.00
May 18, 2004
page 292 of 296
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
Status Register 1 (SRD1)
Status register 1 indicates the status of serial communications, results from ID checks and results from
check sum comparisons. It can be read after the SRD by writing the read status register command (7016).
Also, status register 1 is cleared by writing the clear status register command (5016).
Table 7.4.3 gives the definition of each status register 1 bit. “0016” is output when power is turned ON and
the flag status is maintained even after the reset.
Table 7.4.3. Status register 1 (SRD1)
Definition
SRD1 bits
Status name
SR15 (bit7)
Boot update completed bit
Update completed
Not update
SR14 (bit6)
Reserved
-
-
SR13 (bit5)
Reserved
-
-
SR12 (bit4)
Check sum match bit
Mismatch
SR11 (bit3)
ID check completed bits
Match
00
01
10
11
SR10 (bit2)
SR9 (bit1)
Data receive time out
SR8 (bit0)
Selection area
"1"
Time out
OSD ROM
"0"
Not verified
Verification mismatch
Reserved
Verified
Normal operation
USER ROM
Boot Update Completed Bit (SR15)
This flag indicates whether the control program was downloaded to the RAM or not, using the download function.
Check Sum Consistency Bit (SR12)
This flag indicates whether the check sum matches or not when a program, is downloaded for execution using the download function.
ID Check Completed Bits (SR11 and SR10)
These flags indicate the result of ID checks. Some commands cannot be accepted without an ID
check.
Data Reception Time Out (SR9)
This flag indicates when a time out error is generated during data reception. If this flag is attached
during data reception, the received data is discarded and the microcomputer returns to the command
wait state.
Selection area (SR8)
It is the flag which shows ROM area under present selection.
Rev.1.00
May 18, 2004
page 293 of 296
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
Full Status Check
Results from executed erase and program operations can be known by running a full status check. Figure
7.4.13 shows a flowchart of the full status check and explains how to remedy errors which occur.
Address
0FFFDC16 to 0FFFDF16
ID1 Undefined instruction vector
0FFFE016 to 0FFFE316
ID2 Overflow vector
0FFFE416 to 0FFFE716
BRK instruction vector
0FFFE816 to 0FFFEB16
ID3 Address match vector
0FFFEC16 to 0FFFEF16
ID4 Single step vector
0FFFF016 to 0FFFF316
ID5 Watchdog timer vector
0FFFF416 to 0FFFF716
ID6 DBC vector
0FFFF816 to 0FFFFB16
ID7 Reserved factor
0FFFFC16 to 0FFFFF16
Reset vector
4 bytes
Figure 7.4.13. Full status check flowchart and remedial procedure for errors
Rev.1.00
May 18, 2004
page 294 of 296
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
Example Circuit Application for The Standard Serial I/O Mode
The below figure shows a circuit application for the standard serial I/O mode. Control pins will vary according to peripheral unit (programmer), therefore see the peripheral unit (programmer) manual for more
information.
Read status register
SR4=1 and SR5
=1 ?
YES
Command
sequence error
Execute the clear status register command (50 16)
to clear the status register. Try performing the
operation one more time after confirming that the
command is entered correctly.
Block erase error
Should a block erase error occur, the block in error
cannot be used.
Page Program error
Should a page program error occur, the page in
error cannot be used.
NO
NO
SR5=0?
YES
NO
SR4=0?
YES
NO
SR3=0?
Program error
(block)
YES
After erasing the block in error, execute write
operation one more time. If the same error still
occurs, the block in error cannot be used.
End (block erase, program)
Note: When one of SR5 to SR3 is set to 1, none of the page program, block erase and
erase all unlock blocks commands is accepted. Execute the clear status register
command (50 16) before executing these commands.
Figure 7.4.14. Example circuit application for the standard serial I/O mode
Rev.1.00
May 18, 2004
page 295 of 296
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
Structure of Register
Refer to the figure below as for each register.
<Example>
Processor mode register 1 (Note)
Values immediately
after reset release
(Note 1)
(Note 2)
b7
b6
b5
0 0
b4
b3
0 0
b2
b1
b0
1
0
Symbol
PM1
Address
000516
Bit symbol
Bit name
When reset
00000X002
Bit attributes
Function
Reserved bit
Must always be set to “0”
Reserved bit
Must always be set to “1”
Nothing is assigned.
In an attempt to write to this bit, write “0.” The value, if read, turns out to be
indeterminate.
Reserved bits
Must always be set to “0”
PM17
Wait bit
0 : No wait state
1 : Wait state inserted
A
A
A
A
R W
Notes 1: Set bit 1 of the protect register (address 000A16) to “1” when writing new values
to thie register.
2: As this bit becomes “0” at reset, must always be set to “1” after reset release.
: Bit in which nothing is assigned
Notes 1: Values immediately after reset release
0 ••••••••••••••••••“0” after reset release
1 ••••••••••••••••••“1” after reset release
? ••••••••••••••••••Indeterminate after reset release
✕••••••••••••••••••Bit in which nothing is assigned
2: Bit attributes••••••The attributes of control register bits are classified into 3 types : read-only,
write-only and read and write. In the figure, these attributes are represented
as follows :
R••••••Read
••••••Read enabled
✕••••••Read disabled
••••••Bit in which nothing is assigned (The read value is indeterminate unless otherwise mentioned.)
A
A
W ••••••Write
••••••Write enabled
✕••••••Write disabled
••••••Bit in which nothing is assigned
Rev.1.00
May 18, 2004
page 296 of 296
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REVISION HISTORY
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
Rev.
No.
Revision Description
Rev.
date
1.00
First Edition of PDF File
May 18, 2004
(1/1)