STMICROELECTRONICS M41ST85WMH6TR

M41ST85Y
M41ST85W
5.0 OR 3.0V, 512 bit (64 x 8) SERIAL
RTC and NVRAM SUPERVISOR
FEATURES SUMMARY
■ 5.0 OR 3.0V OPERATING VOLTAGE
■
SERIAL INTERFACE SUPPORTS
(400 KHz)
I2C
NVRAM SUPERVISOR FOR EXTERNAL
LPSRAM
■
OPTIMIZED FOR MINIMAL INTERCONNECT
TO MCU
■
2.5 TO 5.5V OSCILLATOR OPERATING
VOLTAGE
■
AUTOMATIC SWITCH-OVER and DESELECT
CIRCUITRY
■
CHOICE OF POWER-FAIL DESELECT
VOLTAGES
■
PACKAGING INCLUDES A 28-LEAD SOIC and
SNAPHAT® TOP (to be Ordered Separately)
■
SOIC SNAPHAT PACKAGE PROVIDES
DIRECT CONNECTION FOR A SNAPHAT
TOP WHICH CONTAINS THE BATTERY and
CRYSTAL
■
SOIC EMBEDDED CRYSTAL PACKAGE (MX)
OPTION
BUS
■
■
■
Figure 1. 28-pin SOIC Package
SNAPHAT (SH)
Battery & Crystal
– M41ST85Y: VCC = 4.5 to 5.5V;
4.20V ≤ VPFD ≤ 4.50V
– M41ST85W: VCC = 2.7 to 3.6V;
2.55V ≤ VPFD ≤ 2.70V
1.25V REFERENCE (for PFI/PFO)
COUNTERS FOR TENTHS/HUNDREDTHS
OF SECONDS, SECONDS, MINUTES,
HOURS, DAY, DATE, MONTH, YEAR, and
CENTURY
■
44 BYTES OF GENERAL PURPOSE RAM
■
PROGRAMMABLE ALARM and INTERRUPT
FUNCTION (VALID EVEN DURING BATTERY
BACK-UP MODE)
■
WATCHDOG TIMER
■
MICROPROCESSOR POWER-ON RESET
■
BATTERY LOW FLAG
■
POWER-DOWN TIMESTAMP (HT BIT)
■
ULTRA-LOW BATTERY SUPPLY CURRENT
OF 500nA (MAX)
May 2003
Rev. 4.0
28
1
SOH28 (MH)
Figure 2. 28-pin (300mil) SOIC Package
EMBEDDED Crystal
SOX28 (MX)
1/33
M41ST85Y, M41ST85W
TABLE OF CONTENTS
SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 3. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 4. 28-pin SOIC Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 6. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 7. Hardware Hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 2. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 3. DC and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 8. AC Testing Input/Output Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 4. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 5. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
OPERATING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2-Wire Bus Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 9. Serial Bus Data Transfer Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 11. WRITE Cycle Timing: RTC & External SRAM Control Signals . . . . . . . . . . . . . . . . . . . 12
Figure 12. Bus Timing Requirements Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 6. AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
READ Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 13. Slave Address Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 14. READ Mode Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 15. Alternate READ Mode Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
WRITE Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 16. WRITE Mode Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Data Retention Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 17. Power Down/Up Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 7. Power Down/Up AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
CLOCK OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
TIMEKEEPER® Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 8. TIMEKEEPER® Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Calibrating the Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Setting Alarm Clock Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 18. Alarm Interrupt Reset Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 9. Alarm Repeat Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 19. Back-Up Mode Alarm Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2/33
M41ST85Y, M41ST85W
Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Square Wave Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 10. Square Wave Output Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Power-on Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Reset Inputs (RSTIN1 & RSTIN2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 20. RSTIN1 & RSTIN2 Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 11. Reset AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Power-fail INPUT/OUTPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Century Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Output Driver Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Battery Low Warning. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
tREC Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Initial Power-on Defaults. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 12. tREC Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 13. Default Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 21. Crystal Accuracy Across Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 22. Calibration Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 15. SNAPHAT Battery Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3/33
M41ST85Y, M41ST85W
SUMMARY DESCRIPTION
The M41ST85Y/W Serial TIMEKEEPER®/Controller SRAM is a low power 512-bit, static CMOS
SRAM organized as 64 words by 8 bits. A built-in
32.768 kHz oscillator (external crystal controlled)
and 8 bytes of the SRAM (see Table 8, page 18)
are used for the clock/calendar function and are
configured in binary coded decimal (BCD) format.
An additional 12 bytes of RAM provide status/control of Alarm, Watchdog and Square Wave functions. Addresses and data are transferred serially
via a two line, bi-directional I2C interface. The
built-in address register is incremented automatically after each WRITE or READ data byte. The
M41ST85Y/W has a built-in power sense circuit
which detects power failures and automatically
switches to the battery supply when a power failure occurs. The energy needed to sustain the
SRAM and clock operations can be supplied by a
small lithium button-cell supply when a power failure occurs.
Functions available to the user include a non-volatile, time-of-day clock/calendar, Alarm interrupts,
Watchdog Timer and programmable Square
Wave output. Other features include a Power-On
Reset as well as two additional debounced inputs
(RSTIN1 and RSTIN2) which can also generate an
output Reset (RST). The eight clock address locations contain the century, year, month, date, day,
hour, minute, second and tenths/hundredths of a
second in 24 hour BCD format. Corrections for 28,
4/33
29 (leap year - valid until year 2100), 30 and 31
day months are made automatically.
The M41ST85Y/W is supplied in a 28-lead SOIC
SNAPHAT® package (which integrates both crystal and battery in a single SNAPHAT top) or a 28pin, 300mil SOIC package (MX) which includes an
embedded 32kHz crystal.
The 28-pin, 330mil SOIC provides sockets with
gold plated contacts at both ends for direct connection to a separate SNAPHAT housing containing the battery and crystal. The unique design
allows the SNAPHAT battery/crystal package to
be mounted on top of the SOIC package after the
completion of the surface mount process.
Insertion of the SNAPHAT housing after reflow
prevents potential battery and crystal damage due
to the high temperatures required for device surface-mounting. The SNAPHAT housing is also
keyed to prevent reverse insertion.
The SOIC and battery/crystal packages are
shipped separately in plastic anti-static tubes or in
Tape & Reel form. For the 28-lead SOIC, the battery/crystal package (e.g., SNAPHAT) part number is “M4TXX-BR12SH” (see Table 15, page 27).
Caution: Do not place the SNAPHAT battery/crystal top in conductive foam, as this will drain the lithium button-cell battery.
The 300mil, embedded crystal SOIC requires only
a user-supplied battery to provide non-volatile operation.
M41ST85Y, M41ST85W
Figure 3. Logic Diagram
VCC
Table 1. Signal Names
ECON
Conditioned Chip Enable Output
EX
External Chip Enable
IRQ/FT/OUT
Interrupt/Frequency Test/Out Output
(Open Drain)
PFI
Power Fail Input
ECON
PFO
Power Fail Output
RST
RST
Reset Output (Open Drain)
RSTIN1
Reset 1 Input
(1)
VBAT
SCL
SDA
EX
RSTIN1
IRQ/FT/OUT
M41ST85Y
M41ST85W
RSTIN2
Reset 2 Input
SQW
SCL
Serial Clock Input
PFO
SDA
Serial Data Input/Output
SQW
Square Wave Output
WDI
Watchdog Input
VCC
Supply Voltage
VOUT
Voltage Output
VSS
Ground
VBAT(1)
Battery Supply Voltage
RSTIN2
WDI
VOUT
PFI
VSS
AI03658
Note: 1. For 28-pin, 300mil embedded crystal SOIC only.
Note: 1. For 28-pin, 300mil embedded crystal SOIC only.
Figure 4. 28-pin SOIC Connections
Figure 5. 28-pin, 300mil SOIC (MX)
Connections
SQW
NC
NC
NC
NC
NC
NC
WDI
RSTIN1
RSTIN2
NC
NC
PFO
VSS
1
28
27
2
26
3
25
4
24
5
23
6
7 M41ST85Y 22
8 M41ST85W 21
20
9
19
10
18
11
17
12
16
13
15
14
AI03659
VCC
EX
IRQ/FT/OUT
VOUT
NC
NC
PFI
NC
SCL
NC
RST
NC
SDA
ECON
NC
NC
NC
NC
NC
NC
NC
SQW
WDI
RSTIN1
RSTIN2
PFO
NC
VSS
1
28
27
2
26
3
25
4
24
5
23
6
7 M41ST85Y 22
8 M41ST85W 21
20
9
19
10
18
11
17
12
16
13
15
14
VCC
EX
IRQ/FT/OUT
VOUT
VSS
PFI
SCL
NC
NC
RST
NC
SDA
ECON
VBAT
AI06370c
5/33
M41ST85Y, M41ST85W
Figure 6. Block Diagram
REAL TIME CLOCK
CALENDAR
SDA
44 BYTES
USER RAM
I2C
INTERFACE
RTC w/ALARM
& CALIBRATION
SCL
(2)
WATCHDOG
32KHz
OSCILLATOR
Crystal
SQUARE WAVE
WDI
VCC
AFE
WDS
IRQ/FT/OUT(1)
SQW
VOUT
VBAT
VBL= 2.5V
COMPARE
VSO = 2.5V
COMPARE
VPFD = 4.4V
COMPARE
(2.65V for ST85W)
RSTIN1
BL
POR
RST(1)
RSTIN2
ECON
EX
PFI
COMPARE
PFO
1.25V
(Internal)
AI03932
Note: 1. Open drain output
2. Integrated into SOIC package for MX package option.
6/33
M41ST85Y, M41ST85W
Figure 7. Hardware Hookup
M41ST85Y/W
Regulator
Unregulated
Voltage
VIN
VCC
VCC
VOUT
VCC
ECON
E
M68Z128Y/W
or
M68Z512Y/W
From MCU
EX
R1
Pushbutton
Reset
SCL
WDI
SDA
RSTIN1
RST
RSTIN2
SQW
To RST
To LED Display
PFO
To NMI
(1) IRQ/FT/OUT
To INT
PFI
VBAT
R2
VSS
AI03660
Note: 1. Required for embedded crystal (MX) package only.
MAXIMUM RATING
Stressing the device above the rating listed in the
“Absolute Maximum Ratings” table may cause
permanent damage to the device. These are
stress ratings only and operation of the device at
these or any other conditions above those indicated in the Operating sections of this specification is
not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device
reliability.
Refer
also
to
the
STMicroelectronics SURE Program and other relevant quality documents.
Table 2. Absolute Maximum Ratings
Symbol
TSTG
TSLD (1)
Parameter
Storage Temperature (VCC Off, Oscillator Off)
Value
Unit
SNAPHAT®
–40 to 85
°C
SOIC
–55 to 125
°C
260
°C
–0.3 to VCC+0.3
V
M41ST85Y
–0.3 to 7
V
M41ST85W
–0.3 to 4.6
V
Lead Solder Temperature for 10 seconds
VIO
Input or Output Voltage
VCC
Supply Voltage
IO
Output Current
20
mA
PD
Power Dissipation
1
W
Note: 1. Reflow at peak temperature of 215°C to 225°C for < 60 seconds (total thermal budget not to exceed 180°C for between 90 to 120
seconds).
CAUTION: Negative undershoots below –0.3V are not allowed on any pin while in the Battery Back-up mode.
CAUTION: Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets.
7/33
M41ST85Y, M41ST85W
DC AND AC PARAMETERS
This section summarizes the operating and measurement conditions, as well as the DC and AC
characteristics of the device. The parameters in
the following DC and AC Characteristic tables are
derived from tests performed under the Measure-
ment Conditions listed in the relevant tables. Designers should check that the operating conditions
in their projects match the measurement conditions when using the quoted parameters.
Table 3. DC and AC Measurement Conditions
Parameter
M41ST85Y
M41ST85W
VCC Supply Voltage
4.5 to 5.5V
2.7 to 3.6V
Ambient Operating Temperature
–40 to 85°C
–40 to 85°C
Load Capacitance (CL)
100pF
50pF
Input Rise and Fall Times
≤ 50ns
≤ 50ns
Input Pulse Voltages
0.2 to 0.8VCC
0.2 to 0.8VCC
Input and Output Timing Ref. Voltages
0.3 to 0.7VCC
0.3 to 0.7VCC
Note: Output High Z is defined as the point where data is no longer driven.
Figure 8. AC Testing Input/Output Waveforms
0.8VCC
0.7VCC
0.3VCC
0.2VCC
AI02568
Note: 50pF for M41ST85W.
Table 4. Capacitance
Parameter(1,2)
Symbol
CIN
COUT(3)
tLP
Min
Max
Unit
Input Capacitance
7
pF
Output Capacitance
10
pF
Low-pass filter input time constant (SDA and SCL)
50
ns
Note: 1. Effective capacitance measured with power supply at 5V. Sampled only, not 100% tested.
2. At 25°C, f = 1MHz.
3. Outputs are deselected.
8/33
M41ST85Y, M41ST85W
Table 5. DC Characteristics
Sym
IBAT(2)
Parameter
Battery Current OSC
ON
Battery Current OSC
OFF
Test
Condition(1)
M41ST85Y
M41ST85W
Unit
Min
TA = 25°C,
VCC = 0V,
VBAT = 3V
Typ
Max
400
500
Min
50
Typ
Max
400
500
50
nA
nA
ICC1
Supply Current
f = 400kHz
1.4
0.75
mA
ICC2
Supply Current
(Standby)
SCL, SDA =
VCC – 0.3V
1
0.50
mA
0V ≤ VIN ≤
VCC
±1
±1
µA
25
nA
Input Leakage Current
ILI(3)
Input Leakage Current
(PFI)
–25
2
25
–25
2
0V ≤ VIN ≤
VCC
±1
±1
µA
IOUT1(5) VOUT Current (Active)
VOUT1 >
VCC – 0.3V
175
100
mA
VOUT Current (Battery
Back-up)
VOUT2 >
VBAT – 0.3V
100
100
µA
ILO(4)
IOUT2
Output Leakage
Current
VIH
Input High Voltage
0.7VCC
VCC + 0.3
0.7VCC
VCC + 0.3
V
VIL
Input Low Voltage
–0.3
0.3VCC
–0.3
0.3VCC
V
VBAT
Battery Voltage
2.5
3.5(9)
2.5
3.5(9)
V
VOH
Output High Voltage(6)
VOHB(7) VOH (Battery Back-up)
VOL
VPFD
VPFI
2.4
IOUT2 =
–1.0µA
2.5
3.0
2.4
2.9
3.5
2.5
V
2.9
3.5
V
Output Low Voltage
IOL = 3.0mA
0.4
0.4
V
Output Low Voltage
(Open Drain)(8)
IOL = 10mA
0.4
0.4
V
Power Fail Deselect
PFI Input Threshold
PFI Hysteresis
VSO
IOH = –1.0mA
3.0
Battery Back-up
Switchover
VCC = 5V(Y)
VCC = 3V(V)
PFI Rising
4.20
4.40
4.50
2.55
2.60
2.70
V
1.225
1.250
1.275
1.225
1.250
1.275
V
20
70
20
70
mV
2.5
2.5
V
Note: 1.
2.
3.
4.
5.
6.
7.
Valid for Ambient Operating Temperature: TA = –40 to 85°C; VCC = 4.5 to 5.5V or 2.7 to 3.6V (except where noted).
Measured with VOUT and ECON open.
RSTIN1 and RSTIN2 internally pulled-up to VCC through 100KΩ resistor. WDI internally pulled-down to VSS through 100KΩ resistor.
Outputs Deselected.
External SRAM must match RTC SUPERVISOR chip VCC specification.
For PFO and SQW pins (CMOS).
Conditioned output (E CON) can only sustain CMOS leakage current in the battery back-up mode. Higher leakage currents will reduce battery life.
8. For IRQ/FT/OUT, RST pins (Open Drain): if pulled-up to supply other than VCC, this supply must be equal to, or less than 3.0V when
VCC = 0V (during battery back-up mode).
9. For rechargeable back-up, VBAT (max) may be considered VCC.
9/33
M41ST85Y, M41ST85W
OPERATING MODES
The M41ST85Y/W clock operates as a slave device on the serial bus. Access is obtained by implementing a start condition followed by the
correct slave address (D0h). The 64 bytes contained in the device can then be accessed sequentially in the following order:
1. Tenths/Hundredths of a Second Register
2. Seconds Register
3. Minutes Register
4. Century/Hours Register
5. Day Register
6. Date Register
7. Month Register
8. Year Register
9. Control Register
10. Watchdog Register
11 - 16. Alarm Registers
17 - 19. Reserved
20. Square Wave Register
21 - 64. User RAM
The M41ST85Y/W clock continually monitors VCC
for an out-of-tolerance condition. Should VCC fall
below VPFD, the device terminates an access in
progress and resets the device address counter.
Inputs to the device will not be recognized at this
time to prevent erroneous data from being written
to the device from a an out-of-tolerance system.
When VCC falls below VSO, the device automatically switches over to the battery and powers
down into an ultra low current mode of operation to
10/33
conserve battery life. As system power returns and
VCC rises above VSO , the battery is disconnected,
and the power supply is switched to external VCC.
Write protection continues until VCC reaches
VPFD(min) plus tREC(min).
For more information on Battery Storage Life refer
to Application Note AN1012.
2-Wire Bus Characteristics
The bus is intended for communication between
different ICs. It consists of two lines: a bi-directional data signal (SDA) and a clock signal (SCL).
Both the SDA and SCL lines must be connected to
a positive supply voltage via a pull-up resistor.
The following protocol has been defined:
– Data transfer may be initiated only when the bus
is not busy.
– During data transfer, the data line must remain
stable whenever the clock line is High.
– Changes in the data line, while the clock line is
High, will be interpreted as control signals.
Accordingly, the following bus conditions have
been defined:
Bus not busy. Both data and clock lines remain
High.
Start data transfer. A change in the state of the
data line, from High to Low, while the clock is High,
defines the START condition.
Stop data transfer. A change in the state of the
data line, from Low to High, while the clock is High,
defines the STOP condition.
M41ST85Y, M41ST85W
Data Valid. The state of the data line represents
valid data when after a start condition, the data line
is stable for the duration of the high period of the
clock signal. The data on the line may be changed
during the Low period of the clock signal. There is
one clock pulse per bit of data.
Each data transfer is initiated with a start condition
and terminated with a stop condition. The number
of data bytes transferred between the start and
stop conditions is not limited. The information is
transmitted byte-wide and each receiver acknowledges with a ninth bit.
By definition a device that gives out a message is
called “transmitter,” the receiving device that gets
the message is called “receiver.” The device that
controls the message is called “master.” The devices that are controlled by the master are called
“slaves.”
Acknowledge. Each byte of eight bits is followed
by one Acknowledge Bit. This Acknowledge Bit is
a low level put on the bus by the receiver whereas
the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed is obliged to generate an acknowledge
after the reception of each byte that has been
clocked out of the slave transmitter.
The device that acknowledges has to pull down
the SDA line during the acknowledge clock pulse
in such a way that the SDA line is a stable Low during the High period of the acknowledge related
clock pulse. Of course, setup and hold times must
be taken into account. A master receiver must signal an end of data to the slave transmitter by not
generating an acknowledge on the last byte that
has been clocked out of the slave. In this case the
transmitter must leave the data line High to enable
the master to generate the STOP condition.
Figure 9. Serial Bus Data Transfer Sequence
DATA LINE
STABLE
DATA VALID
CLOCK
DATA
START
CONDITION
CHANGE OF
DATA ALLOWED
STOP
CONDITION
AI00587
Figure 10. Acknowledgement Sequence
CLOCK PULSE FOR
ACKNOWLEDGEMENT
START
SCL FROM
MASTER
DATA OUTPUT
BY TRANSMITTER
1
MSB
2
8
9
LSB
DATA OUTPUT
BY RECEIVER
AI00601
11/33
M41ST85Y, M41ST85W
Figure 11. WRITE Cycle Timing: RTC & External SRAM Control Signals
EX
tEXPD
tEXPD
ECON
AI03663
Figure 12. Bus Timing Requirements Sequence
SDA
tBUF
tHD:STA
tHD:STA
tR
tF
SCL
tHIGH
P
S
tLOW
tSU:DAT
tHD:DAT
tSU:STA
SR
tSU:STO
P
AI00589
Table 6. AC Characteristics
Parameter(1)
Symbol
fSCL
SCL Clock Frequency
tBUF
Time the bus must be free before a new transmission can start
tEXPD
EX to ECON Propagation Delay
tF
tHD:DAT(2)
Min
Max
Unit
0
400
kHz
1.3
µs
M41ST85Y
10
M41ST85W
15
ns
SDA and SCL Fall Time
ns
0
µs
START Condition Hold Time
(after this period the first clock pulse is generated)
600
ns
tHIGH
Clock High Period
600
ns
tLOW
Clock Low Period
1.3
µs
tHD:STA
tR
Data Hold Time
300
SDA and SCL Rise Time
300
ns
tSU:DAT
Data Setup Time
100
ns
tSU:STA
START Condition Setup Time
(only relevant for a repeated start condition)
600
ns
tSU:STO
STOP Condition Setup Time
600
ns
Note: 1. Valid for Ambient Operating Temperature: TA = –40 to 85°C; VCC = 4.5 to 5.5V or 2.7 to 3.6V (except where noted).
2. Transmitter must internally provide a hold time to bridge the undefined region (300ns max) of the falling edge of SCL.
12/33
M41ST85Y, M41ST85W
READ Mode
In this mode the master reads the M41ST85Y/W
slave after setting the slave address (see Figure
13, page 13). Following the WRITE Mode Control
Bit (R/W=0) and the Acknowledge Bit, the word
address 'An' is written to the on-chip address
pointer. Next the START condition and slave address are repeated followed by the READ Mode
Control Bit (R/W=1). At this point the master transmitter becomes the master receiver.
The data byte which was addressed will be transmitted and the master receiver will send an Acknowledge Bit to the slave transmitter. The
address pointer is only incremented on reception
of an Acknowledge Clock. The M41ST85Y/W
slave transmitter will now place the data byte at
address An+1 on the bus, the master receiver
reads and acknowledges the new byte and the address pointer is incremented to An+2.
This cycle of reading consecutive addresses will
continue until the master receiver sends a STOP
condition to the slave transmitter (see Figure 14,
page 13).
The system-to-user transfer of clock data will be
halted whenever the address being read is a clock
address (00h to 07h). The update will resume either due to a Stop Condition or when the pointer
increments to a non-clock or RAM address.
Note: This is true both in READ Mode and WRITE
Mode.
An alternate READ Mode may also be implemented whereby the master reads the M41ST85Y/W
slave without first writing to the (volatile) address
pointer. The first address that is read is the last
one stored in the pointer (see Figure 15, page 14).
Figure 13. Slave Address Location
R/W
SLAVE ADDRESS
1
A
LSB
MSB
START
1
0
1
0
0
0
AI00602
R/W
START
SLAVE
ADDRESS
ACK
DATA n+1
ACK
DATA n
ACK
BUS ACTIVITY:
S
ACK
WORD
ADDRESS (An)
STOP
SLAVE
ADDRESS
DATA n+X
P
NO ACK
S
R/W
SDA LINE
ACK
BUS ACTIVITY:
MASTER
START
Figure 14. READ Mode Sequence
AI00899
13/33
M41ST85Y, M41ST85W
STOP
SLAVE
ADDRESS
P
NO ACK
BUS ACTIVITY:
DATA n+X
ACK
DATA n+1
ACK
DATA n
ACK
S
ACK
SDA LINE
R/W
BUS ACTIVITY:
MASTER
START
Figure 15. Alternate READ Mode Sequence
AI00895
WRITE Mode
In this mode the master transmitter transmits to
the M41ST85Y/W slave receiver. Bus protocol is
shown in Figure 16, page 14. Following the
START condition and slave address, a logic '0' (R/
W=0) is placed on the bus and indicates to the addressed device that word address An will follow
and is to be written to the on-chip address pointer.
The data word to be written to the memory is
strobed in next and the internal address pointer is
incremented to the next memory location within
the RAM on the reception of an acknowledge
clock. The M41ST85Y/W slave receiver will send
an acknowledge clock to the master transmitter after it has received the slave address (see Figure
13, page 13) and again after it has received the
word address and each data byte.
SLAVE
ADDRESS
14/33
STOP
DATA n+X
P
ACK
DATA n+1
ACK
BUS ACTIVITY:
DATA n
ACK
WORD
ADDRESS (An)
ACK
S
R/W
SDA LINE
ACK
BUS ACTIVITY:
MASTER
START
Figure 16. WRITE Mode Sequence
AI00591
M41ST85Y, M41ST85W
Data Retention Mode
With valid VCC applied, the M41ST85Y/W can be
accessed as described above with READ or
WRITE Cycles. Should the supply voltage decay,
the M41ST85Y/W will automatically deselect,
write protecting itself (and any external SRAM)
when VCC falls between VPFD(max) and
VPFD(min). This is accomplished by internally inhibiting access to the clock registers. At this time,
the Reset pin (RST) is driven active and will remain active until VCC returns to nominal levels. External RAM access is inhibited in a similar manner
by forcing ECON to a high level. This level is within
0.2 volts of the VBAT. ECON will remain at this level
as long as VCC remains at an out-of-tolerance condition. When VCC falls below the Battery Back-up
Switchover Voltage (VSO), power input is switched
from the VCC pin to the SNAPHAT® battery, and
the clock registers and external SRAM are maintained from the attached battery supply.
All outputs become high impedance. The VOUT pin
is capable of supplying 100 µA of current to the attached memory with less than 0.3 volts drop under
this condition. On power up, when VCC returns to
a nominal value, write protection continues for
tREC by inhibiting ECON. The RST signal also remains active during this time (see Figure 17, page
16).
Note: Most low power SRAMs on the market today can be used with the M41ST85Y/W RTC SUPERVISOR. There are, however some criteria
which should be used in making the final choice of
an SRAM to use. The SRAM must be designed in
a way where the chip enable input disables all other inputs to the SRAM. This allows inputs to the
M41ST85Y/W and SRAMs to be “Don’t Care”
once VCC falls below VPFD(min). The SRAM
should also guarantee data retention down to
VCC=2.0 volts. The chip enable access time must
be sufficient to meet the system needs with the
chip enable output propagation delays included. If
the SRAM includes a second chip enable pin (E2),
this pin should be tied to VOUT.
If data retention lifetime is a critical parameter for
the system, it is important to review the data retention current specifications for the particular
SRAMs being evaluated. Most SRAMs specify a
data retention current at 3.0 volts. Manufacturers
generally specify a typical condition for room temperature along with a worst case condition (generally at elevated temperatures). The system level
requirements will determine the choice of which
value to use. The data retention current value of
the SRAMs can then be added to the IBAT value of
the M41ST85Y/W to determine the total current requirements for data retention. The available battery capacity for the SNAPHAT® of your choice
can then be divided by this current to determine
the amount of data retention available (see Table
15, page 27).
For a further more detailed review of lifetime calculations, please see Application Note AN1012.
15/33
M41ST85Y, M41ST85W
Figure 17. Power Down/Up Mode AC Waveforms
VCC
VPFD (max)
VPFD (min)
VSO
tF
tR
tFB
tRB
tDR
tPD
tREC
PFO
INPUTS
RECOGNIZED
DON'T CARE
RECOGNIZED
RST
HIGH-Z
OUTPUTS
VALID
VALID
(PER CONTROL INPUT)
(PER CONTROL INPUT)
ECON
AI03661
Table 7. Power Down/Up AC Characteristics
Symbol
Parameter(1)
Min
Typ
Max
Unit
tF(2)
VPFD(max) to VPFD(min) VCC Fall Time
300
µs
tFB(3)
VPFD(min) to VSS VCC Fall Time
10
µs
tPD
EX at VIH before Power Down
0
µs
tPFD
PFI to PFO Propagation Delay
15
25
µs
tR
VPFD(min) to VPFD(max) VCC Rise Time
10
µs
tRB
VSS to VPFD(min) VCC Rise Time
1
µs
Power up Deselect Time
40
tREC(4)
200
Note: 1. Valid for Ambient Operating Temperature: TA = –40 to 85°C; VCC = 4.5 to 5.5V or 2.7 to 3.6V (except where noted).
2. VPFD(max) to VPFD(min) fall time of less than tF may result in deselection/write protection not occurring until
200µs after VCC passes VPFD(min).
3. VPFD(min) to VSS fall time of less than tFB may cause corruption of RAM data.
4. Programmable (see Table 12, page 25)
16/33
ms
M41ST85Y, M41ST85W
CLOCK OPERATION
The eight byte clock register (see Table 8, page
18) is used to both set the clock and to read the
date and time from the clock, in a binary coded
decimal format. Tenths/Hundredths of Seconds,
Seconds, Minutes, and Hours are contained within
the first four registers.
Note: A WRITE to any clock register will result in
the Tenths/Hundredths of Seconds being reset to
“00,” and Tenths/Hundredths of Seconds cannot
be written to any value other than “00.”
Bits D6 and D7 of Clock Register 03h (Century/
Hours Register) contain the CENTURY ENABLE
Bit (CEB) and the CENTURY Bit (CB). Setting
CEB to a '1' will cause CB to toggle, either from '0'
to '1' or from '1' to '0' at the turn of the century (depending upon its initial state). If CEB is set to a '0,'
CB will not toggle. Bits D0 through D2 of Register
04h contain the Day (day of week). Registers 05h,
06h, and 07h contain the Date (day of month),
Month and Years. The ninth clock register is the
Control Register (this is described in the Clock
Calibration section). Bit D7 of Register 01h contains the STOP Bit (ST). Setting this bit to a '1' will
cause the oscillator to stop. If the device is expected to spend a significant amount of time on the
shelf, the oscillator may be stopped to reduce current drain. When reset to a '0' the oscillator restarts
within one second.
The eight Clock Registers may be read one byte at
a time, or in a sequential block. The Control Register (Address location 08h) may be accessed independently. Provision has been made to assure
that a clock update does not occur while any of the
eight clock addresses are being read. If a clock address is being read, an update of the clock registers will be halted. This will prevent a transition of
data during the READ.
Note: When a power failure occurs, the Halt Update Bit (HT) will automatically be set to a '1.' This
will prevent the clock from updating the TIMEKEEPER® registers, and will allow the user to read
the exact time of the power-down event. Resetting
the HT Bit to a '0' will allow the clock to update the
TIMEKEEPER registers with the current time.
TIMEKEEPER ® Registers
The M41ST85Y/W offers 20 internal registers
which contain Clock, Alarm, Watchdog, Flag,
Square Wave and Control data. These registers
are memory locations which contain external (user
accessible) and internal copies of the data (usually
referred to as BiPORT™ TIMEKEEPER cells). The
external copies are independent of internal functions except that they are updated periodically by
the simultaneous transfer of the incremented internal copy. The internal divider (or clock) chain will
be reset upon the completion of a WRITE to any
clock address.
The system-to-user transfer of clock data will be
halted whenever the address being read is a clock
address (00h to 07h). The update will resume either due to a Stop Condition or when the pointer
increments to a non-clock or RAM address.
TIMEKEEPER and Alarm Registers store data in
BCD. Control, Watchdog and Square Wave Registers store data in Binary Format.
17/33
M41ST85Y, M41ST85W
Table 8. TIMEKEEPER® Register Map
Data
Address
D7
00h
D6
D5
D4
D3
D2
0.1 Seconds
D1
D0
Function/Range
BCD Format
0.01 Seconds
Seconds
00-99
01h
ST
10 Seconds
Seconds
Seconds
00-59
02h
0
10 Minutes
Minutes
Minutes
00-59
03h
CEB
CB
Hours (24 Hour Format)
Century/Hours
0-1/00-23
04h
TR
0
Day
01-7
05h
0
0
Date: Day of Month
Date
01-31
06h
0
0
Month
Month
01-12
Year
Year
00-99
07h
10 Hours
0
0
0
10 Date
0
Day of Week
10M
10 Years
08h
OUT
FT
S
09h
WDS
BMB4
BMB3
BMB2
0Ah
AFE
SQWE
ABE
Al 10M
0Bh
RPT4
RPT5
0Ch
RPT3
HT
0Dh
RPT2
0Eh
RPT1
0Fh
WDF
AF
0
BL
0
0
0
0
Flags
10h
0
0
0
0
0
0
0
0
Reserved
11h
0
0
0
0
0
0
0
0
Reserved
12h
0
0
0
0
0
0
0
0
Reserved
13h
RS3
RS2
RS1
RS0
0
0
0
0
SQW
BMB1
BMB0
Control
RB1
RB0
Watchdog
Alarm Month
Al Month
01-12
AI 10 Date
Alarm Date
Al Date
01-31
AI 10 Hour
Alarm Hour
Al Hour
00-23
Alarm 10 Minutes
Alarm Minutes
Al Min
00-59
Alarm 10 Seconds
Alarm Seconds
Al Sec
00-59
Keys: S = Sign Bit
FT = Frequency Test Bit
ST = Stop Bit
0 = Must be set to zero
BL = Battery Low Flag (Read only)
BMB0-BMB4 = Watchdog Multiplier Bits
CEB = Century Enable Bit
CB = Century Bit
OUT = Output level
AFE = Alarm Flag Enable Flag
18/33
Calibration
RB0-RB1 = Watchdog Resolution Bits
WDS = Watchdog Steering Bit
ABE = Alarm in Battery Back-Up Mode Enable Bit
RPT1-RPT5 = Alarm Repeat Mode Bits
WDF = Watchdog flag (Read only)
AF = Alarm flag (Read only)
SQWE = Square Wave Enable
RS0-RS3 = SQW Frequency
HT = Halt Update Bit
TR = tREC Bit
M41ST85Y, M41ST85W
Calibrating the Clock
The M41ST85Y/W is driven by a quartz controlled
oscillator with a nominal frequency of 32,768 Hz.
The devices are tested not exceed +/–35 PPM
(parts per million) oscillator frequency error at
25oC, which equates to about +/–1.53 minutes per
month. When the Calibration circuit is properly employed, accuracy improves to better than +1/–2
ppm at 25°C.
The oscillation rate of crystals changes with temperature (see Figure 21, page 26). Therefore, the
M41ST85Y/W design employs periodic counter
correction. The calibration circuit adds or subtracts
counts from the oscillator divider circuit at the divide by 256 stage, as shown in Figure 22, page 26.
The number of times pulses which are blanked
(subtracted, negative calibration) or split (added,
positive calibration) depends upon the value loaded into the five Calibration Bits found in the Control
Register. Adding counts speeds the clock up, subtracting counts slows the clock down.
The Calibration Bits occupy the five lower order
bits (D4-D0) in the Control Register (08h). These
bits can be set to represent any value between 0
and 31 in binary form. Bit D5 is a Sign Bit; '1' indicates positive calibration, '0' indicates negative
calibration. Calibration occurs within a 64 minute
cycle. The first 62 minutes in the cycle may, once
per minute, have one second either shortened by
128 or lengthened by 256 oscillator cycles. If a binary '1' is loaded into the register, only the first 2
minutes in the 64 minute cycle will be modified; if
a binary 6 is loaded, the first 12 will be affected,
and so on.
Therefore, each calibration step has the effect of
adding 512 or subtracting 256 oscillator cycles for
every 125,829,120 actual oscillator cycles, that is
+4.068 or –2.034 PPM of adjustment per calibration step in the calibration register. Assuming that
the oscillator is running at exactly 32,768 Hz, each
of the 31 increments in the Calibration byte would
represent +10.7 or –5.35 seconds per month
which corresponds to a total range of +5.5 or –2.75
minutes per month.
Two methods are available for ascertaining how
much calibration a given M41ST85Y/W may require.
The first involves setting the clock, letting it run for
a month and comparing it to a known accurate reference and recording deviation over a fixed period
of time. Calibration values, including the number of
seconds lost or gained in a given period, can be
found in Application Note AN934, “TIMEKEEPER ® CALIBRATION.” This allows the designer to
give the end user the ability to calibrate the clock
as the environment requires, even if the final prod-
uct is packaged in a non-user serviceable enclosure. The designer could provide a simple utility
that accesses the Calibration byte.
The second approach is better suited to a manufacturing environment, and involves the use of the
IRQ/FT/OUT pin. The pin will toggle at 512Hz,
when the Stop Bit (ST, D7 of 01h) is '0,' the Frequency Test Bit (FT, D6 of 08h) is '1,' the Alarm
Flag Enable Bit (AFE, D7 of 0Ah) is '0,' and the
Watchdog Steering Bit (WDS, D7 of 09h) is '1' or
the Watchdog Register (09h = 0) is reset.
Any deviation from 512 Hz indicates the degree
and direction of oscillator frequency shift at the test
temperature. For example, a reading of
512.010124 Hz would indicate a +20 PPM oscillator frequency error, requiring a –10 (XX001010) to
be loaded into the Calibration Byte for correction.
Note that setting or changing the Calibration Byte
does not affect the Frequency test output frequency.
The IRQ/FT/OUT pin is an open drain output
which requires a pull-up resistor to VCC for proper
operation. A 500 to10k resistor is recommended in
order to control the rise time. The FT Bit is cleared
on power-down.
Setting Alarm Clock Registers
Address locations 0Ah-0Eh contain the alarm settings. The alarm can be configured to go off at a
prescribed time on a specific month, date, hour,
minute, or second, or repeat every year, month,
day, hour, minute, or second. It can also be programmed to go off while the M41ST85Y/W is in the
battery back-up to serve as a system wake-up call.
Bits RPT5–RPT1 put the alarm in the repeat mode
of operation. Table 9, page 20 shows the possible
configurations. Codes not listed in the table default
to the once per second mode to quickly alert the
user of an incorrect alarm setting.
When the clock information matches the alarm
clock settings based on the match criteria defined
by RPT5–RPT1, the AF (Alarm Flag) is set. If AFE
(Alarm Flag Enable) is also set, the alarm condition activates the IRQ/FT/OUT pin as shown in
Figure 18, page 20. To disable alarm, write '0' to
the Alarm Date Register and to RPT5–RPT1.
Note: If the address pointer is allowed to increment to the Flag Register address, an alarm condition will not cause the Interrupt/Flag to occur until
the address pointer is moved to a different address. It should also be noted that if the last address written is the “Alarm Seconds,” the address
pointer will increment to the Flag address, causing
this situation to occur.
19/33
M41ST85Y, M41ST85W
The IRQ/FT/OUT output is cleared by a READ to
the Flags Register. A subsequent READ of the
Flags Register is necessary to see that the value
of the Alarm Flag has been reset to '0.'
The IRQ/FT/OUT pin can also be activated in the
battery back-up mode. The IRQ/FT/OUT will go
low if an alarm occurs and both ABE (Alarm in Battery Back-up Mode Enable) and AFE are set. The
ABE and AFE Bits are reset during power-up,
therefore an alarm generated during power-up will
only set AF. The user can read the Flag Register
at system boot-up to determine if an alarm was
generated while the M41ST85Y/W was in the deselect mode during power-up. Figure 19, page 21
illustrates the back-up mode alarm timing.
Figure 18. Alarm Interrupt Reset Waveform
0Eh
0Fh
10h
ACTIVE FLAG
HIGH-Z
IRQ/FT/OUT
AI03664
Table 9. Alarm Repeat Modes
20/33
RPT5
RPT4
RPT3
RPT2
RPT1
Alarm Setting
1
1
1
1
1
Once per Second
1
1
1
1
0
Once per Minute
1
1
1
0
0
Once per Hour
1
1
0
0
0
Once per Day
1
0
0
0
0
Once per Month
0
0
0
0
0
Once per Year
M41ST85Y, M41ST85W
Figure 19. Back-Up Mode Alarm Waveform
VCC
VPFD
VSO
tREC
ABE, AFE Bits in Interrupt Register
AF bit in Flags Register
IRQ/FT/OUT
HIGH-Z
HIGH-Z
AI03920
Watchdog Timer
The watchdog timer can be used to detect an outof-control microprocessor. The user programs the
watchdog timer by setting the desired amount of
time-out into the Watchdog Register, address 09h.
Bits BMB4-BMB0 store a binary multiplier and the
two lower order bits RB1-RB0 select the resolution, where 00=1/16 second, 01=1/4 second, 10=1
second, and 11=4 seconds. The amount of timeout is then determined to be the multiplication of
the five-bit multiplier value with the resolution. (For
example: writing 00001110 in the Watchdog Register = 3*1 or 3 seconds).
Note: The accuracy of the timer is within ± the selected resolution.
If the processor does not reset the timer within the
specified period, the M41ST85Y/W sets the WDF
(Watchdog Flag) and generates a watchdog interrupt or a microprocessor reset.
The most significant bit of the Watchdog Register
is the Watchdog Steering Bit (WDS). When set to
a '0,' the watchdog will activate the IRQ/FT/OUT
pin when timed-out. When WDS is set to a '1,' the
watchdog will output a negative pulse on the RST
pin for tREC. The Watchdog register, FT, AFE, ABE
and SQWE Bits will reset to a '0' at the end of a
Watchdog time-out when the WDS Bit is set to a
'1.'
The watchdog timer can be reset by two methods:
1) a transition (high-to-low or low-to-high) can be
applied to the Watchdog Input pin (WDI) or 2) the
microprocessor can perform a WRITE of the
Watchdog Register. The time-out period then
starts over.
Note: The WDI pin should be tied to VSS if not
used.
In order to perform a software reset of the watchdog timer, the original time-out period can be written into the Watchdog Register, effectively
restarting the count-down cycle.
Should the watchdog timer time-out, and the WDS
Bit is programmed to output an interrupt, a value of
00h needs to be written to the Watchdog Register
in order to clear the IRQ/FT/OUT pin. This will also
disable the watchdog function until it is again programmed correctly. A READ of the Flags Register
will reset the Watchdog Flag (Bit D7; Register
0Fh).
The watchdog function is automatically disabled
upon power-up and the Watchdog Register is
cleared. If the watchdog function is set to output to
the IRQ/FT/OUT pin and the frequency test function is activated, the watchdog function prevails
and the frequency test function is denied.
21/33
M41ST85Y, M41ST85W
Square Wave Output
The M41ST85Y/W offers the user a programmable square wave function which is output on the
SQW pin. RS3-RS0 bits located in 13h establish
the square wave output frequency. These frequencies are listed in Table 10. Once the selection
of the SQW frequency has been completed, the
SQW pin can be turned on and off under software
control with the Square Wave Enable Bit (SQWE)
located in Register 0Ah.
Table 10. Square Wave Output Frequency
Square Wave Bits
22/33
Square Wave
RS3
RS2
RS1
RS0
Frequency
Units
0
0
0
0
None
–
0
0
0
1
32.768
kHz
0
0
1
0
8.192
kHz
0
0
1
1
4.096
kHz
0
1
0
0
2.048
kHz
0
1
0
1
1.024
kHz
0
1
1
0
512
Hz
0
1
1
1
256
Hz
1
0
0
0
128
Hz
1
0
0
1
64
Hz
1
0
1
0
32
Hz
1
0
1
1
16
Hz
1
1
0
0
8
Hz
1
1
0
1
4
Hz
1
1
1
0
2
Hz
1
1
1
1
1
Hz
M41ST85Y, M41ST85W
Reset Inputs (RSTIN1 & RSTIN2)
The M41ST85Y/W provides two independent inputs which can generate an output reset. The duration and function of these resets is identical to a
reset generated by a power cycle. Table 11 and
Figure 20 illustrate the AC reset characteristics of
this function. Pulses shorter than tRLRH1 and
tRLRH2 will not generate a reset condition. RSTIN1
and RSTIN2 are each internally pulled up to VCC
through a 100kΩ resistor.
Power-on Reset
The M41ST85Y/W continuously monitors VCC.
When VCC falls to the power fail detect trip point,
the RST pulls low (open drain) and remains low on
power-up for tREC after VCC passes VPFD(max).
The RST pin is an open drain output and an appropriate pull-up resistor should be chosen to control
rise time.
Figure 20. RSTIN1 & RSTIN2 Timing Waveforms
RSTIN1
tRLRH1
RSTIN2
tRLRH2
RST
(1)
tR1HRH
tR2HRH
AI03665
Note: With pull-up resistor
Table 11. Reset AC Characteristics
Symbol
Parameter(1)
Min
Max
Unit
tRLRH1(2)
RSTIN1 Low to RSTIN1 High
200
ns
tRLRH2(3)
RSTIN2 Low to RSTIN2 High
100
ms
tR1HRH(4)
RSTIN1 High to RST High
40
200
ms
tR2HRH(4)
RSTIN2 High to RST High
40
200
ms
Note: 1.
2.
3.
4.
Valid for Ambient Operating Temperature: TA = –40 to 85°C; VCC = 4.5 to 5.5V or 2.7 to 3.6V (except where noted).
Pulse width less than 50ns will result in no RESET (for noise immunity).
Pulse width less than 20ms will result in no RESET (for noise immunity).
Programmable (see Table 12, page 25).
23/33
M41ST85Y, M41ST85W
Power-fail INPUT/OUTPUT
The Power-Fail Input (PFI) is compared to an internal reference voltage (1.25V). If PFI is less than
the power-fail threshold (VPFI), the Power-Fail
Output (PFO) will go low. This function is intended
for use as an undervoltage detector to signal a failing power supply. Typically PFI is connected
through an external voltage divider (see Figure 7,
page 7) to either the unregulated DC input (if it is
available) or the regulated output of the VCC regulator. The voltage divider can be set up such that
the voltage at PFI falls below VPFI several milliseconds before the regulated VCC input to the
M41ST85Y/W or the microprocessor drops below
the minimum operating voltage.
During battery back-up, the power-fail comparator
turns off and PFO goes (or remains) low. This occurs after VCC drops below VPFD(min). When power returns, PFO is forced high, irrespective of VPFI
for the write protect time (tREC), which is the time
from VPFD(max) until the inputs are recognized. At
the end of this time, the power-fail comparator is
enabled and PFO follows PFI. If the comparator is
unused, PFI should be connected to VSS and PFO
left unconnected.
Century Bit
Bits D7 and D6 of Clock Register 03h contain the
CENTURY ENABLE Bit (CEB) and the CENTURY
Bit (CB). Setting CEB to a '1' will cause CB to toggle, either from a '0' to '1' or from '1' to '0' at the turn
of the century (depending upon its initial state). If
CEB is set to a '0,' CB will not toggle.
Output Driver Pin
When the FT Bit, AFE Bit and watchdog register
are not set, the IRQ/FT/OUT pin becomes an output driver that reflects the contents of D7 of the
Control Register. In other words, when D7 (OUT
Bit) and D6 (FT Bit) of address location 08h are a
'0,' then the IRQ/FT/OUT pin will be driven low.
Note: The IRQ/FT/OUT pin is an open drain which
requires an external pull-up resistor.
Battery Low Warning
The M41ST85Y/W automatically performs battery
voltage monitoring upon power-up and at factoryprogrammed time intervals of approximately 24
hours. The Battery Low (BL) Bit, Bit D4 of Flags
Register 0Fh, will be asserted if the battery voltage
is found to be less than approximately 2.5V. The
24/33
BL Bit will remain asserted until completion of battery replacement and subsequent battery low
monitoring tests, either during the next power-up
sequence or the next scheduled 24-hour interval.
If a battery low is generated during a power-up sequence, this indicates that the battery is below approximately 2.5 volts and may not be able to
maintain data integrity in the SRAM. Data should
be considered suspect and verified as correct. A
fresh battery should be installed.
If a battery low indication is generated during the
24-hour interval check, this indicates that the battery is near end of life. However, data is not compromised due to the fact that a nominal VCC is
supplied. In order to insure data integrity during
subsequent periods of battery back-up mode, the
battery should be replaced. The SNAPHAT top
may be replaced while VCC is applied to the device.
Note: This will cause the clock to lose time during
the interval the SNAPHAT battery/crystal top is
disconnected.
The M41ST85Y/W only monitors the battery when
a nominal VCC is applied to the device. Thus applications which require extensive durations in the
battery back-up mode should be powered-up periodically (at least once every few months) in order
for this technique to be beneficial. Additionally, if a
battery low is indicated, data integrity should be
verified upon power-up via a checksum or other
technique.
tREC Bit
Bit D7 of Clock Register 04h contains the tREC Bit
(TR). tREC refers to the automatic continuation of
the deselect time after VCC reaches VPFD. This allows for a voltage settling time before WRITEs
may again be performed to the device after a power-down condition. The tREC Bit will allow the user
to set the length of this deselect time as defined by
Table 12, page 25.
Initial Power-on Defaults
Upon initial application of power to the device, the
following register bits are set to a '0' state: Watchdog Register, FT, AFE, ABE, SQWE, and TR. The
following bits are set to a '1' state: ST, OUT, and
HT (see Table 13, page 25).
M41ST85Y, M41ST85W
Table 12. t REC Definitions
tREC Bit (TR)
tREC Time
STOP Bit (ST)
Units
Min
Max
0
0
96
98
ms
0
1
40
200(1)
ms
1
X
50
2000
µs
Note: 1. Default Setting
Table 13. Default Values
Condition
Initial Power-up(2)
Subsequent Power-up (with
battery back-up)(3)
TR
ST
HT
Out
FT
AFE
ABE
SQWE
WATCHDOG
Register(1)
0
1
1
1
0
0
0
0
0
UC
UC
1
UC
0
0
0
0
0
Note: 1. WDS, BMB0-BMB4, RB0, RB1.
2. State of other control bits undefined.
3. UC = Unchanged
25/33
M41ST85Y, M41ST85W
Figure 21. Crystal Accuracy Across Temperature
Frequency (ppm)
20
0
–20
–40
–60
–80
–100
∆F = -0.038 ppm (T - T )2 ± 10%
0
F
C2
–120
T0 = 25 °C
–140
–160
–40
–30
–20
–10
0
10
20
30
40
50
60
70
80
Temperature °C
AI00999
Figure 22. Calibration Waveform
NORMAL
POSITIVE
CALIBRATION
NEGATIVE
CALIBRATION
AI00594B
26/33
M41ST85Y, M41ST85W
PART NUMBERING
Table 14. Ordering Information Scheme
Example:
M41ST
85Y
MH
6
TR
Device Type
M41ST
Supply Voltage and Write Protect Voltage
85Y = VCC = 4.5 to 5.5V; 4.20V ≤ VPFD ≤ 4.50V
85W = VCC = 2.7 to 3.6V; 2.55V ≤ VPFD ≤ 2.70V
Package
MH(1) = SOH28
MX(2) = SOX28
Temperature Range
6 = –40 to 85°C
Shipping Method for SOIC
blank = Tubes
TR = Tape & Reel
Note: 1. The 28-pin SOIC package (SOH28) requires the battery/crystal package (SNAPHAT®) which is ordered separately under the part
number “M4TXX-BR12SHX” in plastic tube or “M4TXX-BR12SHXTR” in Tape & Reel form.
2. The SOX28 package includes an embedded 32,768Hz crystal.
Caution: Do not place the SNAPHAT battery package “M4TXX-BR12SH” in conductive foam as it will drain the lithium button-cell battery.
For a list of available options (e.g., Speed, Package) or for further information on any aspect of this device,
please contact the ST Sales Office nearest to you.
Table 15. SNAPHAT Battery Table
Part Number
Description
Package
M4T28-BR12SH
Lithium Battery (48mAh) and Crystal SNAPHAT
SH
M4T32-BR12SH
Lithium Battery (120mAh) and Crystal SNAPHAT
SH
27/33
M41ST85Y, M41ST85W
PACKAGE MECHANICAL INFORMATION
Figure 23. SOH28 – 28-lead Plastic Small Outline, Battery SNAPHAT, Package Outline
A2
A
C
B
eB
e
CP
D
N
E
H
A1
α
L
1
SOH-A
Note: Drawing is not to scale.
Table 16. SOH28 – 28-lead Plastic Small Outline, battery SNAPHAT, Package Mechanical Data
Symbol
millimeters
Typ
Min
A
Max
Typ
Min
3.05
Max
0.120
A1
0.05
0.36
0.002
0.014
A2
2.34
2.69
0.092
0.106
B
0.36
0.51
0.014
0.020
C
0.15
0.32
0.006
0.012
D
17.71
18.49
0.697
0.728
E
8.23
8.89
0.324
0.350
–
–
–
–
eB
3.20
3.61
0.126
0.142
H
11.51
12.70
0.453
0.500
L
0.41
1.27
0.016
0.050
α
0°
8°
0°
8°
N
28
e
CP
28/33
inches
1.27
0.050
28
0.10
0.004
M41ST85Y, M41ST85W
Figure 24. SH – 4-pin SNAPHAT Housing for 48mAh Battery & Crystal, Package Outline
A1
A2
A
eA
A3
B
L
eB
D
E
SHTK-A
Note: Drawing is not to scale.
Table 17. SH – 4-pin SNAPHAT Housing for 48mAh Battery & Crystal, Package Mechanical Data
Symbol
millimeters
Typ
Min
A
inches
Max
Typ
Min
9.78
Max
0.3850
A1
6.73
7.24
0.2650
0.2850
A2
6.48
6.99
0.2551
0.2752
A3
0.38
0.0150
B
0.46
0.56
0.0181
0.0220
D
21.21
21.84
0.8350
0.8598
E
14.22
14.99
0.5598
0.5902
eA
15.55
15.95
0.6122
0.6280
eB
3.20
3.61
0.1260
0.1421
L
2.03
2.29
0.0799
0.0902
29/33
M41ST85Y, M41ST85W
Figure 25. SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Package Outline
A1
A2
A
eA
A3
B
L
eB
D
E
SHTK-A
Note: Drawing is not to scale.
Table 18. SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Package Mechanical Data
Symbol
millimeters
Typ
Min
A
Max
Typ
Min
10.54
Max
0.4150
A1
6.73
7.24
0.2650
0.2850
A2
6.48
6.99
0.2551
0.2752
A3
30/33
inches
0.38
0.0150
B
0.46
0.56
0.0181
0.0220
D
21.21
21.84
0.8350
0.8598
E
14.22
14.99
0.5598
0.5902
eA
15.55
15.95
0.6122
0.6280
eB
3.20
3.61
0.1260
0.1421
L
2.03
2.29
0.0799
0.0902
M41ST85Y, M41ST85W
Figure 26. SOX28 – 28-lead Plastic Small Outline, 300mils, Embedded Crystal, Package Outline
D
14
h x 45û
1
C
E
15
H
28
A2
A
B
ddd
A1
e
A1
α
L
SO-E
Note: Drawing is not to scale.
Table 19. SOX28 – 28-lead Plastic Small Outline, 300mils, Embedded Crystal, Package Mechanical
Symbol
millimeters
Typ
inches
Min
Max
A
2.44
A1
Min
Max
2.69
0.096
0.106
0.15
0.31
0.006
0.012
A2
2.29
2.39
0.090
0.094
B
0.41
0.51
0.016
0.020
C
0.20
0.31
0.008
0.012
D
17.91
18.01
0.705
0.709
ddd
0.10
E
e
Typ
7.57
1.27
0.004
7.67
0.298
0.050
0.302
–
–
–
–
H
10.16
10.52
0.400
0.414
L
0.51
0.81
0.020
0.032
α
0°
8°
0°
8°
N
28
28
31/33
M41ST85Y, M41ST85W
REVISION HISTORY
Table 20. Document Revision History
Date
Rev. #
August 2000
1.0
First issue
24-Aug-00
1.1
Block Diagram added (Figure 3)
12-Oct-00
1.2
tREC Table removed, cross references corrected
18-Dec-00
2.0
Reformatted, TOC added, and PFI Input Leakage Current added (Table 5)
18-Jun-01
2.1
Addition of tREC information, table changed, one added (Tables 8, 12); changed PFI/PFO
graphic (see Figure 6); change to DC and AC Characteristics, Order Information (Tables 5,
6, 14); note added to “Setting Alarm Clock Registers” section; added temp./voltage info. to
tables (Table 4, 5, 6, 6, 7); addition of Default Values (Table 13)
22-Jun-01
2.2
Note added to Clock Operation section
26-Jul-01
3.0
Change in Product Maturity
07-Aug-01
3.1
Improve text in “Setting the Alarm Clock” section
20-Aug-01
3.2
Change VPFD values in document
06-Sep-01
3.3
DC Characteristics VBAT changed; VOHB changed; PFI Hysteresis (PFI Rising) spec.
added; and Crystal Electrical Characteristics table removed (Tables 5, 6)
03-Dec-01
3.4
Changed READ/WRITE Mode Sequences (Figure 14, 16); change in VPFD lower limit for
5V (M41ST85Y) part only (Table 5, 14)
01-May-02
3.5
Change tREC Definition (Table 12); modify reflow time and temperature footnote (Table 2)
03-Jul-02
3.6
Modify DC Characteristics table footnote, Default Values (Tables 5, 13)
15-Nov-02
3.7
Added embedded crystal (MX) package option; corrected initial power-up condition (Figure
2, 3, 5, 6, 7, 26, Table 1, 13, 14, 19)
24-Jan-03
3.8
Update diagrams (Figure 6, 7, 26); update values (Table 7, 11, 12, 13, 19)
25-Feb-03
4.0
New Si changes (Table 7, 11, 12); corrected dimensions (Figure 26; Table 19)
32/33
Revision Details
M41ST85Y, M41ST85W
M41ST85, M41ST85Y, M41ST85W, 41ST85, ST85, SUPERVISOR, SUPERVISOR, SUPERVISOR, SUPERVISOR, SUPERVISOR, SUPERVISOR, SUPERVISOR, SUPERVISOR, SUPERVISOR, SUPERVISOR, SUPERVISOR, SUPERVISOR, SUPERVISOR, SUPERVISOR, SUPERVISOR, SUPERVISOR, SUPERVISOR, SUPERVISOR, SUPERVISOR, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial,
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Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low,
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Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low,
Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low,
Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low,
Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low,
Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low,
Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low,
Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low,
Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low,
Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low,
Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Low, Battery, Battery, Battery, Battery,
Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery,
Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery,
Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Switchover, Switchover, Switchover, Switchover, Switchover, Switchover, Switchover, Switchover, Switchover,
Switchover, Switchover, Switchover, Switchover, Switchover, Switchover, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Power-fail, Power-fail, Power-fail, Power-fail, Power-fail, Power-fail, Power-fail, Power-fail, Power-fail, Power-fail, Power-fail,
Power-fail, Power-fail, Power-fail, Power-fail, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator,
Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, Comparator, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT,
SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT,
SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT, SNAPHAT,
SNAPHAT, SNAPHAT, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V,
5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 3V, 3V, 3V, 3V, 3V, 3V, 3V, 3V, 3V, 3V, 3V, 3V, 3V, 3V, 3V, 3V, 3V, 3V, 3V,
3V, 3V, 3V, 3V, 3V, 3V
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