STMICROELECTRONICS M41T81SMY6F

M41T81S
Serial Access Real-Time Clock with Alarms
FEATURES SUMMARY
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COUNTERS FOR TENTHS/HUNDREDTHS
OF SECONDS, SECONDS, MINUTES,
HOURS, DAY, DATE, MONTH, YEAR, AND
CENTURY
32KHz CRYSTAL OSCILLATOR WITH
INTEGRATED LOAD CAPACITANCE
(12.5pF) WHICH PROVIDES EXCEPTIONAL
OSCILLATOR STABILITY AND HIGH
CRYSTAL SERIES RESISTANCE
OPERATION)
OSCILLATOR STOP DETECTION
(MONITORS CLOCK OPERATION)
SERIAL INTERFACE SUPPORTS I2C BUS
(400kHz PROTOCOL)
ULTRA-LOW BATTERY SUPPLY CURRENT
OF 0.6µA (typ)
2.0 TO 5.5V CLOCK OPERATING VOLTAGE
AUTOMATIC SWITCHOVER AND
DESELECT CIRCUITRY (FIXED
REFERENCE) WHICH PROVIDES FULL
OPERATION IN 3.0V APPLICATIONS)
– VCC = 2.7 to 5.5V
2.5V ≤ VPFD ≤ 2.7V
POWER-DOWN TIME STAMP (HT BIT)
WHICH ALLOWS DETERMINATION OF
TIME ELAPSED IN BATTERY BACK-UP
BATTERY LOW FLAG
PROGRAMMABLE ALARM AND
INTERRUPT FUNCTION (valid even during
Battery Back-up Mode)
ACCURATE PROGRAMMABLE
WATCHDOG TIMER (from 62.5ms to 128s)
SOFTWARE CLOCK CALIBRATION (TO
COMPENSATE FOR CRYSTAL DEVIATION
DUE TO TEMPERATURE)
OPERATING TEMPERATURE OF –40 TO
85°C
PACKAGE OPTIONS INCLUDE AN 8-LEAD
SOIC OR 18-LEAD EMBEDDED CRYSTAL
SOIC
Figure 1. Packages
8
1
SO8 (M)
8-pin SOIC
18
1
SOX18 (MY)*
18-pin (300mil) SOIC
with Embedded Crystal
* Contact local ST sales office for availability.
Rev 4.0
September 2005
1/29
M41T81S
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 1. Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 2.
Table 1.
Figure 3.
Figure 4.
Figure 5.
Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
8-pin SOIC (M) Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
18-pin, 300mil SOIC (MY) Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2-Wire Bus Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 6. Serial Bus Data Transfer Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 7. Acknowledgement Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
READ Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 8. Slave Address Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 9. READ Mode Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 10.Alternative READ Mode Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
WRITE Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Data Retention Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 11.WRITE Mode Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
CLOCK OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Power-down Timestamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
TIMEKEEPER® Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 2. TIMEKEEPER® Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Calibrating the Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 12.Crystal Accuracy Across Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 13.Clock Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Setting Alarm Clock Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 14.Alarm Interrupt Reset Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 15.Back-up Mode Alarm Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 3. Alarm Repeat Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Square Wave Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 4. Square Wave Output Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Century Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Battery Low Warning. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Oscillator Fail Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Oscillator Fail Interrupt Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Output Driver Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Preferred Initial Power-on Default . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 5. Preferred Default Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
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M41T81S
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 6. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 7. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 16.AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 8. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 9. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 10. Crystal Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 17.Power Down/Up Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 11. Power Down/Up AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 12. Power Down/Up Trip Points DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 18.Bus Timing Requirements Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 13. AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 19.SO8 – 8-lead Plastic Small Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 14. SO8 – 8-lead Plastic Small Outline (150 mils body width), Package Mech. Data . . . . . . 25
Figure 20.SOX18 – 18-lead Plastic Small Outline, 300mils, Embedded Crystal, Outline . . . . . . . . 26
Table 15. SOX18 – 18-lead Plastic Small Outline, 300mils, Embedded Crystal, Package Mech. . 26
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 16. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 17. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3/29
M41T81S
SUMMARY DESCRIPTION
The M41T81S Serial Access TIMEKEEPER ®
SRAM is a low power Serial RTC with a built-in
32.768kHz oscillator (external crystal controlled).
Eight bytes of the SRAM (see Table 2., page 12)
are used for the clock/calendar function and are
configured in binary coded decimal (BCD) format.
An additional 12 bytes of SRAM provide status/
control of Alarm, Watchdog and Square Wave
functions. Addresses and data are transferred serially via a two line, bi-directional I2C interface. The
built-in address register is incremented automatically after each WRITE or READ data byte.
The M41T81S has a built-in power sense circuit
which detects power failures and automatically
switches to the battery supply when a power failure occurs. The energy needed to sustain the
clock operations can be supplied by a small lithium
button supply when a power failure occurs. Functions available to the user include a non-volatile,
time-of-day clock/calendar, Alarm interrupts,
Watchdog Timer and programmable Square
Wave output. The eight clock address locations
contain the century, year, month, date, day, hour,
minute, second and tenths/hundredths of a second in 24 hour BCD format. Corrections for 28, 29
(leap year - valid until year 2100), 30 and 31 day
months are made automatically.
The M41T81S is supplied in either an 8-pin SOIC
or an 18-pin (MY), 300mil SOIC package which includes an embedded 32kHz crystal.
The 18-pin, embedded crystal SOIC requires only
a user-supplied battery to provide non-volatile operation.
Figure 2. Logic Diagram
Table 1. Signal Names
VCC VBAT
XI(1)
Oscillator Input
XO(1)
Oscillator Output
IRQ/OUT/
FT/SQW
Interrupt / Output Driver / Frequency
Test / Square Wave (Open Drain)
(1)
XI
XO(1)
M41T81S
IRQ/FT/OUT/SQW
SCL
SDA
VSS
AI09160
Note: 1. For SO8 package only.
4/29
SDA
Serial Data Input/Output
SCL
Serial Clock Input
VBAT
Battery Supply Voltage
VCC
Supply Voltage
VSS
Ground
NC(2)
No Connect
NF(2)
No Function
Note: 1. For SO8 package only.
2. NC and NF pins should be tied to VSS.
M41T81S
Figure 3. 8-pin SOIC (M) Connections
XI
XO
VBAT
VSS
1
8
7
2
3 M41T81S 6
4
5
VCC
IRQ/FT/OUT/SQW(1)
SCL
SDA
AI09161
Figure 4. 18-pin, 300mil SOIC (MY)
Connections
NC
NF(1)
NF(1)
NC
NC
NC
NC
VBAT
VSS
1
18
17
2
16
3
15
4
5 M41T81S 14
13
6
12
7
11
8
10
9
NC
NF(1)
NF(1)
VCC
NC
IRQ/FT/OUT/SQW(2)
NC
SCL
SDA
AI09162
Note: 1. NC and NF pins should be tied to VSS. Pins 2 and 3 are
internally shorted together. Pins 17 and 16 are internally
shorted together.
2. Open Drain Output
Note: 1. Open Drain Output
Figure 5. Block Diagram
REAL TIME CLOCK
CALENDAR
OSCILLATOR FAIL OFIE
CIRCUIT
32KHz
OSCILLATOR
CRYSTAL
AFE
RTC W/ALARM
& CALIBRATION
(1)
WATCHDOG
SDA
IRQ/FT/OUT/SQW
2
I C
INTERFACE
SCL
WRITE
PROTECT
SQWE(2)
SQUARE WAVE
FREQUENCY TEST FT
OUTPUT DRIVER
OUT
INTERNAL
POWER
VCC
VBAT
VSO
COMPARE
VPFD
AI09163
Note: 1. Open Drain Output
2. Square Wave function has the highest priority on IRQ/FT/OUT/SQW output.
5/29
M41T81S
OPERATION
The M41T81S clock operates as a slave device on
the serial bus. Access is obtained by implementing
a start condition followed by the correct slave address (D0h). The 20 bytes contained in the device
can then be accessed sequentially in the following
order:
1. Tenths/Hundredths of a Second Register
2. Seconds Register
3. Minutes Register
4. Century/Hours Register
5. Day Register
6. Date Register
7. Month Register
8. Year Register
9. Calibration Register
10. Watchdog Register
11 - 15. Alarm Registers
16. Flags Register
17 - 19. Reserved
20. Square Wave Register
The M41T81S clock continually monitors VCC for
an out-of-tolerance condition. Should VCC fall below VPFD, the device terminates an access in
progress and resets the device address counter.
Inputs to the device will not be recognized at this
time to prevent erroneous data from being written
to the device from a an out-of-tolerance system.
Once VCC falls below the switchover voltage
(VSO ), the device automatically switches over to
the battery and powers down into an ultra-low current mode of operation to preserve battery life. If
VBAT is less than VPFD, the device power is
switched from VCC to VBAT when VCC drops below
VBAT. If VBAT is greater than VPFD, the device
power is switched from VCC to VBAT when VCC
drops below VPFD. Upon power-up, the device
switches from battery to VCC at VSO. When VCC
rises above VPFD, it will recognize the inputs.
For more information on Battery Storage Life refer
to Application Note AN1012.
2-Wire Bus Characteristics
The bus is intended for communication between
different ICs. It consists of two lines: a bi-directional data signal (SDA) and a clock signal (SCL).
Both the SDA and SCL lines must be connected to
a positive supply voltage via a pull-up resistor.
The following protocol has been defined:
– Data transfer may be initiated only when the
bus is not busy.
6/29
–
During data transfer, the data line must remain
stable whenever the clock line is High.
– Changes in the data line, while the clock line is
High, will be interpreted as control signals.
Accordingly, the following bus conditions have
been defined:
Bus not busy. Both data and clock lines remain
High.
Start data transfer. A change in the state of the
data line, from high to Low, while the clock is High,
defines the START condition.
Stop data transfer. A change in the state of the
data line, from Low to High, while the clock is High,
defines the STOP condition.
Data Valid. The state of the data line represents
valid data when after a start condition, the data line
is stable for the duration of the high period of the
clock signal. The data on the line may be changed
during the Low period of the clock signal. There is
one clock pulse per bit of data.
Each data transfer is initiated with a start condition
and terminated with a stop condition. The number
of data bytes transferred between the start and
stop conditions is not limited. The information is
transmitted byte-wide and each receiver acknowledges with a ninth bit.
By definition a device that gives out a message is
called “transmitter,” the receiving device that gets
the message is called “receiver.” The device that
controls the message is called “master.” The devices that are controlled by the master are called
“slaves.”
Acknowledge. Each byte of eight bits is followed
by one Acknowledge Bit. This Acknowledge Bit is
a low level put on the bus by the receiver whereas
the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed is obliged to generate an acknowledge
after the reception of each byte that has been
clocked out of the slave transmitter.
The device that acknowledges has to pull down
the SDA line during the acknowledge clock pulse
in such a way that the SDA line is a stable Low during the High period of the acknowledge related
clock pulse. Of course, setup and hold times must
be taken into account. A master receiver must signal an end of data to the slave transmitter by not
generating an acknowledge on the last byte that
has been clocked out of the slave. In this case the
transmitter must leave the data line High to enable
the master to generate the STOP condition.
M41T81S
Figure 6. Serial Bus Data Transfer Sequence
DATA LINE
STABLE
DATA VALID
CLOCK
DATA
START
CONDITION
CHANGE OF
DATA ALLOWED
STOP
CONDITION
AI00587
Figure 7. Acknowledgement Sequence
CLOCK PULSE FOR
ACKNOWLEDGEMENT
START
SCL FROM
MASTER
DATA OUTPUT
BY TRANSMITTER
1
MSB
2
8
9
LSB
DATA OUTPUT
BY RECEIVER
AI00601
7/29
M41T81S
READ Mode
In this mode the master reads the M41T81S slave
after setting the slave address (see Figure
9., page 9). Following the WRITE Mode Control
Bit (R/W=0) and the Acknowledge Bit, the word
address 'An' is written to the on-chip address
pointer. Next the START condition and slave address are repeated followed by the READ Mode
Control Bit (R/W=1). At this point the master transmitter becomes the master receiver. The data byte
which was addressed will be transmitted and the
master receiver will send an Acknowledge Bit to
the slave transmitter. The address pointer is only
incremented on reception of an Acknowledge
Clock. The M41T81S slave transmitter will now
place the data byte at address An+1 on the bus,
the master receiver reads and acknowledges the
new byte and the address pointer is incremented
to “An+2.”
This cycle of reading consecutive addresses will
continue until the master receiver sends a STOP
condition to the slave transmitter.
The system-to-user transfer of clock data will be
halted whenever the address being read is a clock
address (00h to 07h). The update will resume due
to a Stop Condition or when the pointer increments
to any non-clock address (08h-13h).
Note: This is true both in READ Mode and WRITE
Mode.
An alternate READ Mode may also be implemented whereby the master reads the M41T81S slave
without first writing to the (volatile) address pointer. The first address that is read is the last one
stored in the pointer (see Figure 10., page 9).
Figure 8. Slave Address Location
R/W
START
A
1
LSB
MSB
SLAVE ADDRESS
1
0
1
0
0
0
AI00602
8/29
M41T81S
SLAVE
ADDRESS
DATA n+1
ACK
DATA n
ACK
S
ACK
BUS ACTIVITY:
R/W
START
WORD
ADDRESS (An)
ACK
S
R/W
SDA LINE
ACK
BUS ACTIVITY:
MASTER
START
Figure 9. READ Mode Sequence
STOP
SLAVE
ADDRESS
DATA n+X
P
NO ACK
AI00899
STOP
R/W
SLAVE
ADDRESS
DATA n+X
P
NO ACK
BUS ACTIVITY:
DATA n+1
ACK
DATA n
ACK
S
ACK
SDA LINE
ACK
BUS ACTIVITY:
MASTER
START
Figure 10. Alternative READ Mode Sequence
AI00895
9/29
M41T81S
WRITE Mode
In this mode the master transmitter transmits to
the M41T81S slave receiver. Bus protocol is
shown in Figure 11., page 10. Following the
START condition and slave address, a logic '0' (R/
W=0) is placed on the bus and indicates to the addressed device that word address “An” will follow
and is to be written to the on-chip address pointer.
The data word to be written to the memory is
strobed in next and the internal address pointer is
incremented to the next address location on the
reception of an acknowledge clock. The M41T81S
slave receiver will send an acknowledge clock to
the master transmitter after it has received the
slave address see Figure 8., page 8 and again after it has received the word address and each data
byte.
Data Retention Mode
With valid VCC applied, the M41T81S can be accessed as described above with READ or WRITE
Cycles. Should the supply voltage decay, the power input will be switched from the VCC pin to the
battery when VCC falls below the Battery Back-up
Switchover Voltage (VSO). At this time the clock
registers will be maintained by the attached battery supply. On power-up, when VCC returns to a
nominal value, write protection continues for tREC.
For a further, more detailed review of lifetime calculations, please see Application Note AN1012.
SLAVE
ADDRESS
10/29
STOP
DATA n+X
P
ACK
DATA n+1
ACK
BUS ACTIVITY:
DATA n
ACK
WORD
ADDRESS (An)
ACK
S
R/W
SDA LINE
ACK
BUS ACTIVITY:
MASTER
START
Figure 11. WRITE Mode Sequence
AI00591
M41T81S
CLOCK OPERATION
The 20-byte Register Map (see Table 2., page 12)
is used to both set the clock and to read the date
and time from the clock, in a binary coded decimal
format. Tenths/Hundredths of Seconds, Seconds,
Minutes, and Hours are contained within the first
four registers.
Note: Tenths/Hundredths of Seconds cannot be
written to any value other than “00.”
Bits D6 and D7 of Clock Register 03h (Century/
Hours Register) contain the CENTURY ENABLE
Bit (CEB) and the CENTURY Bit (CB). Setting
CEB to a '1' will cause CB to toggle, either from '0'
to '1' or from '1' to '0' at the turn of the century (depending upon its initial state). If CEB is set to a '0,'
CB will not toggle. Bits D0 through D2 of Register
04h contain the Day (day of week). Registers 05h,
06h, and 07h contain the Date (day of month),
Month and Years. The ninth clock register is the
Calibration Register (this is described in the Clock
Calibration section). Bit D7 of Register 01h contains the STOP Bit (ST). Setting this bit to a '1' will
cause the oscillator to stop. If the device is expected to spend a significant amount of time on the
shelf, the oscillator may be stopped to reduce current drain. When reset to a '0' the oscillator restarts
within one second.
The eight Clock Registers may be read one byte at
a time, or in a sequential block. Provision has been
made to assure that a clock update does not occur
while any of the eight clock addresses are being
read. If a clock address is being read, an update of
the clock registers will be halted. This will prevent
a transition of data during the READ.
Power-down Timestamp
When a power failure occurs, the HALT (HT) Bit
will automatically be set to a '1.' This will prevent
the clock from updating the TIMEKEEPER® registers, and will allow the user to read the exact time
of the power-down event. Resetting the HT Bit to
a '0' will allow the clock to update the TIMEKEEPER registers with the current time.
TIMEKEEPER ® Registers
The M41T81S offers 20 internal registers which
contain Clock, Alarm, Watchdog, Flags, Square
Wave and Calibration data. These registers are
memory locations which contain external (user accessible) and internal copies of the data (usually
referred to as BiPORT™ TIMEKEEPER cells). The
external copies are independent of internal functions except that they are updated periodically by
the simultaneous transfer of the incremented internal copy. The internal divider (or clock) chain will
be reset upon the completion of a WRITE to any
clock address.
The system-to-user transfer of clock data will be
halted whenever the address being read is a clock
address (00h to 07h). The update will resume either due to a Stop Condition or when the pointer
increments to any non-clock address (08h-13h).
TIMEKEEPER and Alarm Registers store data in
BCD. Calibration, Watchdog and Square Wave
Registers store data in Binary Format.
11/29
M41T81S
Table 2. TIMEKEEPER® Register Map
Addr
D7
00h
D6
D5
D4
D3
0.1 Seconds
D2
D1
D0
Function/Range BCD
Format
0.01 Seconds
Seconds
00-99
01h
ST
10 Seconds
Seconds
Seconds
00-59
02h
0
10 Minutes
Minutes
Minutes
00-59
03h
CEB
CB
Hours (24 Hour Format)
Century/
Hours
0-1/00-23
04h
0
0
Day
01-7
05h
0
0
Date: Day of Month
Date
01-31
06h
0
0
Month
Month
01-12
Year
Year
00-99
07h
10 Hours
0
0
0
10 Date
0
Day of Week
10M
10 Years
08h
OUT
FT
S
Calibration
09h
OFIE
BMB4
BMB3
BMB2
0Ah
AFE
SQWE
ABE
Al 10M
0Bh
RPT4
RPT5
0Ch
RPT3
HT
0Dh
RPT2
0Eh
RPT1
0Fh
WDF
AF
0
BL
0
OF
0
0
Flags
10h
0
0
0
0
0
0
0
0
Reserved
11h
0
0
0
0
0
0
0
0
Reserved
12h
0
0
0
0
0
0
0
0
Reserved
13h
RS3
RS2
RS1
RS0
0
0
0
0
SQW
BMB0
RB1
RB0
Watchdog
Alarm Month
Al Month
01-12
AI 10 Date
Alarm Date
Al Date
01-31
AI 10 Hour
Alarm Hour
Al Hour
00-23
Alarm 10 Minutes
Alarm Minutes
Al Min
00-59
Alarm 10 Seconds
Alarm Seconds
Al Sec
00-59
Keys: 0 = Must be set to '0'
ABE = Alarm in Battery Back-up Mode Enable Bit
AF = Alarm Flag (Read only)
AFE = Alarm Flag Enable Flag
BL = Battery Low Bit
BMB0-BMB4 = Watchdog Multiplier Bits
CB = Century Bit
CEB = Century Enable Bit
FT = Frequency Test Bit
HT = Halt Update Bit
12/29
BMB1
Calibration
OF = Oscillator Fail Flag
OFIE = Oscillator Fail Interrupt Enable
OUT = Output level
RB0-RB1 = Watchdog Resolution Bits
RPT1-RPT5 = Alarm Repeat Mode Bits
RS0-RS3 = SQW Frequency
S = Sign Bit
SQWE = Square Wave Enable
ST = Stop Bit
WDF = Watchdog Flag (Read only)
M41T81S
Calibrating the Clock
The M41T81S is driven by a quartz controlled oscillator with a nominal frequency of 32,768Hz. The
devices are tested not exceed ±35 ppm (parts per
million) oscillator frequency error at 25oC, which
equates to about +1.9 to –1.1 minutes per month
(see Figure 12., page 14). When the Calibration
circuit is properly employed, accuracy improves to
better than ±2 ppm at 25°C.
The oscillation rate of crystals changes with temperature. The M41T81S design employs periodic
counter correction. The calibration circuit adds or
subtracts counts from the oscillator divider circuit
at the divide by 256 stage, as shown in Figure
13., page 14. The number of times pulses which
are blanked (subtracted, negative calibration) or
split (added, positive calibration) depends upon
the value loaded into the five Calibration Bits found
in the Calibration Register. Adding counts speeds
the clock up, subtracting counts slows the clock
down.
The Calibration Bits occupy the five lower order
bits (D4-D0) in the Calibration Register 08h. These
bits can be set to represent any value between 0
and 31 in binary form. Bit D5 is a Sign Bit; '1' indicates positive calibration, '0' indicates negative
calibration. Calibration occurs within a 64 minute
cycle. The first 62 minutes in the cycle may, once
per minute, have one second either shortened by
128 or lengthened by 256 oscillator cycles. If a binary '1' is loaded into the register, only the first 2
minutes in the 64 minute cycle will be modified; if
a binary 6 is loaded, the first 12 will be affected,
and so on.
Therefore, each calibration step has the effect of
adding 512 or subtracting 256 oscillator cycles for
every 125,829,120 actual oscillator cycles, that is
+4.068 or –2.034 ppm of adjustment per calibration step in the calibration register (see Figure
13., page 14). Assuming that the oscillator is running at exactly 32,768Hz, each of the 31 increments in the Calibration byte would represent
+10.7 or –5.35 seconds per month which corresponds to a total range of +5.5 or –2.75 minutes
per month.
Two methods are available for ascertaining how
much calibration a given M41T81S may require.
The first involves setting the clock, letting it run for
a month and comparing it to a known accurate reference and recording deviation over a fixed period
of time. Calibration values, including the number of
seconds lost or gained in a given period, can be
found in Application Note AN934, “TIMEKEEPER ® CALIBRATION.” This allows the designer to
give the end user the ability to calibrate the clock
as the environment requires, even if the final product is packaged in a non-user serviceable enclosure. The designer could provide a simple utility
that accesses the Calibration byte.
The second approach is better suited to a manufacturing environment, and involves the use of the
IRQ/FT/OUT/SQW pin. The pin will toggle at
512Hz, when the Stop Bit (ST, D7 of 01h) is '0,' the
Frequency Test Bit (FT, D6 of 08h) is '1,' the Alarm
Flag Enable Bit (AFE, D7 of 0Ah) is '0,' and the
Square Wave Enable Bit (SQWE, D6 of 0Ah) is '0'
and the Watchdog Register (09h = 0) is reset.
Any deviation from 512Hz indicates the degree
and direction of oscillator frequency shift at the test
temperature. For example, a reading of
512.010124Hz would indicate a +20 ppm oscillator
frequency error, requiring a –10 (XX001010) to be
loaded into the Calibration Byte for correction.
Note that setting or changing the Calibration Byte
does not affect the Frequency Test output frequency.
The IRQ/FT/OUT/SQW pin is an open drain output
which requires a pull-up resistor to VCC for proper
operation. A 500-10k resistor is recommended in
order to control the rise time. The FT Bit is cleared
on power-down.
13/29
M41T81S
Figure 12. Crystal Accuracy Across Temperature
Frequency (ppm)
20
0
–20
–40
–60
∆F = K x (T – T )2
O
F
–80
2
2
K = –0.036 ppm/°C ± 0.006 ppm/°C
–100
TO = 25°C ± 5°C
–120
–140
–160
–40
–30
–20
–10
0
10
20
30
40
50
60
70
80
Temperature °C
AI07888
Figure 13. Clock Calibration
NORMAL
POSITIVE
CALIBRATION
NEGATIVE
CALIBRATION
AI00594B
14/29
M41T81S
Setting Alarm Clock Registers
Address locations 0Ah-0Eh contain the alarm settings. The alarm can be configured to go off at a
prescribed time on a specific month, date, hour,
minute, or second or repeat every year, month,
day, hour, minute, or second. It can also be programmed to go off while the M41T81S is in the
battery back-up mode to serve as a system wakeup call.
Bits RPT5-RPT1 put the alarm in the repeat mode
of operation. Table 3., page 16 shows the possible
configurations. Codes not listed in the table default
to the once per second mode to quickly alert the
user of an incorrect alarm setting.
When the clock information matches the alarm
clock settings based on the match criteria defined
by RPT5-RPT1, the AF (Alarm Flag) is set. If AFE
(Alarm Flag Enable) is also set (and SQWE is '0.'),
the alarm condition activates the IRQ/FT/OUT/
SQW pin.
Note: If the address pointer is allowed to increment to the Flags Register address, an alarm condition will not cause the Interrupt/Flag to occur until
the address pointer is moved to a different address. It should also be noted that if the last address written is the “Alarm Seconds,” the address
pointer will increment to the Flag address, causing
this situation to occur.
The IRQ/FT/OUT/SQW output is cleared by a
READ to the Flags Register as shown in Figure
14. A subsequent READ of the Flags Register is
necessary to see that the value of the Alarm Flag
has been reset to '0.'
The IRQ/FT/OUT/SQW pin can also be activated
in the battery back-up mode. The IRQ/FT/OUT/
SQW will go low if an alarm occurs and both ABE
(Alarm in Battery Back-up Mode Enable) and AFE
are set. Figure 15 illustrates the back-up mode
alarm timing.
Figure 14. Alarm Interrupt Reset Waveform
0Eh
0Fh
10h
ACTIVE FLAG
HIGH-Z
IRQ/FT/OUT/SQW
AI04617
Figure 15. Back-up Mode Alarm Waveform
VCC
VPFD
VSO
trec
ABE and AFE Bits
AF Bit in Flags
Register
IRQ/FT/OUT/SQW
HIGH-Z
AI09164b
15/29
M41T81S
Table 3. Alarm Repeat Modes
RPT5
RPT4
RPT3
RPT2
RPT1
Alarm Setting
1
1
1
1
1
Once per Second
1
1
1
1
0
Once per Minute
1
1
1
0
0
Once per Hour
1
1
0
0
0
Once per Day
1
0
0
0
0
Once per Month
0
0
0
0
0
Once per Year
Watchdog Timer
The watchdog timer can be used to detect an outof-control microprocessor. The user programs the
watchdog timer by setting the desired amount of
time-out into the Watchdog Register, address 09h.
Bits BMB4-BMB0 store a binary multiplier and the
two lower order bits RB1-RB0 select the resolution, where 00 = 1/16 second, 01 = 1/4 second,
10 = 1 second, and 11 = 4 seconds. The amount
of time-out is then determined to be the multiplication of the five-bit multiplier value with the resolution. (For example: writing 00001110 in the
Watchdog Register = 3*1, or 3 seconds). If the
processor does not reset the timer within the specified period, the M41T81S sets the WDF (Watchdog Flag) and generates a watchdog interrupt.
16/29
The watchdog timer can be reset by having the microprocessor perform a WRITE of the Watchdog
Register. The time-out period then starts over.
Should the watchdog timer time-out, a value of
00h needs to be written to the Watchdog Register
in order to clear the IRQ/FT/OUT/SQW pin. This
will also disable the watchdog function until it is
again programmed correctly. A READ of the Flags
Register will reset the Watchdog Flag (Bit D7;
Register 0Fh).
The watchdog function is automatically disabled
upon power-up and the Watchdog Register is
cleared. If the watchdog function is set, the frequency test function is activated, and the SQWE
Bit is '0,' the watchdog function prevails and the
frequency test function is denied.
M41T81S
Square Wave Output
The M41T81S offers the user a programmable
square wave function which is output on the SQW
pin. RS3-RS0 bits located in 13h establish the
square wave output frequency. These frequencies
are listed in Table 4. Once the selection of the
SQW frequency has been completed, the IRQ/FT/
OUT/SQW pin can be turned on and off under software control with the Square Wave Enable Bit
(SQWE) located in Register 0Ah.
Table 4. Square Wave Output Frequency
Square Wave Bits
Square Wave
RS3
RS2
RS1
RS0
Frequency
Units
0
0
0
0
None
-
0
0
0
1
32.768
kHz
0
0
1
0
8.192
kHz
0
0
1
1
4.096
kHz
0
1
0
0
2.048
kHz
0
1
0
1
1.024
kHz
0
1
1
0
512
Hz
0
1
1
1
256
Hz
1
0
0
0
128
Hz
1
0
0
1
64
Hz
1
0
1
0
32
Hz
1
0
1
1
16
Hz
1
1
0
0
8
Hz
1
1
0
1
4
Hz
1
1
1
0
2
Hz
1
1
1
1
1
Hz
17/29
M41T81S
Century Bit
Bits D7 and D6 of Clock Register 03h contain the
CENTURY ENABLE Bit (CEB) and the CENTURY
Bit (CB). Setting CEB to a '1' will cause CB to toggle, either from a '0' to '1' or from '1' to '0' at the turn
of the century (depending upon its initial state). If
CEB is set to a '0,' CB will not toggle.
Battery Low Warning
The M41T81S automatically performs battery voltage monitoring upon power-up and at factory-programmed time intervals of approximately 24
hours. The Battery Low (BL) Bit, Bit D4 of Flags
Register 0Fh, will be asserted if the battery voltage
is found to be less than approximately 2.5V. The
BL Bit will remain asserted until completion of battery replacement and subsequent battery low
monitoring tests, either during the next power-up
sequence or the next scheduled 24-hour interval.
If a battery low is generated during a power-up sequence, this indicates that the battery is below approximately 2.5 volts and may not be able to
maintain data integrity. Clock data should be considered suspect and verified as correct. A fresh
battery should be installed.
If a battery low indication is generated during the
24-hour interval check, this indicates that the battery is near end of life. However, data is not compromised due to the fact that a nominal VCC is
supplied. In order to insure data integrity during
subsequent periods of battery back-up mode, the
battery should be replaced.
The M41T81S only monitors the battery when a
nominal VCC is applied to the device. Thus applications which require extensive durations in the
battery back-up mode should be powered-up periodically (at least once every few months) in order
for this technique to be beneficial. Additionally, if a
battery low is indicated, data integrity should be
verified upon power-up via a checksum or other
technique.
Oscillator Fail Detection
If the Oscillator Fail Bit (OF) is internally set to '1,'
this indicates that the oscillator has either stopped,
or was stopped for some period of time and can be
used to judge the validity of the clock and date data.
In the event the OF Bit is found to be set to '1' at
any time other than the initial power-up, the STOP
Bit (ST) should be written to a '1,' then immediately
reset to '0.' This will restart the oscillator.
The following conditions can cause the OF Bit to
be set:
– The first time power is applied (defaults to a '1'
on power-up).
– The voltage present on VCC is insufficient to
support oscillation.
– The ST Bit is set to '1.'
– External interference of the crystal.
The OF Bit will remain set to '1' until written to logic
'0.' The oscillator must start and have run for at
least 4 seconds before attempting to reset the OF
Bit to '0.'
Oscillator Fail Interrupt Enable
If the Oscillator Fail Interrupt Bit (OFIE) is set to a
'1,' the IRQ pin will also be activated. The IRQ output is cleared by resetting the OFIE or OF Bit to '0'
(not be reading the Flags Register).
Output Driver Pin
When the FT Bit, AFE Bit, SQWE Bit, and Watchdog Register are not set, the IRQ/FT/OUT/SQW
pin becomes an output driver that reflects the contents of D7 of the Calibration Register. In other
words, when D7 (OUT Bit) and D6 (FT Bit) of address location 08h are a '0,' then the IRQ/FT/OUT/
SQW pin will be driven low.
Note: The IRQ/FT/OUT/SQW pin is an open drain
which requires an external pull-up resistor.
Preferred Initial Power-on Default
Upon initial application of power to the device, the
following register bits are set to a '0' state: Watchdog Register; AFE; ABE; SQWE; OFIE; and FT.
The following bits are set to a '1' state: ST; OUT;
OF; and HT (see Table 5., page 18).
Table 5. Preferred Default Values
Condition
Initial Power-up(2)
Subsequent Power-up
(with battery back-up)(3)
ST
HT
Out
FT
AFE
SQWE
ABE
WATCHDOG
Register(1)
OF
OFIE
1
1
1
0
0
0
0
0
1
0
UC
1
UC
0
UC
UC
UC
0
UC
UC
Note: 1. BMB0-BMB4, RB0, RB1.
2. State of other control bits undefined.
3. UC = Unchanged
18/29
M41T81S
MAXIMUM RATING
Stressing the device above the rating listed in the
“Absolute Maximum Ratings” table may cause
permanent damage to the device. These are
stress ratings only and operation of the device at
these or any other conditions above those indicated in the Operating sections of this specification is
not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device
reliability.
Refer
also
to
the
STMicroelectronics SURE Program and other relevant quality documents.
Table 6. Absolute Maximum Ratings
Sym
Parameter
TSTG
Storage Temperature (VCC Off, Oscillator Off)
VCC
Supply Voltage
TSLD
VIO
Lead Solder Temperature for 10 Seconds
Input or Output Voltages
IO
Output Current
PD
Power Dissipation
Value
Unit
–55 to 125
°C
–0.3 to 7
V
Lead-free lead finish(1)
260
°C
Standard (SnPb)
lead finish(2,3)
240
°C
–0.3 to Vcc+0.3
V
20
mA
1
W
SOIC
Note: 1. For SO8 package, Lead-free (Pb-free) lead finish: Reflow at peak temperature of 260°C (total thermal budget not to exceed 245°C
for greater than 30 seconds).
2. For SO8 package, standard (SnPb) lead finish: Reflow at peak temperature of 240°C (total thermal budget not to exceed 180°C for
between 90 to 150 seconds).
3. The SOX18 package has Lead-free (Pb-free) lead finish, but cannot be exposed to peak reflow temperature in excess of 240°C
(use same reflow profile as standard (SnPb) lead finish).
CAUTION: Negative undershoots below –0.3 volts are not allowed on any pin while in the Battery Back-up Mode
19/29
M41T81S
DC AND AC PARAMETERS
This section summarizes the operating and measurement conditions, as well as the DC and AC
characteristics of the device. The parameters in
the following DC and AC Characteristic tables are
derived from tests performed under the Measure-
ment Conditions listed in the relevant tables. Designers should check that the operating conditions
in their projects match the measurement conditions when using the quoted parameters.
Table 7. Operating and AC Measurement Conditions
Parameter
M41T81S
Supply Voltage (VCC)
2.7 to 5.5V
Ambient Operating Temperature (TA)
–40 to 85°C
Load Capacitance (CL)
100pF
Input Rise and Fall Times
≤ 50ns
Input Pulse Voltages
0.2VCC to 0.8 VCC
Input and Output Timing Ref. Voltages
0.3VCC to 0.7 VCC
Note: Output Hi-Z is defined as the point where data is no longer driven.
Figure 16. AC Measurement I/O Waveform
0.8VCC
0.7VCC
0.3VCC
0.2VCC
AI02568
Table 8. Capacitance
Parameter(1,2)
Symbol
CIN
COUT(3)
tLP
Max
Unit
7
pF
Output Capacitance
10
pF
Low-pass filter input time constant (SDA and SCL)
50
ns
Input Capacitance
Note: 1. Effective capacitance measured with power supply at 5V; sampled only, not 100% tested.
2. At 25°C, f = 1MHz.
3. Outputs deselected.
20/29
Min
M41T81S
Table 9. DC Characteristics
Sym
Test Condition(1)
Parameter
ILI
Input Leakage Current
ILO
Output Leakage Current
ICC1
Supply Current
Min
Typ
Max
Unit
0V ≤ VIN ≤ VCC
±1
µA
0V ≤ VOUT ≤ VCC
±1
µA
Switch Freq = 400kHz
400
µA
SCL = 0Hz
All Inputs
≥ VCC – 0.2V
≤ VSS + 0.2V
100
µA
ICC2
Supply Current (standby)
VIL
Input Low Voltage
–0.3
0.3VCC
V
VIH
Input High Voltage
0.7VCC
VCC + 0.3
V
VOL
Output Low Voltage
IOL = 3.0mA
0.4
V
Output Low Voltage (Open Drain)(2)
IOL = 10mA
0.4
V
Pull-up Supply Voltage (Open Drain)
IRQ/OUT/FT/SQW
5.5
V
3.5(4)
V
1
µA
VBAT(3)
Back-up Supply Voltage
IBAT
Battery Supply Current
Note: 1.
2.
3.
4.
2.0
TA = 25°C, VCC = 0V
Oscillator ON, VBAT = 3V
0.6
Valid for Ambient Operating Temperature: TA = –40 to 85°C; VCC = 2.7 to 5.5V (except where noted).
For IRQ/FT/OUT/SQW pin (Open Drain)
STMicroelectronics recommends the RAYOVAC BR1225 or BR1632 (or equivalent) as the battery supply.
For rechargeable back-up, VBAT (max) may be considered to be VCC.
Table 10. Crystal Electrical Characteristics
Parameter(1,2)
Sym
fO
Resonant Frequency
RS
Series Resistance
CL
Load Capacitance
Min
Typ
Max
32.768
kHz
60(3)
12.5
Units
kΩ
pF
Note: 1. Externally supplied if using the SO8 package. STMicroelectronics recommends the KDS DT-38: 1TA/1TC252E127, Tuning Fork
Type (thru-hole) or the DMX-26S: 1TJS125FH2A212, (SMD) quartz crystal for industrial temperature operations. KDS can be contacted at [email protected] or http://www.kdsj.co.jp for further information on this crystal type.
2. Load capacitors are integrated within the M41T81S. Circuit board layout considerations for the 32.768kHz crystal of minimum trace
lengths and isolation from RF generating signals should be taken into account.
3. For applications requiring back-up supply operation below 2.5V, RS (max) should be considered 40kΩ.
21/29
M41T81S
Figure 17. Power Down/Up Mode AC Waveforms
VCC
VSO
tPD
trec
SDA
SCL
DON'T CARE
AI00596
Table 11. Power Down/Up AC Characteristics
Parameter(1,2)
Symbol
Min
Typ
Max
Unit
tPD
SCL and SDA at VIH before Power Down
0
nS
trec
SCL and SDA at VIH after Power Up
10
µS
Note: 1. VCC fall time should not exceed 5mV/µs.
2. Valid for Ambient Operating Temperature: TA = –40 to 85°C; VCC = 2.7 to 5.5V (except where noted).
Table 12. Power Down/Up Trip Points DC Characteristics
Parameter(1,2)
Sym
Power-fail Deselect
VPFD
VSO
Hysteresis
Battery Back-up Switchover Voltage
(VCC < VBAT; VCC < VPFD)
Hysteresis
Min
Typ
Max
Unit
2.5
2.6
2.7
V
25
mV
VBAT < VPFD
VBAT
V
VBAT > VPFD
VPFD
V
40
mV
Note: 1. All voltages referenced to VSS.
2. Valid for Ambient Operating Temperature: TA = –40 to 85°C; VCC = 2.7 to 5.5V (except where noted).
22/29
M41T81S
Figure 18. Bus Timing Requirements Sequence
SDA
tBUF
tHD:STA
tHD:STA
tF
tR
SCL
tHIGH
P
S
tLOW
tSU:DAT
tHD:DAT
tSU:STA
SR
tSU:STO
P
AI00589
Table 13. AC Characteristics
Parameter(1)
Sym
Min
Typ
Max
Units
400
kHz
fSCL
SCL Clock Frequency
tLOW
Clock Low Period
1.3
µs
tHIGH
Clock High Period
600
ns
0
tR
SDA and SCL Rise Time
300
ns
tF
SDA and SCL Fall Time
300
ns
tHD:STA
START Condition Hold Time
(after this period the first clock pulse is generated)
600
ns
tSU:STA
START Condition Setup Time
(only relevant for a repeated start condition)
600
ns
tSU:DAT(2)
Data Setup Time
100
ns
tHD:DAT
Data Hold Time
0
µs
tSU:STO
STOP Condition Setup Time
600
ns
Time the bus must be free before a new
transmission can start
1.3
µs
tBUF
Note: 1. Valid for Ambient Operating Temperature: TA = –40 to 85°C; VCC = 2.7 to 5.5V (except where noted).
2. Transmitter must internally provide a hold time to bridge the undefined region (300ns max) of the falling edge of SCL.
23/29
M41T81S
PACKAGE MECHANICAL INFORMATION
In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These
packages have a Lead-free second level interconnect. The category of second Level Interconnect is
marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97.
The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK
is an ST trademark. ECOPACK specifications are available at: www.st.com.
24/29
M41T81S
Figure 19. SO8 – 8-lead Plastic Small Package Outline
h x 45˚
A2
A
C
B
ddd
e
D
8
E
H
1
A1
α
L
SO-A
Note: Drawing is not to scale.
Table 14. SO8 – 8-lead Plastic Small Outline (150 mils body width), Package Mech. Data
mm
inches
Symb
Typ
Min
Max
A
1.35
A1
Min
Max
1.75
0.053
0.069
0.10
0.25
0.004
0.010
A2
1.10
1.65
0.043
0.065
B
0.33
0.51
0.013
0.020
C
0.19
0.25
0.007
0.010
D
4.80
5.00
0.189
0.197
E
3.80
4.00
0.150
0.157
–
–
–
–
H
5.80
6.20
0.228
0.244
h
0.25
0.50
0.010
0.020
L
0.40
0.90
0.016
0.035
α
0°
8°
0°
8°
N
8
e
ddd
1.27
Typ
0.050
8
0.10
0.004
25/29
M41T81S
Figure 20. SOX18 – 18-lead Plastic Small Outline, 300mils, Embedded Crystal, Outline
D
9
h x 45°
1
C
E
10
H
18
A2
A
B
ddd
A1
e
A1
α
L
SO-J
Note: Drawing is not to scale.
Table 15. SOX18 – 18-lead Plastic Small Outline, 300mils, Embedded Crystal, Package Mech.
Symbol
millimeters
Min
Max
Min
Max
A
2.44
2.69
0.096
0.106
A1
0.15
0.31
0.006
0.012
A2
2.29
2.39
0.090
0.094
B
0.41
0.51
0.016
0.020
C
0.20
0.31
0.008
0.012
11.56
11.66
0.455
0.459
D
Typ
11.61
ddd
e
Typ
0.457
0.10
E
26/29
inches
7.57
1.27
0.004
7.67
0.298
0.050
0.302
–
–
–
–
H
10.16
10.52
0.400
0.414
L
0.51
0.81
0.020
0.032
α
0°
8°
0°
8°
N
18
18
M41T81S
PART NUMBERING
Table 16. Ordering Information Scheme
Example:
M41T
81S
M
6
E
Device Type
M41T
Supply Voltage and Write Protect Voltage
81S = VCC = 2.7 to 5.5V
Package
M = SO8
MY(1) = SOX18
Temperature Range
6 = –40°C to 85°C
Shipping Method
For SO8:
E = ECOPACK Package, Tubes
F = ECOPACK Package, Tape & Reel
For SOX18:
blank = ECOPACK Package, Tubes
T = ECOPACK Package, Tape & Reel
Note: 1. The SOX18 package includes an embedded 32,768Hz crystal. Contact local ST sales office for availability.
For other options, or for more information on any aspect of this device, please contact the ST Sales Office
nearest you.
27/29
M41T81S
REVISION HISTORY
Table 17. Document Revision History
Date
Version
Revision Details
January 22, 2004
0.1
First Draft
06-Feb-04
0.2
Update BL information, characteristics, ratings, and Lead (Pb)-free information (Table
12, 6, 10, 16)
20-Feb-04
0.3
Update characteristics (Table 11, 12, 7, 16)
14-Apr-04
1.0
Product promoted; reformatted; update characteristics, including Lead-free package
information (Figure 4, 5, 12, 15; 4, 13, 16)
05-May-04
1.1
Update DC Characteristics (Table 9)
16-Jun-04
1.2
Add shipping package (Table 16)
13-Sep-04
2.0
Update Maximum ratings (Table 6)
26-Nov-04
3.0
Promote document; update characteristics and marketing status (Figure 1, 5; Table
16)
23-Sep-05
4.0
Update features; added Lead-free information (page 1; Figure 4; Table 1, 16)
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Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface, Interface,
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Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt,
Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt, Interrupt,
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Watchdog, Watchdog, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery,
Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery,
Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery,
Battery, Battery, Battery, Switchover, Switchover, Switchover, Switchover, Switchover, Switchover, Switchover, Switchover, Switchover, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Backup, Write Protect, Write
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SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC, SOIC
28/29
M41T81S
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics.
All other names are the property of their respective owners
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29/29