M62354AGP 8-bit 6ch D/A Converter with Buffer Amplifiers REJ03D0871-0201 Rev.2.01 Dec 27, 2007 Description M62354A is a CMOS structured semiconductor integrated circuit integrating 6 channels of built-in D/A converters with high performance buffer operational amplifier for each channel output. 3-wire serial interface (DI, CLK, LD) method is used for the transfer format of digital data to allow connection with microcomputer with minimum wiring DO terminal is provided to allow cascading serial use. Built-in buffer operational amplifiers are designed to operate or full swing in the whole voltage range from VCC to GND for each input/output. And their higher stability for capacitive load perfectly fits in to the use for electronic volume (VCA) or the replacement for semi-variable resistor for tuning. Features • • • • • 12-bit serial data input (3 wire serial data transfer method, DI, CLK, LD) Corresponds to TTL input for digital input (VINH ≥ 2 V, VINL ≤ 0.8 V) R-2R + segment method high performance 6ch 8-bit D/A converters 6ch buffer operational amplifiers operating in the whole voltage range from VCC to GND Buffer operational amplifiers with high oscillation stability for capacitive load Application Adjustment or control of industrial or home-use electronic equipments such as VTR camera, VTR set, TV, and CRT display. VCC VDD AO6 AO5 AO4 AO3 VSS 16 15 14 13 12 11 9 + − + − + − + − Block Diagram D/A D/A D/A 8-bit R-2R segment D/A converter Ch6 5 L 4 L 3 8-bit latch L (6) (6) ...... .... Address decoder 8-bit latch L Ch1 2 D/A + − + − D11 10 9 8 D7 6 5 4 3 2 1 0 8-bit R-2R segment D/A converter 1 2 3 4 5 6 8 DO LD CLK DI AO1 AO2 GND 12-bit shift register REJ03D0871-0201 Rev.2.01 Dec 27, 2007 Page 1 of 8 M62354AGP Pin Arrangement M62354AGP VCC DO 1 16 LD 2 15 VDD (VrefU) CLK 3 14 AO6 DI 4 13 AO5 AO1 5 12 AO4 AO2 6 11 AO3 NC 7 10 NC GND 8 9 VSS (VrefL) NC: No connection (Top view) Outline: PLSP0016JA-A (16P2E-A) Pin Description Pin No. Pin Name 4 1 3 DI DO CLK 2 5 6 11 12 13 14 16 8 15 9 LD AO1 AO2 AO3 AO4 AO5 AO6 VCC GND VDD VSS Function Serial data input terminal. 12-bit serial data is input to this terminal. Serial data output terminal. Serial data of 12-bit shift register is output from this terminal. Serial clock input terminal. Input signal from DI terminal is input to 12-bit shift register upon the rise of shift clock. Data is loaded to register when "H" is input to LD terminal. 8-bit D/A converter output terminal. Built-in buffer amp. is connected to VCC. D/A converted voltage between VDD and VSS is output to each terminal. Power supply terminal. Digital and analog common GND D/A converter High level reference voltage input terminal. D/A converter Low level reference voltage input terminal. REJ03D0871-0201 Rev.2.01 Dec 27, 2007 Page 2 of 8 M62354AGP Block Diagram for Explanation of Terminals DI CLK VCC GND 16 8 4 12-bit shift register 3 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 Decoder (8) (6) D0 ..... 8-bit latch D7 ............................... DO 2 LD ..... 8-bit latch D7 8-bit R-2R+segment D/A converter + − + − ......................................... 1 1 2 3 4 5 6 D0 ............................... 8-bit R-2R+segment D/A converter A1 15 D11 A6 5 14 AO6 AO1 VDD (VrefU) 9 VSS (VrefL) Absolute Maximum Ratings Item Supply voltage D/A converter High level reference voltage Digital input voltage Output voltage Power dissipation Operating temperature Storage temperature REJ03D0871-0201 Rev.2.01 Dec 27, 2007 Page 3 of 8 Symbol VCC VDD VIN Vout Pd Topr Tstg Ratings –0.3 to +7.0 –0.3 to +7.0 –0.3 to VCC + 0.3 –0.3 to VCC + 0.3 150 –20 to +85 –40 to +125 Unit V V V V mW °C °C M62354AGP Electrical Characteristics <Digital Part> (VCC, VrefU = 5 V ± 10%, VCC ≥ VrefU, GND, VrefL = 0.0 V, Ta = –20 to +85°C unless otherwise specified.) Min Limits Typ Max Unit Supply voltage Supply current VCC ICC 4.5 — 5.0 0.7 5.5 2.5 V mA Input leak current Digital input Low voltage Digital input High voltage Digital output Low voltage Digital output High voltage IILK VIL VIH VOL VOH –10 — 2.0 — VCC – 0.4 — — — — — 10 0.8 — 0.4 — µA V V V V Item Note: Symbol Conditions CLK = 1 MHz operation VCC = 5 V, IAO = 0 µA VIN = 0 to VCC IOL = 2.5 mA IOH = –400 µA Typical value is for Ta = 25°C Changes from M62354GP: Digital input voltage corresponds to TTL spec. <Analog Part> (VCC, VrefU = 5 V ± 10%, VCC ≥ VrefU, GND, VrefL = 0.0 V, Ta = –20 to +85°C unless otherwise specified.) Item Symbol Min Limits Typ Max Unit Conditions Reference voltage pin current IrefU — 0.7 1.3 mA VrefU = 5 V, VrefL = 0 V, IAO = 0 µA Data condition: at maximum current D/A converter High level reference voltage range VDD (VrefU) 3.5 — VCC V D/A converter Low level reference voltage range VSS (VrefL) GND — VCC – 3.5 V The output does not necessarily be the Values within the reference voltage setting range. The output value is determined by the buffer amplifier output voltage range (VAO). Buffer amplifier output drive range VAO IAO — — — VCC – 0.1 VCC – 0.2 1 V Buffer amplifier output drive range Differential nonlinearity Nonlinearity Zero code error Full scale error Output capacitive load 0.1 0.2 –1 mA –1.0 –1.5 –2.0 –2.0 — — — — — — — 5 1.0 1.5 2.0 2.0 0.1 — LSB LSB LSB LSB µF Ω Buffer Amp. output impedance SDL SL SZERO SFULL CO RO REJ03D0871-0201 Rev.2.01 Dec 27, 2007 Page 4 of 8 IAO = ± 100 µA IAO = ± 500 µA Upper side saturation voltage = 0.3 V Lower side saturation voltage = 0.2 V VrefU = 4.79 V VrefL = 0.95 V (15 mV/LSB) VCC = 5.5 V Without load (IAO = +0 µA) M62354AGP AC Characteristics (VCC, VrefU = 5 V ± 10%, VCC ≥ VrefU, GND, VrefL = 0.0 V, Ta = –20 to +85°C unless otherwise specified.) Item Clock "L" pulse width Clock "H" pulse width Clock rise time Clock fall time Data setup time Data hold time LD setup time LD hold time LD "H" hold time Data output delay time D/A output setting time Symbol tCKL tCKH tCR tCF tDCH tCHD tCHL tLDC tLDH tDO tLDD Min Limits Typ Max Unit 200 200 — — — — — — 200 ns ns ns 30 60 200 100 100 70 — — — — — — — — — — — — — 350 300 ns ns ns ns ns ns µs Conditions CL ≤ 100 pF CL ≤ 100 pF, VAO: 0.5 ↔ 4.5 V The time until the output becomes the final value of 1/2 LSB Measurement Circuit Input Output DUT CL ≤ 100 pF Timing Chart tCR tCKH tCF tCHL CLK tCKL tLDC DI tDCH tCHD tLDH tCHL LD tLDD AO1 to AO6 output tDO DO output REJ03D0871-0201 Rev.2.01 Dec 27, 2007 Page 5 of 8 tDO M62354AGP Digital Data Format First MSB Last LSB D0 D1 D2 D3 D4 D5 D6 D7 D8 DAC data D9 D10 D11 DAC select data DAC Data D0 0 1 0 1 : 0 1 D1 0 0 1 1 : 1 1 Note: D2 0 0 0 0 : 1 1 D3 0 0 0 0 : 1 1 D4 0 0 0 0 : 1 1 D5 0 0 0 0 : 1 1 D6 0 0 0 0 : 1 1 D7 0 0 0 0 : 1 1 D/A Output (VrefU – VrefL) / 256 × 1 + VrefL [V] (VrefU – VrefL) / 256 × 2 + VrefL [V] (VrefU – VrefL) / 256 × 3 + VrefL [V] (VrefU – VrefL) / 256 × 4 + VrefL [V] : (VrefU – VrefL) / 256 × 255 + VrefL [V] VrefU [V] VrefU = VDD, VrefL = VSS DAC Select Data D8 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 D9 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D10 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D11 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 DAC Selection Don't care AO1 select AO2 select AO3 select AO4 select AO5 select AO6 select Don't care Don't care Don't care Don't care Don't care Don't care Don't care Don't care Don't care Timing Chart (Model) CLK SI D11 D10 D9 D8 LD AO1 to AO6 REJ03D0871-0201 Rev.2.01 Dec 27, 2007 Page 6 of 8 D7 D6 D5 D4 D3 D2 D1 D0 (1 LSB) (2 LSB) (3 LSB) (4 LSB) (255 LSB) (256 LSB) M62354AGP Typical Application MCU 4 DI 3 CLK 2 LD 1 DO 16 15 VCC VDD (VrefU) AO1 5 AO2 6 AO3 11 AO4 12 AO5 13 AO6 14 GND VSS (VrefL) 8 9 Precaution for Use M62354AGP has 3 terminals (VDD, VCC, and VSS) to which constant voltage is to be applied. Ripple voltage or spike noise to these terminals may worsen converting precision or cause erroneous operations. So be sure to use this device by putting capacitor between each terminal and GND to get D/A conversion operation stabilized. Output buffer amplifiers have high oscillation stability against capacitive load. This means that jitters by wirings around output terminals or capacitor between output and GND (0.1 µF Max) do not cause any problems with DAC operations. Connect capacitor (0.1 µF or around) between output and GND for protection from spark discharge when this device is used under such high electric field as that for instance of instruments with cathode ray tube. REJ03D0871-0201 Rev.2.01 Dec 27, 2007 Page 7 of 8 M62354AGP Package Dimensions JEITA Package Code P-LSSOP16-4.4x5-0.65 RENESAS Code PLSP0016JA-A MASS[Typ.] 0.06g 9 E 16 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. *1 HE Previous Code 16P2E-A F 1 8 Index mark c A2 A1 Reference Dimension in Millimeters Symbol *2 A L D *3 e bp y Detail F D E A2 A A1 bp c HE e y L REJ03D0871-0201 Rev.2.01 Dec 27, 2007 Page 8 of 8 Min 4.9 4.3 Nom Max 5.0 5.1 4.4 4.5 1.15 1.45 0 0.1 0.2 0.17 0.22 0.32 0.13 0.15 0.2 0° 10° 6.2 6.4 6.6 0.53 0.65 0.77 0.10 0.3 0.5 0.7 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Notes: 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document. 2. 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