M68AW064F 1 Mbit (64K x16) 3.0V Asynchronous SRAM FEATURES SUMMARY ■ SUPPLY VOLTAGE: 2.7 to 3.6V ■ 64K x 16 bits SRAM with OUTPUT ENABLE ■ EQUAL CYCLE and ACCESS TIME: 55ns and 70ns ■ LOW STANDBY CURRENT ■ ■ LOW VCC DATA RETENTION: 2.0V TRI-STATE COMMON I/O ■ AUTOMATIC POWER DOWN April 2003 Figure 1. Packages BGA TFBGA48 (ZB) 6 x 8 solder balls 1/18 M68AW064F TABLE OF CONTENTS SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Figure 3. TFBGA Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 4. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Table 2. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Table 3. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 5. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 6. AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Table 4. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 5. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 6. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 7. Address Controlled, Read Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 8. Chip Enable or Output Enable Controlled, Read Mode AC Waveforms. . . . . . . . . . . . . . . 9 Figure 9. Chip Enable or UB/LB Controlled, Standby Mode AC Waveforms . . . . . . . . . . . . . . . . . . 9 Table 7. Read and Standby Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Write Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 10. Write Enable Controlled, Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 11. Chip Enable Controlled, Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 8. Write Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 12. Low V CC Data Retention AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 9. Low V CC Data Retention Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 TFBGA48 - 6 x 8 ball array, 0.75 mm pitch, Bottom View Package Outline . . . . . . . . . . . . . . . . . . 15 TFBGA48 - 6 x 8 ball array, 0.75 mm pitch, Package Mechanical Data . . . . . . . . . . . . . . . . . . . . . 15 PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 11. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 12. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2/18 M68AW064F SUMMARY DESCRIPTION The M68AW064F is a 1 Mbit (1,048,576 bit) CMOS SRAM, organized as 65,536 words by 16 bits. The device features fully static operation requiring no external clocks or timing strobes, with equal address access and cycle times. It requires a single 2.7 to 3.6V supply. This device has an au- tomatic power-down feature, reducing the power consumption by over 99% when deselected. The M68AW064F is available in TFBGA48 (0.75 mm pitch) package. Figure 2. Logic Diagram Table 1. Signal Names A0-A15 Address Inputs DQ0-DQ15 Data Input/Output E Chip Enable G Output Enable W Write Enable UB Upper Byte Enable Input LB Lower Byte Enable Input G VCC Supply Voltage UB VSS Ground NC Not Connected Internally VCC 16 16 A0-A15 DQ0-DQ15 W E M68AW064F LB VSS AI04872b 3/18 M68AW064F Figure 3. TFBGA Connections (Top view through package) 1 2 3 4 5 6 A LB G A0 A1 A2 NC B DQ8 UB A3 A4 E DQ0 C DQ9 DQ10 A5 A6 DQ1 DQ2 D VSS DQ11 NC A7 DQ3 VCC E VCC DQ12 NC NC DQ4 VSS F DQ14 DQ13 A14 A15 DQ5 DQ6 G DQ15 NC A12 A13 W DQ7 H NC A8 A9 A10 A11 NC AI04874 4/18 M68AW064F Figure 4. Block Diagram VCC VSS A15 ROW DECODER MEMORY ARRAY A7 DQ15 (8) I/O CIRCUITS UB COLUMN DECODER DQ0 (8) LB A0 A6 (8) UB W E UB (8) LB LB G AI04875 MAXIMUM RATING Stressing the device above the rating listed in the Absolute Maximum Ratings" table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not im- plied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 2. Absolute Maximum Ratings Symbol Value Unit 20 mA Ambient Operating Temperature –55 to 125 °C TSTG Storage Temperature –65 to 150 °C VCC Supply Voltage –0.5 to 4.6 V –0.5 to VCC +0.5 V 1 W IO (1) TA VIO (2) PD Parameter Output Current Input or Output Voltage Power Dissipation Note: 1. One output at a time, not to exceed 1 second duration. 2. Up to a maximum operating VCC of 3.6V only. 5/18 M68AW064F DC AND AC PARAMETERS This section summarizes the operating and measurement conditions, as well as the DC and AC characteristics of the device. The parameters in the following DC and AC Characteristic tables are derived from tests performed under the Measure- ment Conditions listed in the relevant tables. Designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters. Table 3. Operating and AC Measurement Conditions Parameter M68AW064F VCC Supply Voltage 2.7 to 3.6V Ambient Operating Temperature –40 to 85°C Load Capacitance (CL) 30 or 5pF Output Circuit Protection Resistance (R1) 1.10kΩ Load Resistance (R2) 1.55kΩ ≤ 4ns Input Rise and Fall Times 0 to VCC Input Pulse Voltages VCC/2 Input and Output Timing Ref. Voltages VOL = 0.3VCC; VOH = 0.7VCC Input and Output Transition Timing Ref. Voltages Figure 5. AC Measurement I/O Waveform Figure 6. AC Measurement Load Circuit VCC 1N914 I/O Timing Reference Voltage VCC R1 VCC/2 0V DEVICE UNDER TEST OUT CL I/O Transition Timing Reference Voltage VCC 0V R2 0.7VCC 0.3VCC AI04831 CL includes JIG capacitance AI03853 6/18 M68AW064F Table 4. Capacitance CIN COUT (3) Test Condition Parameter(1,2) Symbol Input Capacitance on all pins (except DQ) Output Capacitance Min Max Unit VIN = 0V 6 pF VOUT = 0V 8 pF Note: 1. Sampled only, not 100% tested. 2. At TA = 25°C, f = 1 MHz, VCC = 3.0V. 3. Outputs deselected. Table 5. DC Characteristics M68AW064F Symbol Parameter Test Condition 55 Min 70 Typ Max ICC1 (1) Operating Supply Current VCC = 3.6V, f = 1/tAVAV, IOUT = 0mA 7 20 ICC2 Operating Supply Current VCC = 3.6V, f = 1MHz, IOUT = 0mA 1 2 Standby Supply Current CMOS VCC = 3.6V, E ≥ VCC –0.15V, f = 0 0.5 15 ISB (2) Min Typ Unit Max 15 mA 1 2 mA 0.5 15 µA 0V ≤ VIN ≤ VCC –1 1 –1 1 µA 0V ≤ VOUT ≤ VCC (3) –1 1 –1 1 µA Input High Voltage VCC = 2.7V 2.0 VCC + 0.3 2.0 VCC + 0.3 V VIL Input Low Voltage VCC = 2.7V –0.3 0.4 –0.3 0.4 V VOH Output High Voltage VCC = 2.7V, IOH = –1.0mA 2.2 VOL Output Low Voltage VCC = 2.7V, IOL = 2.1mA ILI Input Leakage Current ILO Output Leakage Current VIH 2.2 0.4 V 0.4 V Note: 1. Average AC current, cycling at tAVAV minimum. 2. All other Inputs at V IL ≤ 0.15V or V IH ≥ V CC –0.15V. 3. Output disabled. 7/18 M68AW064F OPERATION The M68AW064F has a Chip Enable power down feature which invokes an automatic standby mode whenever either Chip Enable is de-asserted (E = High) or LB and UB are de-asserted (LB and UB = High). An Output Enable (G) signal provides a high speed tri-state control, allowing fast read/ write cycles to be achieved with the common I/O data bus. Operational modes are determined by device control inputs W, E, LB and UB as summarized in the Operating Modes table (see Table 6). Table 6. Operating Modes Operation E W G LB UB DQ0-DQ7 DQ8-DQ15 Power Deselected/Power-down VIH X X X X Hi-Z Hi-Z Standby (ISB) Deselected/Power-down X X X VIH VIH Hi-Z Hi-Z Standby (ISB) Lower Byte Read VIL VIH VIL VIL VIH Data Output Hi-Z Active (ICC) Lower Byte Write VIL VIL X VIL VIH Data Input Hi-Z Active (ICC) Output Disabled VIL X VIH VIL X Hi-Z Hi-Z Active (ICC) Output Disabled VIL X VIH X VIL Hi-Z Hi-Z Active (ICC) Upper Byte Read VIL VIH VIL VIH VIL Hi-Z Data Output Active (ICC) Upper Byte Write VIL VIL X VIH VIL Hi-Z Data Input Active (ICC) Word Read VIL VIH VIL VIL VIL Data Output Data Output Active (ICC) Word Write VIL VIL X VIL VIL Data Input Data Input Active (ICC) Note: 1. X = VIH or VIL. Read Mode The M68AW064F is in the Read mode whenever Write Enable (W) is High with Output Enable (G) Low, and Chip Enable (E) is asserted. This provides access to data from eight or sixteen, depending on the status of the signal UB and LB, of the 1,048,576 locations in the static memory array, specified by the 16 address inputs. Valid data will be available at the eight or sixteen output pins within t AVQV after the last stable address, providing G is Low and E is Low. If Chip Enable or Output Enable access times are not met, data access will be measured from the limiting parameter (tELQV, tGLQV or t BLQV) rather than the address. Data out may be indeterminate at tELQX, tGLQX and tBLQX but data lines will always be valid at tAVQV. Figure 7. Address Controlled, Read Mode AC Waveforms tAVAV A0-A15 VALID tAVQV DQ0-DQ15 tAXQX DATA VALID AI04876 Note: E = Low, G = Low, W = High, UB = Low and/or LB = Low. 8/18 M68AW064F Figure 8. Chip Enable or Output Enable Controlled, Read Mode AC Waveforms. tAVAV VALID A0-A15 tAVQV tAXQX tELQV tEHQZ E tELQX tGLQV tGHQZ G tGLQX DQ0-DQ15 VALID tBLQV tBHQZ UB, LB tBLQX AI04877 Note: Write Enable (W) = High. Figure 9. Chip Enable or UB/LB Controlled, Standby Mode AC Waveforms E, UB, LB ICC ISB tPU tPD 50% AI03856 9/18 M68AW064F Table 7. Read and Standby Mode AC Characteristics M68AW064F Symbol Parameter 55 Min. tAVAV Read Cycle Time tAVQV Address Valid to Output Valid tAXQX Data hold from address change 70 Max. 55 Min. Unit Max. 70 55 10 ns 70 10 ns ns tBHQZ (1, 2) Upper/Lower Byte Enable High to Output Hi-Z 20 25 ns tBLQV Upper/Lower Byte Enable Low to Output Valid 25 35 ns tBLQX Upper/Lower Byte Enable Low to Output Transition 5 5 ns tEHQZ (1, 2) Chip Enable High to Output Hi-Z 20 25 ns tELQV Chip Enable Low to Output Valid 55 70 ns tELQX Chip Enable Low to Output Transition 10 10 ns tGHQZ (1, 2) Output Enable High to Output Hi-Z 20 25 ns tGLQV Output Enable Low to Output Valid 25 35 ns tGLQX Output Enable Low to Output Transition tPD Chip Enable or UB/LB High to Power Down tPU Chip Enable or UB/LB Low to Power Up 5 5 55 0 ns 70 0 ns ns Note: 1. At any given temperature and voltage condition, t GHQZ is less than tGLQX , tBHQZ is less than tBLQX and t EHQZ is less than tELQX for any given device. 2. CL = 5pF. 10/18 M68AW064F Write Mode The M68AW064F is in the Write mode whenever the W and E are Low. Either the Chip Enable input (E) or the Write Enable input (W) must be deasserted during Address transitions for subsequent write cycles. When E (W) is Low, and UB or LB is Low, write cycle begins on the W (E)’s falling edge. Therefore, address setup time is referenced to Write Enable as tAVWL and to Chip Enable as tAVEL and is determined by the latter occurring edge. The Write cycle can be terminated by the earlier rising edge of E or W. If the Output is enabled (E = Low, G = Low, LB or UB = Low), then W will return the outputs to high impedance within t WLQZ of its falling edge. Care must be taken to avoid bus contention in this type of operation. Data input must be valid for tDVWH before the rising edge of Write Enable, or for tDVEH before the rising edge of E, whichever occurs first, and remain valid for t WHDX and tEHDX respectively. Figure 10. Write Enable Controlled, Write AC Waveforms tAVAV VALID A0-A15 tAVWH tWHAX tAVEL E tWLWH tAVWL W tWLQZ tWHQX tWHDX DQ0-DQ15 DATA INPUT tDVWH tBLWH UB, LB AI04878 11/18 M68AW064F Figure 11. Chip Enable Controlled, Write AC Waveforms tAVAV A0-A15 VALID tAVEH tAVEL tELEH tEHAX E tAVWL W tEHDX DQ0-DQ15 DATA INPUT tDVEH tBLEH UB, LB AI04879 12/18 M68AW064F Table 8. Write Mode AC Characteristics M68AW064F Symbol Parameter 55 Min 70 Max Min Unit Max tAVAV Write Cycle Time 55 70 ns tAVEH Address Valid to Chip Enable High 45 60 ns tAVEL Address valid to Chip Enable Low 0 0 ns tAVWH Address Valid to Write Enable High 45 60 ns tAVWL Address Valid to Write Enable Low 0 0 ns tBLEH LB, UB Low to Chip Enable High 45 60 ns tBLWH LB, UB Low to Write Enable High 45 60 ns tDVEH Input Valid to Chip Enable High 25 30 ns tDVWH Input Valid to Write Enable High 25 30 ns tEHAX Chip Enable High to Address Transition 0 0 ns tEHDX Chip enable High to Input Transition 0 0 ns tELEH Chip Enable Low to Chip Enable High 45 60 ns tWHAX Write Enable High to Address Transition 0 0 ns tWHDX Write Enable High to Input Transition 0 0 ns tWHQX (1) Write Enable High to Output Transition 5 5 ns tWLQZ (1,2) Write Enable Low to Output Hi-Z tWLWH Write Enable Low to Write Enable High 25 40 25 50 ns ns Note: 1. At any given temperature and voltage condition, tWLQZ is less than tWHQX for any given device. 2. CL = 5pF. 13/18 M68AW064F Figure 12. Low VCC Data Retention AC Waveforms DATA RETENTION MODE 3.6V VCC 3.3V VDR > 2.0V tCDR tR E ≥ VDR – 0.2V E AI04885 Table 9. Low V CC Data Retention Characteristics Symbol Parameter ICCDR (1) Supply Current (Data Retention) tCDR (1,2) Chip Deselected to Data Retention Time tR (2) Operation Recovery Time VDR (1) Supply Voltage (Data Retention) Test Condition Min VCC = 2.0V, E ≥ VCC –0.3V, f = 0 (3) E ≥ VCC –0.3V, f = 0 E ≥ VCC –0.3V, f = 0 Max Unit 0.5 15 µA tAVAV ns 0 ns 2.0 Note: 1. All other Inputs at V IH ≥ VCC –0.2V or VIL ≤ 0.2V. 2. See Figure 12 for measurement points. Guaranteed but not tested. tAVAV is Read cycle time. 3. No input may exceed VCC +0.3V. 14/18 Typ 3.6 V M68AW064F PACKAGE MECHANICAL Figure 13. TFBGA48 - 6 x 8 ball array, 0.75 mm pitch, Bottom View Package Outline D D1 FD FE SD SE BALL "A1" E E1 ddd e e b A A2 A1 BGA-Z26 Note: Drawing is not to scale. Table 10. TFBGA48 - 6 x 8 ball array, 0.75 mm pitch, Package Mechanical Data Symbol millimeters Typ Min A inches Max Typ Min 1.200 A1 0.0472 0.260 A2 0.0102 0.900 b Max 0.350 0.450 0.0354 0.0138 0.0177 D 6.000 5.900 6.100 0.2362 0.2323 0.2402 D1 3.750 – – 0.1476 – – ddd 0.100 0.0039 E 8.000 7.900 8.100 0.3150 0.3110 0.3189 E1 5.250 – – 0.2067 – – e 0.750 – – 0.0295 – – FD 1.125 – – 0.0443 – – FE 1.375 – – 0.0541 – – SD 0.375 – – 0.0148 – – SE 0.375 – – 0.0148 – – 15/18 M68AW064F PART NUMBERING Table 11. Ordering Information Scheme Example: M68AW064F L 55 ZB 6 T Device Type M68 Mode A = Asynchronous Operating Voltage W = 2.7 to 3.6V Array Organization 064 = 1 Mbit (64K x16) Option 1 F = 1 Chip Enable; Standby from UB and LB Option 2 L = Low Leakage Speed Class 55 = 55ns 70 = 70ns Package ZB = TFBGA48: 0.75 mm pitch Operative Temperature 6 = –40 to 85 °C Shipping T = Tape & Reel Packing For a list of available options (Speed, Package, etc.) or for further information on any aspect of this device, please contact the STMicroelectronics Sales Office nearest to you. 16/18 M68AW064F REVISION HISTORY Table 12. Document Revision History Date Version Revision Details July 2001 -01 First Issue 09-Oct-2002 1.1 Revision numbering modified: a minor revision will be indicated by incrementing the digit after the dot, and a major revision, by incrementing the digit before the dot (revision version 01 equals 1.0). Part number modified. 23-Apr-2003 1.2 55ns speed class added. Maximum Standby Supply Current ISB modified. Values of certain AC Characteristics modified. 17/18 M68AW064F Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics All other names are the property of their respective owners © 2003 STMicroelectronics - All Rights Reserved STMicroelectronics group of companies Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. www.st.com 18/18