FINAL COM’L: -12/15/20 IND: -18/24 MACHLV210-12/15/20 Lattice Semiconductor High Density EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS ■ Low-voltage operation, 3.3-V JEDEC compatible ■ 83.3 MHz fCNT — VCC = +3.0 V to +3.6 V ■ < 5 mA standby current ■ 32 Outputs ■ Patented design allows minimal standby current without speed degradation ■ 4 “PAL22V16” blocks with buried macrocells ■ Exclusively designed for 3.3-V applications ■ 44 Pins ■ 64 Macrocells ■ 38 Bus-Friendly Inputs ■ 64 Flip-flops; 2 clock choices ■ Pin-, function-, and JEDEC-compatible with MACH210 ■ Pin-compatible with MACH110, MACH111, MACH210, MACH211, and MACH215 ■ 12 ns tPD Commercial 18 ns tPD Industrial GENERAL DESCRIPTION The MACHLV210 is a member of the highperformance EE CMOS MACH 2 device family. This device has approximately six times the logic macrocell capability of the popular PAL22V10 at an equal speed with a lower cost per macrocell. It is architecturally identical to the MACH210, with the addition of I/O pull-up/pull-down resistors and low-voltage, low-power operation. matrix connects the PAL blocks to each other and to all input pins, providing a high degree of connectivity between the fully-connected PAL blocks. This allows designs to be placed and routed efficiently. The MACHLV210 provides 3.3-V operation with lowpower CMOS technology. The patented design allows for minimal standby current without speed degradation by limiting the leakage current when signals are not switching. At less than 5 mA maximum standby current, the MACHLV210 is ideal for low-power applications. The MACHLV210 has two kinds of macrocell: output and buried. The MACHLV210 output macrocell provides registered, latched, or combinatorial outputs with programmable polarity. If a registered configuration is chosen, the register can be configured as D-type or T-type to help reduce the number of product terms. The register type decision can be made by the designer or by the software. All output macrocells can be connected to an I/O cell. If a buried macrocell is desired, the internal feedback path from the macrocell can be used, which frees up the I/O pin for use as an input. The MACHLV210 consists of four PAL blocks interconnected by a programmable switch matrix. The four PAL blocks are essentially “PAL22V16” structures complete with product-term arrays and programmable macrocells, including additional buried macrocells. The switch The MACHLV210 has dedicated buried macrocells which, in addition to the capabilities of the output macrocell, also provide input registers or latches for use in synchronizing signals and reducing setup time requirements. Publication# 17908 Rev. D Issue Date: May 1995 Amendment /0 BLOCK DIAGRAM I/O0–I/O7 I0–I1, I3–I4 I/O8–I/O15 8 I/O Cells 8 I/O Cells 8 8 8 Macrocells Macrocells 8 8 8 Macrocells 2 Macrocells OE OE 44 x 68 AND Logic Array and Logic Allocator 44 x 68 AND Logic Array and Logic Allocator 22 4 22 Switch Matrix 22 22 44 x 68 AND Logic Array and Logic Allocator 44 x 68 AND Logic Array and Logic Allocator OE OE Macrocells 8 8 I/O Cells 2 Macrocells 8 Macrocells 8 8 Macrocells 8 2 I/O Cells 8 8 I/O24–I/O31 I/O16–I/O23 CLK0/I2, CLK1/I5 17908D-1 2 MACHLV210-12/15/20 CONNECTION DIAGRAM Top View I/O0 GND 4 2 3 I/O29 I/O28 I/O2 I/O1 5 I/O31 I/O30 I/O3 6 VCC I/O4 PLCC 1 44 43 42 41 40 I/O5 I/O6 7 39 I/O27 8 38 I/O7 I0 9 37 I/O26 I/O25 10 I/O24 CLK1/I5 I1 11 36 35 GND 12 34 GND CLK0/I2 13 33 I4 I/O8 I/O9 14 32 I3 15 31 I/O10 I/O11 16 30 I/O23 I/O22 29 I/O21 17 I/O20 I/O18 I/O19 I/O16 I/O17 GND VCC I/O14 I/O15 I/O12 I/O13 18 19 20 21 22 23 24 25 26 27 28 17908D-2 Note: Pin-compatible with MACH110, MACH111, MACH210, MACH211, and MACH215. PIN DESIGNATIONS CLK/I = GND = I = I/O = VCC Clock or Input Ground Input Input/Output = Supply Voltage MACHLV210-12/15/20 3 ORDERING INFORMATION Commercial Products Programmable logic products for commercial applications are available with several ordering options. The order number (Valid Combination) is formed by a combination of: MACH LV 210 -12 J C FAMILY TYPE MACH = Macro Array CMOS High-Speed OPTIONAL PROCESSING Blank = Standard Processing TECHNOLOGY LV = Low Voltage OPERATING CONDITIONS C = Commercial (0°C to +70°C) DEVICE NUMBER 210 = 64 Macrocells, 44 Pins, Input Pull-Up/Pull-Down Resistors PACKAGE TYPE J = 44-Pin Plastic Leaded Chip Carrier (PL 044) SPEED -12 = 12 ns tPD -15 = 15 ns tPD -20 = 20 ns tPD Valid Combinations MACHLV210-12 MACHLV210-15 MACHLV210-20 4 JC Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations. MACHLV210-12/15/20 (Com’l) ORDERING INFORMATION Industrial Products Programmable logic products for industrial applications are available with several ordering options. The order number (Valid Combination) is formed by a combination of: MACH LV 210 -18 J I FAMILY TYPE MACH = Macro Array CMOS High-Speed OPTIONAL PROCESSING Blank = Standard Processing TECHNOLOGY LV = Low Voltage OPERATING CONDITIONS I = Industrial (–40°C to +85°C) DEVICE NUMBER 210 = 64 Macrocells, 44 Pins, Input Pull-Up/Pull-Down Resistors PACKAGE TYPE J = 44-Pin Plastic Leaded Chip Carrier (PL 044) SPEED -18 = 18 ns tPD -24 = 24 ns tPD Valid Combinations MACHLV210-18 MACHLV210-24 JI Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations. MACHLV210-18/24 (Ind) 5 FUNCTIONAL DESCRIPTION Table 1. Logic Allocation The MACHLV210 consists of four PAL blocks connected by a switch matrix. There are 32 I/O pins and 4 dedicated input pins feeding the switch matrix. These signals are distributed to the four PAL blocks for efficient design implementation. There are two clock pins that can also be used as dedicated inputs. The MACHLV210 inputs and I/O pins have advanced pull-up/pull-down resistors that enable the inputs to be pulled to the last driven state. While it is always a good design practice to tie unused pins high or low, the MACHLV210 pull-up/pull-down resistors provide design security and stability in the event that unused pins are left disconnected. Macrocell Output Buried M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 The PAL Blocks Each PAL block in the MACHLV210 (Figure 1) contains a 64-product-term logic array, a logic allocator, 8 output macrocells, 8 buried macrocells, and 8 I/O cells. The switch matrix feeds each PAL block with 22 inputs. This makes the PAL block look effectively like an independent “PAL22V16” with 8 buried macrocells. In addition to the logic product terms, two output enable product terms, an asynchronous reset product term, and an asynchronous preset product term are provided. One of the two output enable product terms can be chosen within each I/O cell in the PAL block. All flip-flops within the PAL block are initialized together. The Switch Matrix The MACHLV210 switch matrix is fed by the inputs and feedback signals from the PAL blocks. Each PAL block provides 16 internal feedback signals and 8 I/O feedback signals. The switch matrix distributes these signals back to the PAL blocks in an efficient manner that also provides for high performance. The design software automatically configures the switch matrix when fitting a design into the device. The Product-term Array M11 M12 M13 M14 M15 Available Clusters C0, C1, C2 C0, C1, C2, C3 C1, C2, C3, C4 C2, C3, C4, C5 C3, C4, C5, C6 C4, C5, C6, C7 C5, C6, C7, C8 C6, C7, C8, C9 C7, C8, C9, C10 C8, C9, C10, C11 C9, C10, C11, C12 C10, C11, C12, C13 C11, C12, C13, C14 C12, C13, C14, C15 C13, C14, C15 C14, C15 The Macrocell The MACHLV210 has two types of macrocell: output and buried. The output macrocells can be configured as either registered, latched, or combinatorial, with programmable polarity. The macrocell provides internal feedback whether configured with or without the flip-flop. The registers can be configured as D-type or T-type, allowing for product-term optimization. The flip-flops can individually select one of two clock/ gate pins, which are also available as data inputs. The registers are clocked on the LOW-to-HIGH transition of the clock signal. The latch holds its data when the gate input is HIGH, and is transparent when the gate input is LOW. The flip-flops can also be asynchronously initialized with the common asynchronous reset and preset product terms. The MACHLV210 product-term array consists of 64 product terms for logic use, and 4 special-purpose product terms. Two of the special-purpose product terms provide programmable output enable; one provides asynchronous reset, and one provides asynchronous preset. The buried macrocells are the same as the output macrocells if they are used for generating logic. In that case, the only thing that distinguishes them from the output macrocells is the fact that there is no I/O cell connection, and the signal is only used internally. The buried macrocell can also be configured as an input register or latch. The Logic Allocator The I/O Cell The logic allocator in the MACHLV210 takes the 64 logic product terms and allocates them to the 16 macrocells as needed. Each macrocell can be driven by up to 16 product terms. The design software automatically configures the logic allocator when fitting the design into the device. The I/O cell in the MACHLV210 consists of a three-state output buffer. The three-state buffer can be configured in one of three ways: always enabled, always disabled, or controlled by a product term. If product term control is chosen, one of two product terms may be used to provide the control. The two product terms that are available are common to all I/O cells in a PAL block. Table 1 illustrates which product term clusters are available to each macrocell within a PAL block. Refer to Figure 1 for cluster and macrocell numbers. 6 These choices make it possible to use the macrocell as an output, an input, a bidirectional pin, or a three-state output for use in driving a bus. MACHLV210-12/15/20 Benefits of Lower Operating Voltage The MACHLV210 has an operating voltage range of 3.0 V to 3.6 V. Low voltage allows for lower operating power consumption, longer battery life, and/or smaller batteries for portable applications. Because power is proportional to the square of the voltage, reduction of the supply voltge from 5.0 V to 3.3 V significantly reduces power consumption. This directly translates to longer battery life for portable applications. Lower power consumption can also be used to reduce the size and weight of the battery. Thus, 3.3-V designs facilitate a reduction in the form factor. The MACHLV210 is not designed to interface between 3.3-V and 5.0-V logic. Latch-up may occur if VOH for the MACHLV210 is greater than VIH for the 5.0-V device. Although this scenario is unlikely, interfacing the MACHLV210 with 5.0-V devices is not encouraged without necessary latch-up design precautions. MACHLV210-12/15/20 7 0 4 8 12 16 20 24 28 32 36 40 43 Output Enable Output Enable Asynchronous Reset Asynchronous Preset Output Macro cell M0 I/O Cell I/O I/O Cell I/O I/O Cell I/O I/O Cell I/O I/O Cell I/O I/O Cell I/O I/O Cell I/O I/O Cell I/O 2 Buried Macro cell M1 2 Output Macro cell M2 2 Buried Macro cell M3 0 2 C0 C1 Output Macro cell M4 2 C2 C3 Buried Macro cell M5 2 C5 C6 Switch Matrix C7 C8 Logic Allocator C4 C9 Output Macro cell M6 2 Buried Macro cell M7 2 Output Macro cell M8 2 C10 C11 Buried Macro cell M9 2 C12 C13 Output Macro cell M10 2 C14 C15 63 Buried Macro cell M11 2 Output Macro cell M12 2 Buried Macro cell M13 2 Output Macro cell M14 2 Buried Macro cell M15 2 8 12 16 20 24 28 32 36 40 43 CLK1 4 CLK0 0 16 8 14128G-2 17908D-3 Figure 1. MACHLV210 PAL Block 8 MACHLV210-12/15/20 ABSOLUTE MAXIMUM RATINGS OPERATING RANGES Storage Temperature . . . . . . . . . . . –65°C to +150°C Commercial (C) Devices Ambient Temperature with Power Applied . . . . . . . . . . . . . –55°C to +125°C Temperature (TA) Operating in Free Air . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C Supply Voltage with Respect to Ground . . . . . . . . . . . . . –0.5 V to +5.0 V Supply Voltage (VCC) with Respect to Ground . . . . . . . . . . . . . . +3.0 V to +3.6 V DC Input Voltage . . . . . . . . . . . –0.5 V to VCC + 0.5 V DC Output or I/O Pin Voltage . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Operating ranges define those limits between which the functionality of the device is guaranteed. Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V Latchup Current (TA = 0°C to +70°C) . . . . . . 200 mA Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ. DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified Parameter Symbol Parameter Description Test Conditions Min Typ Max Unit VOH Output HIGH Voltage IOH = –2 mA, VCC = Min VIN = VIH or VIL 2.4 VOL Output LOW Voltage IOL = 2 mA, VCC = Min VIN = VIH or VIL VIH Input HIGH Voltage Guaranteed Input Logical HIGH Voltage for all Inputs (Note 1) VIL Input LOW Voltage Guaranteed Input Logical LOW Voltage for all Inputs (Note 1) 0.8 V IIH Input HIGH Leakage Current VIN = 3.6 V, VCC = Max (Note 2) 10 µA IIL Input LOW Leakage Current VIN = 0 V, VCC = Max (Note 2) –10 µA IOZH Off-State Output Leakage Current HIGH VOUT = 3.6 V, VCC = Max VIN = VIH or VIL (Note 2) 10 µA IOZL Off-State Output Leakage Current LOW VOUT = 0 V, VCC = Max VIN = VIH or VIL (Note 2) –10 µA ISC Output Short-Circuit Current VOUT = 0.5 V, VCC = Max (Note 3) –160 mA ICC Supply Current (Typical) VCC = 3.3 V, TA = 25°C, f = 0 MHz (Note 4) f = 25 MHz V 0.4 2.0 V V –30 2 mA 60 mA Notes: 1. These are absolute values with respect to device ground and all overshoots due to system or tester noise are included. 2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH). 3. Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second. VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation. 4. Measured with a 16-bit up/down counter pattern. This pattern is programmed in each PAL block and is capable of being loaded, enabled, and reset. MACHLV210-12 (Com’l) 9 CAPACITANCE (Note 1) Parameter Symbol CIN COUT Parameter Description Test Conditions Input Capacitance VCC = 3.3 V, TA = 25°C, f = 1 MHz Output Capacitance Typ Unit 6 pF 8 pF SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2) Parameter Symbol tPD -12 Parameter Description Min Input, I/O, or Feedback to Combinatorial Output tS Setup Time from Input, I/O, or Feedback to Clock tH Register Data Hold Time tCO Clock to Output tWL tWH Clock Width fMAX 12 Internal Feedback (fCNT) ns 9 ns T-type 10 ns 0 ns ns LOW HIGH 5 6 ns ns D-type 58.8 MHz T-type 55.6 MHz D-type 83.3 MHz T-type 76.9 MHz 90.9 MHz No Feedback (fCNT) 10 Unit D-type 8 External Feedback Maximum Frequency (Note 1) Max tSL Setup Time from Input, I/O, or Feedback to Gate 9 ns tHL Latch Data Hold Time 0 ns tGO Gate to Output tGWL Gate Width LOW tPDL Input, I/O, or Feedback to Output Through Transparent Input or Output Latch tSIR Input Register Setup Time 2 ns tHIR Input Register Hold Time 1.5 ns tICO Input Register Clock to Combinatorial Output tICS Input Register Clock to Output Register Setup 9 5 tWICL tWICH Input Register Clock Width fMAXIR Maximum Input Register Frequency 1/(tWICL + tWICH) ns ns 15 15 ns ns D-type 12 ns T-type 13 ns LOW HIGH 5 6 ns ns 90.9 MHz tSIL Input Latch Setup Time 2 ns tHIL Input Latch Hold Time 1.5 ns tIGO Input Latch Gate to Combinatorial Output 17 ns tIGOL Input Latch Gate to Output Through Transparent Output Latch 19 ns tSLL Setup Time from Input, I/O, or Feedback Through Transparent Input Latch to Output Latch Gate 10 ns tIGS Input Latch Gate to Output Latch Setup 13 ns MACHLV210-12 (Com’l) SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2) (continued) Parameter Symbol -12 Parameter Description Min tWIGL Input Latch Gate Width LOW tPDLL Input, I/O, or Feedback to Output Through Transparent Input and Output Latches Max 5 Unit ns 17 16 ns tAR Asynchronous Reset to Registered or Latched Output tARW Asynchronous Reset Width (Note 1) 12 ns tARR Asynchronous Reset Recovery Time (Note 1) 12 ns 16 ns tAP Asynchronous Preset to Registered or Latched Output tAPW Asynchronous Preset Width (Note 1) 12 ns ns tAPR Asynchronous Preset Recovery Time (Note 1) 12 ns tEA Input, I/O, or Feedback to Output Enable 12 ns tER Input, I/O, or Feedback to Output Disable 12 ns Notes: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. 2. See Switching Test Circuit, for test conditions. MACHLV210-12 (Com’l) 11 ABSOLUTE MAXIMUM RATINGS OPERATING RANGES Storage Temperature . . . . . . . . . . . –65°C to +150°C Commercial (C) Devices Ambient Temperature with Power Applied . . . . . . . . . . . . . –55°C to +125°C Supply Voltage with Respect to Ground . . . . . . . . . . . . . –0.5 V to +5.0 V Temperature (TA) Operating in Free Air . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C Supply Voltage (VCC) with Respect to Ground . . . . . . . . . . . . +3.0 V to +3.6 V DC Input Voltage . . . . . . . . . . . –0.5 V to VCC + 0.5 V DC Output or I/O Pin Voltage . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Operating ranges define those limits between which the functionality of the device is guaranteed. Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V Latchup Current (TA = 0°C to +70°C) . . . . . . 200 mA Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ. DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified Parameter Symbol Parameter Description Test Conditions Min VOH Output HIGH Voltage IOH = –2 mA, VCC = Min VIN = VIH or VIL 2.4 VOL Output LOW Voltage IOL = 2 mA, VCC = Min VIN = VIH or VIL VIH Input HIGH Voltage Guaranteed Input Logical HIGH Voltage for all Inputs (Note 1) VIL Input LOW Voltage Guaranteed Input Logical LOW Voltage for all Inputs (Note 1) 0.8 V IIH Input HIGH Leakage Current Input LOW Leakage Current VIN = 3.6 V, VCC = Max (Note 2) VIN = 0 V, VCC = Max (Note 2) 10 –10 µA µA IOZH Off-State Output Leakage Current HIGH VOUT = 3.6 V, VCC = Max VIN = VIH or VIL (Note 2) 10 µA IOZL Off-State Output Leakage Current LOW VOUT = 0 V, VCC = Max VIN = VIH or VIL (Note 2) –10 µA ISC Output Short-Circuit Current VOUT = 0.5 V, VCC = Max (Note 3) –160 mA ICC Supply Current (Typical) VCC = 3.3 V, TA = 25°C (Note 4) IIL Typ Max V 0.4 f = 0 MHz f = 25 MHz Unit 2.0 V V –30 2 60 mA mA Notes: 1. These are absolute values with respect to device ground and all overshoots due to system or tester noise are included. 2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH). 3. Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second. VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation. 4. Measured with a 16-bit up/down counter pattern. This pattern is programmed in each PAL block and capable of being loaded, enabled, and reset. 12 MACHLV210-15/20 (Com’l) CAPACITANCE (Note 1) Parameter Symbol CIN COUT Parameter Description Test Conditions Typ Input Capacitance VCC = 3.3 V, TA = 25°C, f = 1 MHz Output Capacitance Unit 6 pF 8 pF SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2) Parameter Symbol -15 Min Max Parameter Description tPD Input, I/O, or Feedback to Combinatorial Output (Note 3) tS Setup Time from Input, I/O, or Feedback to Clock tH Register Data Hold Time tCO Clock to Output (Note 3) tWL tWH Clock Width External Feedback fMAX Maximum Frequency (Note 1) 15 20 1/(tS + tCO) Unit ns D-type 10 14 ns T-type 11 15 ns 0 0 ns 10 Internal Feedback (fCNT) No Feedback -20 Min Max 12 ns LOW HIGH 5 6 7 8 ns ns D-type 50 38.5 MHz T-type 47.6 37 MHz D-type 66.6 50 MHz T-type 62.5 47.6 MHz 90.9 66.7 MHz 14 ns 1/(tWL + tWH) tSL Setup Time from Input, I/O, or Feedback to Gate 10 0 tHL Latch Data Hold Time tGO Gate to Output (Note 3) tGWL Gate Width LOW tPDL Input, I/O, or Feedback to Output Through tSIR Input Register Setup Time 2.5 3 ns tHIR Input Register Hold Time 1.5 3 ns tICO Input Register Clock to Combinatorial Output tICS Input Register Clock to Output Register Setup 0 11 5 tWICL tWICH Input Register Clock Width fMAXIR Maximum Input Register Frequency 1/(tWICL + tWICH) ns 15 7 17 ns 23 18 ns 24 ns ns D-type 13 27 ns T-type 14 20 ns LOW HIGH 5 6 7 8 ns ns 90.9 66.7 MHz tSIL Input Latch Setup Time 2.5 3 ns tHIL Input Latch Hold Time 1.5 2 ns tIGO Input Latch Gate to Combinatorial Output 19 25 ns tIGOL Input Latch Gate to Output Through Transparent Output Latch 22 29 ns tSLL Setup Time from Input, I/O, or Feedback Through Transparent Input Latch to Output Latch Gate 12 16 ns Input Latch Gate to Output Latch Setup 14 18 ns tIGS MACHLV210-15/20 (Com’l) 13 SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2) (continued) -15 Min Max Parameter Symbol Parameter Description -20 Min Max Unit tWIGL Input Latch Gate Width LOW tPDLL Input, I/O, or Feedback to Output Through Transparent Input and Output Latches 21 28 ns tAR Asynchronous Reset to Registered or Latched Output 20 26 ns 5 tARW Asynchronous Reset Width (Note 1) 15 tARR Asynchronous Reset Recovery Time (Note 1) 15 tAP Asynchronous Preset to Registered or Latched Output 7 ns 20 ns 20 20 ns 26 ns tAPW Asynchronous Preset Width (Note 1) 15 20 ns tAPR Asynchronous Preset Recovery Time (Note 1) 15 20 ns tEA Input, I/O, or Feedback to Output Enable (Note 3) 15 20 ns tER Input, I/O, or Feedback to Output Disable (Note 3) 15 20 ns Notes: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. 2. See Switching Test Circuit for test conditions. 3. Parameters measured with 16 outputs switching. 14 MACHLV210-15/20 (Com’l) ABSOLUTE MAXIMUM RATINGS INDUSTRIAL OPERATING RANGES Storage Temperature . . . . . . . . . . . –65°C to +150°C Temperature (TA) Operating in Free Air . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C Ambient Temperature with Power Applied . . . . . . . . . . . . . –55°C to +125°C Supply Voltage with Respect to Ground . . . . . . . . . . . . . –0.5 V to +5.0 V DC Input Voltage . . . . . . . . . . . –0.5 V to VCC + 0.5 V DC Output or I/O Pin Voltage . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Supply Voltage (VCC) with Respect to Ground . . . . . . . . . . . . . . +3.0 V to +3.6 V Operating ranges define those limits between which the functionality of the device is guaranteed. Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V Latchup Current (TA = –40°C to +85°C) . . . . 200 mA Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ. DC CHARACTERISTICS over INDUSTRIAL operating ranges unless otherwise specified Parameter Symbol Parameter Description Test Conditions Min VOH Output HIGH Voltage IOH = –2 mA, VCC = Min VIN = VIH or VIL 2.4 VOL Output LOW Voltage IOL = 2 mA, VCC = Min VIN = VIH or VIL VIH Input HIGH Voltage Guaranteed Input Logical HIGH Voltage for all Inputs (Note 1) VIL Input LOW Voltage Guaranteed Input Logical LOW Voltage for all Inputs (Note 1) 0.8 V IIH Input HIGH Leakage Current Input LOW Leakage Current VIN = 3.6 V, VCC = Max (Note 2) VIN = 0 V, VCC = Max (Note 2) 10 –10 µA µA IOZH Off-State Output Leakage Current HIGH VOUT = 3.6 V, VCC = Max VIN = VIH or VIL (Note 2) 10 µA IOZL Off-State Output Leakage Current LOW VOUT = 0 V, VCC = Max VIN = VIH or VIL (Note 2) –10 µA ISC Output Short-Circuit Current VOUT = 0.5 V, VCC = Max (Note 3) –160 mA ICC Supply Current (Typical) VCC = 3.3 V, TA = 25°C (Note 4) IIL Typ Max V 0.4 f = 0 MHz f = 25 MHz Unit 2.0 V V –30 2 60 mA mA Notes: 1. These are absolute values with respect to device ground and all overshoots due to system or tester noise are included. 2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH). 3. Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second. VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation. 4. Measured with a 16-bit up/down counter pattern. This pattern is programmed in each PAL block and capable of being loaded, enabled, and reset. MACHLV210-18/24 (Ind) 15 CAPACITANCE (Note 1) Parameter Symbol CIN COUT Parameter Description Test Conditions Typ Input Capacitance VCC = 3.3 V, TA = 25°C, f = 1 MHz Output Capacitance Unit 6 pF 8 pF SWITCHING CHARACTERISTICS over INDUSTRIAL operating ranges (Note 2) Parameter Symbol Parameter Description tPD Input, I/O, or Feedback to Combinatorial Output (Note 3) tS Setup Time from Input, I/O, or Feedback to Clock tH Register Data Hold Time tCO Clock to Output (Note 3) tWL tWH Clock Width External Feedback fMAX Maximum Frequency (Note 1) -24 Min Max 18 24 ns 12 17 ns T-type 13.5 18 ns 0 12 1/(tS + tCO) Unit D-type 0 Internal Feedback (fCNT) No Feedback 16 -18 Min Max ns 14.5 ns LOW HIGH 6 7.5 8.5 10 ns ns D-type 40 30.5 MHz T-type 38 29.5 MHz D-type 53 40 MHz T-type 1/(tWL + tWH) 50 38 MHz 72.5 53 MHz tSL Setup Time from Input, I/O, or Feedback to Gate 12 17 ns tHL Latch Data Hold Time 0 0 ns tGO Gate to Output (Note 3) tGWL Gate Width LOW tPDL Input, I/O, or Feedback to Output Through Latch tSIR Input Register Setup Time 3 4 ns tHIR Input Register Hold Time 2.5 4 ns tICO Input Register Clock to Combinatorial Output tICS Input Register Clock to Output Register Setup 13.5 6 tWICL tWICH Input Register Clock Width fMAXIR Maximum Input Register Frequency 1/(tWICL + tWICH) 18 ns 28 ns 8.5 20.5 22 ns 29 ns D-type 16 32.5 ns T-type 17 24 ns LOW HIGH 6 7.5 8.5 10 ns ns 72.5 53 MHz tSIL Input Latch Setup Time 3 4 ns tHIL Input Latch Hold Time 2.5 3 ns tIGO Input Latch Gate to Combinatorial Output tIGOL Input Latch Gate to Output Through Transparent Output Latch tSLL Setup Time from Input, I/O, or Feedback Through Transparent Input Latch to Output Latch Gate tIGS Input Latch Gate to Output Latch Setup MACHLV210-18/24 (Ind) 23 30 26.5 34.5 ns ns 14.5 19.5 ns 17 22 ns SWITCHING CHARACTERISTICS over INDUSTRIAL operating ranges (Note 2) (continued) -18 Min Max Parameter Symbol Parameter Description -24 Min Max Unit tWIGL Input Latch Gate Width LOW tPDLL Input, I/O, or Feedback to Output Through Transparent Input and Output Latches 25.5 34 ns tAR Asynchronous Reset to Registered or Latched Output 24 31.5 ns 6 tARW Asynchronous Reset Width (Note 1) 18 tARR Asynchronous Reset Recovery Time (Note 1) 18 tAP Asynchronous Preset to Registered or Latched Output 8.5 ns 24 ns 24 24 ns 31.5 ns tAPW Asynchronous Preset Width (Note 1) 18 24 ns tAPR Asynchronous Preset Recovery Time (Note 1) 18 24 ns tEA Input, I/O, or Feedback to Output Enable (Note 3) 18 24 ns tER Input, I/O, or Feedback to Output Disable (Note 3) 18 24 ns Notes: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. 2. See Switching Test Circuit at the back of this Data Sheet for test conditions. 3. Parameters measured with 16 outputs switching. MACHLV210-18/24 (Ind) 17 KEYS TO SWITCHING WAVEFORMS WAVEFORM INPUTS OUTPUTS Must be Steady Will be Steady May Change from H to L Will be Changing from H to L May Change from L to H Will be Changing from L to H Don’t Care; Any Change Permitted Changing, State Unknown Does Not Apply Center Line is HighImpedance “Off” State KS000010-PAL SWITCHING TEST CIRCUIT* 3.3 V S1 R1 Output Test Point R2 CL 17908D-4 Commercial Specification tPD, tCO tEA tER S1 CL R1 R2 Closed 1.5 V Z → H: Open Z → L: Closed 30 pF H → Z: Open L → Z: Closed 5 pF 1.5 V 1.6 K 1.6 K *Switching several outputs simultaneously should be avoided for accurate measurement. 18 Measured Output Value MACHLV210-12/15/20 H → Z: VOH – 0.5 V L → Z: VOL + 0.5 V TYPICAL CURRENT VS. VOLTAGE (I-V) CHARACTERISTICS VCC = 3.3 V, TA = 25°C IOL (mA) 80 60 40 20 VOL (V) –1.0 –0.8 –0.6 –0.4 –0.2 –20 .2 .4 .6 .8 1.0 –40 –60 –80 17908D-5 Output, LOW IOH (mA) 25 1 2 3 4 5 VOH (V) –3 –2 –1 –25 –50 –75 –100 –125 –150 17908D-6 Output, HIGH II (mA) 20 VI (V) –2 –1 –20 1 2 3 4 5 –40 –60 –80 –100 17908D-7 Input MACHLV210-12/15/20 19 TYPICAL ICC CHARACTERISTICS VCC = 3.3 V, TA = 25°C 150 125 100 MACHLV210 ICC (mA) 75 50 25 0 0 10 20 30 40 50 60 70 Frequency (MHz) 17908D-8 The selected “typical” pattern is a 16-bit up/down counter. This pattern is programmed in each PAL block and is capable of being loaded, enabled, and reset. Maximum frequency shown uses internal feedback and a D-type register. 20 MACHLV210-12/15/20 ENDURANCE CHARACTERISTICS The MACHLV210 is manufactured using our advanced Electrically Erasable process. This technology uses an EE cell to replace the fuse link used in bipolar Parameter Symbol tDR N Parameter Description parts. As a result, the device can be erased and reprogrammed, a feature which allows 100% testing at the factory. Min Unit Max Storage Temperature Test Conditions 10 Years Min Pattern Data Retention Time Max Operating Temperature 20 Years Max Reprogramming Cycles Normal Programming Conditions 100 Cycles INPUT/OUTPUT EQUIVALENT SCHEMATICS VCC >50 kΩ ESD Program/Verify Protection Circuitry Input VCC >50 kΩ Preload Circuitry Feedback Input Output 17908D-9 MACHLV210-12/15/20 21 TYPICAL THERMAL CHARACTERISTICS Measured at 25°C ambient. These parameters are not tested. Parameter Symbol Typ Parameter Description PLCC Units θjc Thermal impedance, junction to case 15 °C/W θja Thermal impedance, junction to ambient 40 °C/W 200 lfpm air 36 °C/W 400 lfpm air 33 °C/W 600 lfpm air 31 °C/W 800 lfpm air 29 °C/W θjma Thermal impedance, junction to ambient with air flow Plastic θjc Considerations The data listed for plastic θjc are for reference only and are not recommended for use in calculating junction temperatures. The heat-flow paths in plastic-encapsulated devices are complex, making the θjc measurement relative to a specific location on the package surface. Tests indicate this measurement reference point is directly below the die-attach area on the bottom center of the package. Furthermore, θjc tests on packages are performed in a constant-temperature bath, keeping the package surface at a constant temperature. Therefore, the measurements can only be used in a similar environment. 22 MACHLV210-12/15/20 SWITCHING WAVEFORMS Input, I/O, or Feedback VT tPD Combinatorial Output VT 17908D-10 Combinatorial Output Input, I/O, or Feedback Input, I/O, or Feedback VT tS VT tH tSL Gate VT Clock tHL tCO Registered Output VT tPDL tGO Latched Out VT VT 17908D-12 17908D-11 Registered Output Latched Output (MACH 2, 3, and 4) tWH Clock Gate VT tGWS tWL 17908D-14 17908D-13 Clock Width Gate Width (MACH 2, 3, and 4) Registered Input VT tSIR Input Register Clock Registered Input VT tHIR Input Register Clock VT tICO Combinatorial Output VT 17908D-15 Output Register Clock Registered Input (MACH 2 and 4) VT tICS VT 17908D-16 Input Register to Output Register Setup (MACH 2 and 4) Notes: 1. VT = 1.5 V. 2. Input pulse amplitude 0 V to 3.0 V. 3. Input rise and fall times 2 ns–4 ns typical. MACHLV210-12/15/20 23 SWITCHING WAVEFORMS Latched In VT tSIL tHIL Gate VT tIGO Combinatorial Output VT 17908D-17 Latched Input (MACH 2 and 4) tPDLL Latched In VT Latched Out Input Latch Gate VT tIGOL tSLL tIGS VT Output Latch Gate 17908D-18 Latched Input and Output (MACH 2, 3, and 4) Notes: 1. VT = 1.5 V. 2. Input pulse amplitude 0 V to 3.0 V. 3. Input rise and fall times 2 ns–4 ns typical. 24 MACHLV210-12/15/20 SWITCHING WAVEFORMS tWICH Clock Input Latch Gate VT VT tWICL tWIGL 17908D-20 17908D-19 Input Register Clock Width (MACH 2 and 4) Input Latch Gate Width (MACH 2 and 4) tARW tAPW Input, I/O, or Feedback Input, I/O, or Feedback VT VT tAR Registered Output tAP Registered Output VT VT tARR Clock tAPR Clock VT VT 17908D-21 17908D-22 Asynchronous Reset Asynchronous Preset Input, I/O, or Feedback VT tER Outputs tEA VOH - 0.5V VOL + 0.5V VT 17908D-23 Output Disable/Enable Notes: 1. VT = 1.5 V. 2. Input pulse amplitude 0 V to 3.0 V. 3. Input rise and fall times 2 ns–4 ns typical. MACHLV210-12/15/20 25 fMAX PARAMETERS The parameter fMAX is the maximum clock rate at which the device is guaranteed to operate. Because the flexibility inherent in programmable logic devices offers a choice of clocked flip-flop designs, fMAX is specified for three types of synchronous designs. The first type of design is a state machine with feedback signals sent off-chip. This external feedback could go back to the device inputs, or to a second device in a multi-chip state machine. The slowest path defining the period is the sum of the clock-to-output time and the input setup time for the external signals (tS + tCO). The reciprocal, fMAX, is the maximum frequency with external feedback or in conjunction with an equivalent speed device. This fMAX is designated “fMAX external.” The second type of design is a single-chip state machine with internal feedback only. In this case, flip-flop inputs are defined by the device inputs and flip-flop outputs. Under these conditions, the period is limited by the internal delay from the flip-flop outputs through the internal feedback and logic to the flip-flop inputs. This fMAX is designated “fMAX internal”. A simple internal counter is a good example of this type of design; therefore, this parameter is sometimes called “fCNT.” The third type of design is a simple data path application. In this case, input data is presented to the flip-flop and clocked through; no feedback is employed. Under these conditions, the period is limited by the sum of the data setup time and the data hold time (tS + tH). However, a lower limit for the period of each fMAX type is the minimum clock period (tWH + tWL). Usually, this minimum clock period determines the period for the third fMAX, designated “fMAX no feedback.” For devices with input registers, one additional fMAX parameter is specified: fMAXIR. Because this involves no feedback, it is calculated the same way as fMAX no feedback. The minimum period will be limited either by the sum of the setup and hold times (tSIR + tHIR) or the sum of the clock widths (tWICL + tWICH). The clock widths are normally the limiting parameters, so that fMAXIR is specified as 1/(tWICL + tWICH). Note that if both input and output registers are use in the same path, the overall frequency will be limited by tICS. All frequencies except fMAX internal are calculated from other measured AC parameters. fMAX internal is measured directly. CLK CLK (SECOND CHIP) LOGIC LOGIC REGISTER tS tS t CO fMAX Internal (fCNT) fMAX External; 1/(tS + tCO) LOGIC REGISTER CLK CLK REGISTER REGISTER tS tSIR fMAX No Feedback; 1/(tS + tH) or 1/(tWH + tWL) LOGIC tHIR fMAXIR ; 1/(tSIR + tHIR) or 1/(tWICL + tWICH) 17908D-24 26 MACHLV210-12/15/20 POWER-UP RESET The MACH devices have been designed with the capability to reset during system power-up. Following powerup, all flip-flops will be reset to LOW. The output state will depend on the logic polarity. This feature provides extra flexibility to the designer and is especially valuable in simplifying state machine initialization. A timing diagram and parameter table are shown below. Due to the synchronous operation of the power-up reset and the Parameter Symbol wide range of ways VCC can rise to its steady state, two conditions are required to insure a valid power-up reset. These conditions are: 1. The VCC rise must be monotonic. 2. Following reset, the clock input must not be driven from LOW to HIGH until all applicable input and feedback setup times are met. Parameter Descriptions Max Unit tPR Power-Up Reset Time 10 µs tS Input or Feedback Setup Time tWL Clock Width LOW See Switching Characteristics VCC Power 4V tPR Registered Output tS Clock tWL 17908D-25 Power-Up Reset Waveform MACHLV210-12/15/20 27 USING PRELOAD AND OBSERVABILITY In order to be testable, a circuit must be both controllable and observable. To achieve this, the MACH devices incorporate register preload and observability. Preloaded HIGH D In preload mode, each flip-flop in the MACH device can be loaded from the I/O pins, in order to perform functional testing of complex state machines. Register preload makes it possible to run a series of tests from a known starting state, or to load illegal states and test for proper recovery. This ability to control the MACH device’s internal state can shorten test sequences, since it is easier to reach the state of interest. Q1 Q AR Preloaded HIGH The observability function makes it possible to see the internal state of the buried registers during test by overriding each register’s output enable and activating the output buffer. The values stored in output and buried registers can then be observed on the I/O pins. Without this feature, a thorough functional test would be impossible for any designs with buried registers. D Q2 Q AR While the implementation of the testability features is fairly straightforward, care must be taken in certain instances to insure valid testing. One case involves asynchronous reset and preset. If the MACH registers drive asynchronous reset or preset lines and are preloaded in such a way that reset or preset are asserted, the reset or preset may remove the preloaded data. This is illustrated in Figure 2. Care should be taken when planning functional tests, so that states that will cause unexpected resets and presets are not preloaded. Another case to be aware of arises in testing combinatorial logic. When an output is configured as combinatorial, the observability feature forces the output into registered mode. When this happens, all product terms are forced to zero, which eliminates all combinatorial data. For a straight combinatorial output, the correct value will be restored after the preload or observe function, and there will be no problem. If the function implements a combinatorial latch, however, it relies on feedback to hold the correct value, as shown in Figure 3. As this value may change during the preload or observe operation, you cannot count on the data being correct after the operation. To insure valid testing in these cases, outputs that are combinatorial latches should not be tested immediately following a preload or observe sequence, but should first be restored to a known state. On Preload Mode Off Q1 AR Q2 Figure 2. Preload/Reset Conflict 17908D-26 Set All MACH 2 devices support both preload and observability. Contact individual programming vendors in order to verify programmer support. Reset Figure 3. Combinatorial Latch 17908D-27 28 MACHLV210-12/15/20 PHYSICAL DIMENSIONS* PL 044 44-Pin Plastic Leaded Chip Carrier (measured in inches) .685 .695 .650 .656 .042 .056 .062 .083 Pin 1 I.D. .685 .695 .650 .656 .500 .590 REF .630 .013 .021 .026 .032 .050 REF .009 .015 TOP VIEW .090 .120 .165 .180 SEATING PLANE SIDE VIEW 16-038-SQ PL 044 DA78 6-28-94 ae *For reference only. BSC is an ANSI standard for Basic Space Centering. MACHLV210-12/15/20 33