FUJITSU MICROELECTRONICS
DATA SHEET
DS07-12625-3E
8-bit Proprietary Microcontrollers
CMOS
F2MC-8FX MB95R203
MB95R203
■ DESCRIPTION
The MB95R203 is general-purpose, single-chip microcontrollers. In addition to a compact instruction set, the
microcontrollers contain a variety of peripheral functions.
Note : F2MC is the abbreviation of FUJITSU Flexible Microcontroller.
■ FEATURES
• F2MC-8FX CPU core
Instruction set optimized for controllers
• Multiplication and division instructions
• 16-bit arithmetic operations
• Bit test branch instruction
• Bit manipulation instructions etc.
• Clock
• Selectable Main clock source
Main OSC clock (Up to 10 MHz, Maximum Machine clock frequency is 5 MHz)
External clock (Up to 20 MHz, Maximum Machine clock frequency is 10 MHz)
Internal main CR clock (Typ 1 MHz, Machine clock frequency is 1 MHz)
• Selectable Sub clock source
Sub OSC clock (32 kHz)
Sub internal CR clock (Typ : 100 kHz, Min : 50 kHz, Max : 200 kHz)
(Continued)
Copyright©2009 FUJITSU MICROELECTRONICS LIMITED All rights reserved
2009.8
MB95R203
(Continued)
• Timer
• 8/16-bit composite timer
• Timebase timer
• Watch prescaler
• UART/SIO
• Offers clock asynchronous (UART) or clock synchronous (SIO) serial data transfer
• Full duplex double buffer
2
•IC
• Built-in wake-up function
• External interrupt
• Interrupt by the edge detection (Select rising edge/falling edge/both edges)
• Can be used to recover from low-power consumption modes (also called standby mode)
• 8/10-bit A/D converter
• 8-bit or 10-bit resolutions can be selected
• Low-power consumption (standby) mode
• Stop mode
• Sleep mode
• Watch mode
• Timebase timer mode
• I/O port : Max 16
• General-purpose I/O ports (Max) :
CMOS I/O : 12, N-ch open drain : 4
• On-chip debug
• 1 wire serial control
• Support serial writing. (Asynchronous mode)
• Hardware/Software watchdog timer
• Built-in Hardware watchdog timer
• Low voltage detection circuit (LVD)
• Low voltage detection reset circuit
• Circuit to monitor FRAM power supply
• Clock supervisor counter (CSV)
• Built-in Clock supervise function
• Programmable input voltage levels of port
• CMOS input level / hysteresis input level
• FRAM
• Non-volatile memory
• 8 Kbytes of FRAM integrated on-chip
• FRAM memory security function
• Protects the content of FRAM memory
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MB95R203
■ PRODUCT OVERVIEW
Part number
MB95R203
Parameter
ROM (FRAM) capacity
8 Kbytes
RAM capacity
496 bytes
Reset output
Yes
Low voltage detection
Yes
: 136 instructions
: 8 bits
: 1 to 3 bytes
: 1, 8, and 16 bits
: 300 ns (at machine clock 10 MHz)
: 1.7 μs (at machine clock 10 MHz)
CPU function
Number of basic instructions
Instruction bit length
Instruction length
Data bit length
Minimum instruction execution time
Interrupt processing time
Port
General-purpose I/O ports (Max) : 16
CMOS I/O : 12, N-ch open drain : 4
Timebase timer
Interrupt cycle : 0.256 ms to 8.3 s (at external 4 MHz)
Hardware/software
Watchdog timer
Reset generation cycle
Main clock at 10 MHz : 105 ms (Min)
Subclock CR can be used as the Watchdog source clock.
Wild registers
It can be used to replace three bytes of data.
UART/SIO
Able to transfer data using UART/SIO
Variable data length (5/6/7/8-bit) , built-in baud rate generator
Transfer rate (2400 bps to 125000 bps at 10 MHz) , full-duplex transfers with
built-in double buffers
NRZ type transfer format, error detection function
LSB-first or MSB-first can be selected
Capable of clock synchronous (SIO) or clock asynchronous (UART) serial data
transfer
I2C bus
Transmit and receive master/slave
Bus function, arbitration function, transfer direction detection function
Start condition repeated generation and detection functions
Built-in timeout detection function
8/10-bit A/D converter
6 ch
8-bit or 10-bit resolution can be selected
2 ch
8/16-bit composite timer
Can be configured as a 2 ch × 8-bit timer or 1 ch × 16-bit timer
Built-in timer function, PWC function, PWM function and capture function
Count clock : available from internal clocks (7 types) or external clocks
With square wave output
6 ch
External interrupt
On-chip debug
Interrupt by edge detection (Select rising edge/falling edge/both edges)
Can be used to recover from standby modes
1 wire serial control
Support serial writing. (Asynchronous mode)
(Continued)
DS07-12625-3E
3
MB95R203
(Continued)
Part number
MB95R203
Parameter
Watch prescaler
Eight different time intervals can be selected.
FRAM
Non-volatile memory
Number of read/write cycles : (Min)1010 times (Typ)1011 times
Data retention characteristics : 10 years ( + 55 °C)
Read security function
Function to monitor FRAM power supply
Standby Mode
Sleep mode, Stop mode, Watch mode, timebase timer mode
Package
SDIP-24, SOP-20
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DS07-12625-3E
MB95R203
■ PIN ASSIGNMENT
(TOP VIEW)
X0
NC
X1
Vss
X1A/PG2
X0A/PG1
Vcc
SCL/P65
RST/PF2
TO10/P62
NC
TO11/P63
1
2
3
4
5
6
7
8
9
10
11
12
24pin
(DIP-24)
*The number of usable pins is 20.
24
23
22
21
20
19
18
17
16
15
14
13
P12/EC0/DBG
NC
P07/INT07
P06/INT06/TO01
P05/INT05/AN05/TO00/HCLK2
P04/INT04/AN04/UI/HCLK1/EC0
P03/INT03/AN03/UO
P02/INT02/AN02/UCK
P01/AN01
P00/AN00
NC
P64/EC1/SDA
20
19
18
17
16
15
14
13
12
11
P12/EC0/DBG
P07/INT07
P06/INT06/TO01
P05/INT05/AN05/TO00/HCLK2
P04/INT04/AN04/UI/HCLK1/EC0
P03/INT03/AN03/UO
P02/INT02/AN02/UCK
P01/AN01
P00/AN00
P64/EC1/SDA
(DIP-24P-M07)
(TOP VIEW)
X0
X1
Vss
X1A/PG2
X0A/PG1
Vcc
SCL/P65
RST/PF2
TO10/P62
TO11/P63
1
2
3
4
5
6
7
8
9
10
20pin
(SOP-20)
(FPT-20P-M09)
DS07-12625-3E
5
MB95R203
■ PIN DESCRIPTION
Pin no.
SDIP24 SOP20
Pin name
I/O
Circuit
type*
Function
1
1
X0
B
Main clock input oscillation pin
3
2
X1
B
Main clock input/output oscillation pin
4
3
Vss
⎯
Power supply pin (GND)
5
4
PG2/X1A
C
General-purpose I/O port
This pin is also used as Sub clock input/output oscillation pin.
6
5
PG1/X0A
C
General-purpose I/O port
This pin is also used as Sub clock input oscillation pin.
7
6
Vcc
⎯
Power supply pin
8
7
P65/SCL
I
General-purpose I/O port
This pin is also used as I2C clock I/O.
9
8
PF2/RST
A
General-purpose I/O port
This pin is also used as reset pin
10
9
P62/TO10
D
General-purpose I/O port
High current port
This pin is also used as 8/16-bit composite timer ch.1 output.
12
10
P63/TO11
D
General-purpose I/O port
This pin is also used as 8/16-bit composite timer ch.1 output.
High current port
13
11
P64/SDA/EC1
I
General-purpose I/O port
This pin is also used as I2C data I/O.
This pin is also used as 8/16-bit composite timer ch.1 clock input.
15
12
P00/AN00
E
General-purpose I/O port
This pin is also used as A/D converter analog input.
16
13
P01/AN01
E
General-purpose I/O port
This pin is also used as A/D converter analog input.
14
P02/INT02/AN02/
UCK
E
General-purpose I/O port
This pin is also used as external interrupt input.
This pin is also used as A/D converter analog input.
This pin is also used as UART/SIO clock I/O.
15
P03/INT03/AN03/
UO
E
General-purpose I/O port
This pin is also used as external interrupt input.
This pin is also used as A/D converter analog input.
This pin is also used as UART/SIO data output.
F
General-purpose I/O port
This pin is also used as external interrupt input.
This pin is also used as A/D converter analog input.
This pin is also used as UART/SIO data input.
This pin is also used as 8/16-bit composite timer ch.0 clock input.
17
18
19
16
P04/INT04/AN04/
UI/HCLK1/EC0
(Continued)
6
DS07-12625-3E
MB95R203
(Continued)
Pin no.
SDIP24 SOP20
20
17
Pin name
P05/INT05/AN05/
TO00/HCLK2
I/O
Circuit
type*
Function
E
General-purpose I/O port
This pin is also used as external interrupt input.
This pin is also used as A/D converter analog input.
The pins are also used as 8/16-bit compound timer ch.0 output.
This pin is also used as the external clock input.
21
18
P06/INT06/TO01
G
General-purpose I/O port
High current port
This pin is also used as external interrupt input.
This pin is also used as 8/16-bit compound timer ch.0 output.
22
19
P07/INT07
G
General-purpose I/O port
This pin is also used as external interrupt input.
24
20
P12/EC0/DBG
H
General-purpose I/O port
This pin is also used as DBG input pin.
This pin is also used as 8/16-bit composite timer ch.0 clock input.
2, 11,
14, 23
⎯
NC
⎯
Internal connect pin. Be sure this pin is left open.
* : For the I/O circuit type, refer to “■ I/O CIRCUIT TYPE”.
DS07-12625-3E
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MB95R203
■ I/O CIRCUIT TYPE
Type
Circuit
A
Remarks
Reset input / Hysteresis input
Reset output / Digital output
• N-ch open drain output
• Hysteresis input
• Reset output
N-ch
B
Clock input
X1
X0
• Oscillation circuit
• High-speed side
Feedback resistance : approx. 1 MΩ
• CMOS output
• Hysteresis input
Standby control
C
Port select
R
P-ch
Pull-up control
P-ch
Digital output
N-ch
Digital output
• Oscillation circuit
• Low-speed side
Feedback resistance : approx. 10 MΩ
• CMOS output
• Hysteresis input
• With pull-up control
Standby control
Hysteresis input
Clock input
X1A
X0A
Standby control / Port select Clock input
Port select
R
Digital
output
Pull-up control
Digital output
P-ch
N-ch
Digital output
Standby control
Hysteresis input
D
P-ch
Digital output
• CMOS output
• Hysteresis input
Digital output
N-ch
Standby control
Hysteresis input
(Continued)
8
DS07-12625-3E
MB95R203
(Continued)
Type
Circuit
Remarks
E
Pull-up control
R
P-ch
• CMOS output
• Hysteresis input
• With pull-up control
Digital output
P-ch
Digital output
N-ch
Analog input
A/D control
Standby control
Hysteresis input
F
Pull-up control
R
P-ch
Digital output
P-ch
•
•
•
•
CMOS output
Hysteresis input
CMOS input
With pull-up control
Digital output
N-ch
Analog input
A/D control
Standby control
Hysteresis input
CMOS input
G
Pull-up control
R
P-ch
• Hysteresis input
• CMOS output
• With pull-up control
Digital output
P-ch
Digital output
N-ch
Standby control
Hysteresis input
H
Hysteresis input
• N-ch open drain output
• Hysteresis input
Digital output
N-ch
I
N-ch
Digital output
• N-ch open drain output
• CMOS input
• Hysteresis input
CMOS input
Standby control
DS07-12625-3E
Hysteresis input
9
MB95R203
■ NOTES ON DEVICE HANDLING
• Preventing Latch-up
Care must be taken to ensure that maximum voltage ratings are not exceeded when they are used.
Latch-up may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pins
other than medium- and high-withstand voltage pins or if higher than the rating voltage is applied between VCC
pin and VSS pin.
When latch-up occurs, power supply current increases rapidly and might thermally damage elements.
• Stable Supply Voltage
Supply voltage should be stabilized.
A sudden change in power-supply voltage may cause a malfunction even within the guaranteed operating range
of the Vcc power-supply voltage.
For stabilization, in principle, keep the variation in Vcc ripple (p-p value) in a commercial frequency range
(50 Hz / 60 Hz) not to exceed 10% of the standard Vcc value and suppress the voltage variation so that the
transient variation rate does not exceed 0.1 V/ms during a momentary change such as when the power supply
is switched.
• Precautions for Use of External Clock
Even when an external clock is used, oscillation stabilization wait time is required for power-on reset, wake-up
from sub clock mode or stop mode.
• Do not use a sample used in program development as mass-produced product.
10
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MB95R203
■ PIN CONNECTION
• Treatment of Unused Input Pin
Leaving unused input pins unconnected can cause abnormal operation or latch-up, leaving to permanent damage. Unused input pins should always be pulled up or down through resistance of at least 2 kΩ. Any unused
input/output pins may be set to output mode and left open, or set to input mode and treated the same as unused
input pins. If there is unused output pin, make it to open.
• Power Supply Pins
In products with multiple VCC or VSS pins, the pins of the same potential are internally connected in the device
to avoid abnormal operations including latch-up. However, you must connect the pins to external power supply
and a ground line to lower the electro-magnetic emission level, to prevent abnormal operation of strobe signals
caused by the rise in the ground level, and to conform to the total output current rating.
Moreover, connect the current supply source with the VCC and VSS pins of this device at the low impedance. It
is also advisable to connect a ceramic bypass capacitor of approximately 0.1 μF between VCC and VSS near this
device.
• DBG Pin
Connect the DBG pin directly to external Pull-up.
To prevent the device unintentionally entering test mode due to noise, lay out the printed circuit board so as to
minimize the distance from the DBG pins to VCC or VSS pins.
The DBG pin should not stay at “L” level after power-on until the reset output is released.
• RST Pin
Connect the RST pin directly to Pull-up.
To prevent the device unintentionally entering test mode due to noise, lay out the printed circuit board so as to
minimize the distance from the RST pins to VCC or VSS pins.
The RST/PF2 pin functions as the reset input/output pin after power-on. In addition, the reset output can be
enabled by the RSTOE bit of the SYSC register, and the reset input function or the general purpose I/O function
can be selected by the RSTEN bit of the SYSC register.
• Example of DBG / RST connection diagram
R
DBG
R
RST
Pull-up resistor recommended
resistance
For DBG pin : R = 4.7 kΩ
For RST pin : R = 10 kΩ
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11
MB95R203
■ RESTRICTIONS
• Data written to FRAM before IR reflow is not guaranteed to retain after IR reflow.
(Data written to FRAM might be broken by heart processing at IR reflow.)
■ NOTES ON DEBUG
• Although the [Upload Flash Memory] button is enabled, clicking it does not start the actual processing.
• When you click on the [Erase Flash Memory] button on SOFTUNE Workbench, data is overwritten into the FRAM
area, as shown below.
Address
Data to be overwritten
F554H
55H
FAAAH
A0H
FFBCH
Indeterminate
FFBDH
Indeterminate
Entire FRAM except the above
FFH
• Be very careful not to apply voltages to the pins PF2/RST in excess of the absolute maximum ratings. Especially
when handling devices in the environment compatible to the package, such as MB95F200H/210H and so on,
the voltage may be erroneously applied to the pins PF2/RST in excess of the maximum rating and it may cause
thermal breakdown of the device.
12
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MB95R203
■ BLOCK DIAGRAM
F2MC-8FX CPU
Reset
PF2*1/RST*2
X1
X0
PG2/X1A*2
PG1/X0A*2
Oscillator
circuit
CR
Oscillator
LVD
FRAM (8 Kbytes)
with security
RAM (496 bytes)
Clock control
P12*1/DBG
On-chip debug
8/16-bit
composite timer (0)
Wild register
P02/INT02 to P07/INT07
External interrupt
P65*1/SCL*1
P64*1/SDA*1
(P02/UCK)
(P04/UI)
(P03/UO)
8/16-bit
composite timer (1)
(P05/TO00)
(P06/TO01)
P12/EC0(P04/EC0)
P62/TO10
P63/TO11
(P64/EC1)
I2C
8/10-bit A/D converter
(P00/AN00 to P05/AN05)
UART/SIO
Port
Port
VCC
VSS
*1 : P12, P64, P65, PF2 is N-ch open drain
*2 : Software option
DS07-12625-3E
13
MB95R203
■ CPU CORE
1. Memory space
Memory space of the MB95R203 is 64 Kbytes and consists of I/O area, data area, and program area. The
memory space includes special-purpose areas such as the general-purpose registers and vector table. Memory
map of the MB95R203 shown below.
• Memory Map
MB95R203
0000H
0080H
0090H
0100H
0200H
0280H
0F80H
1000H
I/O
RAM 496 B
Register
Extension I/O
-
E000H
FRAM 8 KB
FFFFH
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MB95R203
■ I/O MAP
Address
Register
abbreviation
Register name
R/W
Initial value
0000H
PDR0
Port 0 data register
R/W
00000000B
0001H
DDR0
Port 0 direction register
R/W
00000000B
0002H
PDR1
Port 1 data register
R/W
00000000B
0003H
DDR1
Port 1 direction register
R/W
00000000B
0004H
⎯
(disabled)
⎯
⎯
0005H
WATR
Oscillation stabilization wait time setting register
R/W
11111111B
0006H
⎯
(disabled)
⎯
⎯
0007H
SYCC
System clock control register
R/W
XXXXXX11B
0008H
STBC
Standby control register
R/W
00000XXXB
0009H
RSRR
Reset source register
R
XXXXXXXXB
000AH
TBTC
Timebase timer control register
R/W
00000000B
000BH
WPCR
Watch prescaler control register
R/W
00000000B
000CH
WDTC
Watchdog timer control register
R/W
00000000B
000DH
SYCC2
System clock control register 2
R/W
XX100011B
000EH
to
0015H
⎯
(disabled)
⎯
⎯
0016H
PDR6
Port 6 data register
R/W
00000000B
0017H
DDR6
Port 6 direction register
R/W
00000000B
0018H
to
0027H
⎯
(disabled)
⎯
⎯
0028H
PDRF
Port F data register
R/W
00000000B
0029H
DDRF
Port F direction register
R/W
00000000B
002AH
PDRG
Port G data register
R/W
00000000B
002BH
DDRG
Port G direction register
R/W
00000000B
002CH
PUL0
Port 0 pull-up register
R/W
00000000B
002DH
to
0034H
⎯
(disabled)
⎯
⎯
0035H
PULG
Port G pull-up register
R/W
00000000B
0036H
T01CR1
8/16-bit compound timer 01 control status register 1 ch.0
R/W
00000000B
0037H
T00CR1
8/16-bit compound timer 00 control status register 1 ch.0
R/W
00000000B
0038H
T11CR1
8/16-bit compound timer 11 control status register 1 ch.1
R/W
00000000B
0039H
T10CR1
8/16-bit compound timer 10 control status register 1 ch.1
R/W
00000000B
(Continued)
DS07-12625-3E
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MB95R203
Address
Register
abbreviation
Register name
R/W
Initial value
003AH
to
0048H
⎯
(disabled)
⎯
⎯
0049H
EIC10
External interrupt circuit control register ch.2/ch.3
R/W
00000000B
004AH
EIC20
External interrupt circuit control register ch.4/ch.5
R/W
00000000B
004BH
EIC30
External interrupt circuit control register ch.6/ch.7
R/W
00000000B
004CH
to
0055H
⎯
(disabled)
⎯
⎯
0056H
SMC1
UART/SIO serial mode control register 1
R/W
00000000B
0057H
SMC2
UART/SIO serial mode control register 2
R/W
00100000B
0058H
SSR
UART/SIO serial status and data register
R/W
00000001B
0059H
TDR
UART/SIO serial output data register
R/W
00000000B
005AH
RDR
UART/SIO serial input data register
R/W
00000000B
005BH
to
005FH
⎯
(disabled)
⎯
⎯
0060H
IBCR00
I2C bus control register 0
R/W
00000000B
R/W
00000000B
0061H
IBCR10
2
I C bus control register 1
2
0062H
IBSR0
I C bus status register
R/W
00000000B
0063H
IDDR0
I2C data register
R/W
00000000B
0064H
IAAR0
I2C address register
R/W
00000000B
2
0065H
ICCR0
I C clock control register
R/W
00000000B
0066H
FSCR
FRAM status/control register
R/W
00000000B
0067H
FRAC
FRAM register access control register
R/W
00000000B
0068H
FABH
FRAM write permit start address register (H)
R/W
11111111B
0069H
FABL
FRAM write permit start address register (L)
R/W
11111111B
006AH
FASH
FRAM write permit area size register (H)
R/W
00000000B
006BH
FASL
FRAM write permit area size register (L)
R/W
00000000B
006CH
ADC1
8/10-bit A/D converter control register 1
R/W
00000000B
006DH
ADC2
8/10-bit A/D converter control register 2
R/W
00000000B
006EH
ADDH
8/10-bit A/D converter data register (upper byte)
R/W
00000000B
006FH
ADDL
8/10-bit A/D converter data register (lower byte)
R/W
00000000B
0070H
FVAH
FRAM violation address register (H)
R
XXXXXXXXB
0071H
FVAL
FRAM violation address register (L)
R
XXXXXXXXB
(Continued)
16
DS07-12625-3E
MB95R203
Address
Register
abbreviation
Register name
R/W
Initial value
0072H
to
0075H
⎯
(disabled)
⎯
⎯
0076H
WREN
Wild register address compare enable register
R/W
00000000B
0077H
WROR
Wild register data test setting register
R/W
00000000B
0078H
⎯
Register bank pointer (RP) ,
Mirror of direct bank pointer (DP)
⎯
⎯
0079H
ILR0
Interrupt level setting register 0
R/W
11111111B
007AH
ILR1
Interrupt level setting register 1
R/W
11111111B
007BH
ILR2
Interrupt level setting register 2
R/W
11111111B
007CH
ILR3
Interrupt level setting register 3
R/W
11111111B
007DH
ILR4
Interrupt level setting register 4
R/W
11111111B
007EH
ILR5
Interrupt level setting register 5
R/W
11111111B
007FH
⎯
(disabled)
⎯
⎯
0F80H
WRARH0
Wild register address setting register (upper byte) ch.0
R/W
00000000B
0F81H
WRARL0
Wild register address setting register (lower byte) ch.0
R/W
00000000B
0F82H
WRDR0
Wild register data setting register ch.0
R/W
00000000B
0F83H
WRARH1
Wild register address setting register (upper byte) ch.1
R/W
00000000B
0F84H
WRARL1
Wild register address setting register (lower byte) ch.1
R/W
00000000B
0F85H
WRDR1
Wild register data setting register ch.1
R/W
00000000B
0F86H
WRARH2
Wild register address setting register (upper byte) ch.2
R/W
00000000B
0F87H
WRARL2
Wild register address setting register (lower byte) ch.2
R/W
00000000B
0F88H
WRDR2
Wild register data setting register ch.2
R/W
00000000B
0F89H
to
0F91H
⎯
(disabled)
⎯
⎯
0F92H
T01CR0
8/16-bit compound timer 01 control status register 0 ch.0
R/W
00000000B
0F93H
T00CR0
8/16-bit compound timer 00 control status register 0 ch.0
R/W
00000000B
0F94H
T01DR
8/16-bit compound timer 01 data register ch.0
R/W
00000000B
0F95H
T00DR
8/16-bit compound timer 00 data register ch.0
R/W
00000000B
0F96H
TMCR0
8/16-bit compound timer 00/01 timer mode control
register ch.0
R/W
00000000B
0F97H
T11CR0
8/16-bit compound timer 11 control status register 0 ch.1
R/W
00000000B
0F98H
T10CR0
8/16-bit compound timer 10 control status register 0 ch.1
R/W
00000000B
(Continued)
DS07-12625-3E
17
MB95R203
(Continued)
Address
Register
abbreviation
Register name
R/W
Initial value
0F99H
T11DR
8/16-bit compound timer 11 data register ch.1
R/W
00000000B
0F9AH
T10DR
8/16-bit compound timer 10 data register ch.1
R/W
00000000B
0F9BH
TMCR1
8/16-bit compound timer 10/11 timer mode control
register ch.1
R/W
00000000B
0F9CH
to
0FBDH
⎯
(disabled)
⎯
⎯
0FBEH
PSSR0
UART/SIO prescaler select register
R/W
00000000B
0FBFH
BRSR0
UART/SIO baud rate setting register
R/W
00000000B
0FC0H
to
0FC2H
⎯
(disabled)
⎯
⎯
0FC3H
AIDRL
A/D input disable register lower
R/W
00000000B
0FC4H
to
0FE3H
⎯
(disabled)
⎯
⎯
0FE4H
CRTH
CR-trimming register upper
R/W
1XXXXXXXB
0FE5H
CRTL
CR-trimming register lower
R/W
000XXXXXB
0FE6H,
0FE7H
⎯
(disabled)
⎯
⎯
0FE8H
SYSC
System control register
R/W
11000-11B
0FE9H
CMCR
Clock monitor control register
R/W
--000000B
0FEAH
CMDR
Clock monitor data register
R/W
00000000B
0FEBH
WDTH
Watchdog ID register upper
R/W
XXXXXXXXB
0FECH
WDTL
Watchdog ID register lower
R/W
XXXXXXXXB
0FEDH
⎯
(disabled)
⎯
⎯
0FEEH
ILSR
Input level select register
R/W
-----0--B
0FEFH
to
0FFFH
⎯
(disabled)
⎯
⎯
• R/W access symbols
R/W : Readable / Writable
R
: Read only
W
: Write only
• Initial value symbols
0 : The initial value of this bit is “0”.
1 : The initial value of this bit is “1”.
X : The initial value of this bit is undefined.
Note : Do not write to the “ (Disabled) ”. Reading the “ (Disabled) ” returns an undefined value.
18
DS07-12625-3E
MB95R203
■ INTERRUPT SOURCE TABLE
Lower
Bit name of
interrupt level
setting register
Priority order of
interrupt sources
of the same level
(occurring simultaneously)
FFFAH
FFFBH
L00 [1 : 0]
High
IRQ01
FFF8H
FFF9H
L01 [1 : 0]
IRQ02
FFF6H
FFF7H
L02 [1 : 0]
IRQ03
FFF4H
FFF5H
L03 [1 : 0]
IRQ04
FFF2H
FFF3H
L04 [1 : 0]
8/16-bit composite timer
ch.0 (Lower)
IRQ05
FFF0H
FFF1H
L05 [1 : 0]
8/16-bit composite timer
ch.0 (Upper)
IRQ06
FFEEH
FFEFH
L06 [1 : 0]
⎯
IRQ07
FFECH
FFEDH
L07 [1 : 0]
⎯
RQ08
FFEAH
FFEBH
L08 [1 : 0]
IRQ09
FFE8H
FFE9H
L09 [1 : 0]
⎯
IRQ10
FFE6H
FFE7H
L10 [1 : 0]
⎯
IRQ11
FFE4H
FFE5H
L11 [1 : 0]
⎯
IRQ12
FFE2H
FFE3H
L12 [1 : 0]
⎯
IRQ13
FFE0H
FFE1H
L13 [1 : 0]
IRQ14
FFDEH
FFDFH
L14 [1 : 0]
IRQ15
FFDCH
FFDDH
L15 [1 : 0]
IRQ16
FFDAH
FFDBH
L16 [1 : 0]
IRQ17
FFD8H
FFD9H
L17 [1 : 0]
8/10-bit A/D converter
IRQ18
FFD6H
FFD7H
L18 [1 : 0]
Timebase timer
IRQ19
FFD4H
FFD5H
L19 [1 : 0]
Watch prescaler
IRQ20
FFD2H
FFD3H
L20 [1 : 0]
IRQ21
FFD0H
FFD1H
L21 [1 : 0]
8/16-bit composite timer
ch.1 (Lower)
IRQ22
FFCEH
FFCFH
L22 [1 : 0]
FRAM (AREA)
IRQ23
FFCCH
FFCDH
L23 [1 : 0]
Vector table
address
Interrupt
request
number
Upper
External interrupt ch.4
IRQ00
External interrupt ch.5
Interrupt source
External interrupt ch.2
External interrupt ch.6
External interrupt ch.3
External interrupt ch.7
UART/SIO (transmit)
UART/SIO (receive)
FRAM (UDEF, PROT)
8/16-bit composite timer
ch.1 (Upper)
⎯
I2C complete/error
I2C stop/AL/wakeup
⎯
⎯
DS07-12625-3E
Low
19
MB95R203
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Parameter
Power supply voltage*1
Input voltage*1
Output voltage
*1
“L” level maximum output current
Symbol
Rating
Min
V
VI1
Vss − 0.3 Vss + 4.0
V
Other than P64, P65*2
VI2
Vss − 0.3 Vss + 6.0
V
P64, P65
VO
Vss − 0.3 Vss + 4.0
V
*2
IOL1
IOL2
⎯
15
⎯
mA
mA
12
ΣIOL
⎯
100
mA
ΣIOLAV
⎯
50
mA
IOH1
IOH2
⎯
−15
−15
⎯
“H” level average current
mA
−4
IOHAV1
mA
−8
IOHAV2
“H” level total maximum output
current
15
4
IOLAV2
“H” level maximum output current
ΣIOH
⎯
−100
mA
ΣIOHAV
⎯
−50
mA
Power consumption
Pd
⎯
320
mW
Operating temperature
TA
−20
+ 70
°C
Tstg
−20
+ 85
°C
“H” level total average output
current
Storage temperature
Remarks
Vss − 0.3 Vss + 4.0
“L” level average current
“L” level total average output
current
Unit
Vcc
IOLAV1
“L” level total maximum output
current
Max
Other than P05, P06, P62 and P63
P05, P06, P62 and P63
Other than P05, P06, P62 and P63
Average output current =
operating current × operating ratio
(1pin)
P05, P06, P62 and P63
Average output current =
operating current × operating ratio
(1pin)
Total average output current =
operating current × operating ratio
(Total of pins)
Other than P05, P06, P62 and P63
P05, P06, P62 and P63
Other than P05, P06, P62 and P63
Average output current =
operating current × operating ratio
(1 pin)
P05, P06, P62 and P63
Average output current =
operating current × operating ratio
(1pin)
Total average output current =
operating current × operating ratio
(Total of pins)
(Continued)
20
DS07-12625-3E
MB95R203
(Continued)
*1 : The parameter is based on VSS = 0.0 V.
*2 : VI1 and Vo should not exceed VCC + 0.3 V. VI1 must not exceed the rating voltage.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
DS07-12625-3E
21
MB95R203
2. Recommended Operating Conditions
(VSS = 0.0 V)
Parameter
Power supply voltage
Operating temperature
Symbol
Vcc
TA
Rating
Unit
Remarks
Min
Max
2.7
3.6
3.0
3.6
2.6
3.6
−20
+70
°C
Other than on-chip debug mode
+5
+35
°C
On-chip debug mode
In normal operating
V
On-chip debug mode
Hold condition in STOP mode
WARNING: The recommended operating conditions are required in order to ensure the normal operation of
the semiconductor device. All of the device's electrical characteristics are warranted when the
device is operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges.
Operation outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented
on the data sheet. Users considering application outside the listed conditions are advised to contact
their representatives beforehand.
22
DS07-12625-3E
MB95R203
3. DC Characteristics
(Vcc = 3.3 V, Vss = 0.0 V, TA = −20 °C to +70 °C)
Parameter
Symbol
Open-drain
output application voltage
“H” level
output voltage
“L” level
output voltage
Condition
Value
Min
Typ
Max
Unit
Remarks
VIH1
P04
*1
0.7 VCC
⎯
VCC + 0.3
V
When CMOS input
level (Hysteresis
input) is selected
VIH2
P64, P65
*1
0.7 VCC
⎯
VSS + 5.5
V
When CMOS input
level (Hysteresis
input) is selected
VIHS1
P00 to P07,
P12,
P62, P63,
PG1, PG2
*1
0.8 VCC
⎯
VCC + 0.3
V
Hysteresis input
VIHS2
P64, P65
*1
0.8 VCC
⎯
VSS + 5.5
V
Hysteresis input
VIHM
PF2
⎯
0.8 VCC
⎯
VCC + 0.3
V
Hysteresis input
VIL
P04, P64,
P65
*1
VSS − 0.3
⎯
0.3 VCC
V
When CMOS input
level (Hysteresis
input) is selected
VILS
P00 to P07,
P12,
P62 to P65,
PG1, PG2
*1
VSS − 0.3
⎯
0.2 VCC
V
Hysteresis input
VILM
PF2
⎯
VSS − 0.3
⎯
0.3 VCC
V
Hysteresis input
VD1
P64, P65
⎯
VSS − 0.3
⎯
VSS + 5.5
V
VD2
PF2, P12
⎯
VSS − 0.3
⎯
0.2 VCC
V
VOH1
Output pins
other than
P05, P06,
P62 to P65,
PF2, P12
IOH = −4.0 mA
2.4
⎯
⎯
V
VOH2
P05, P06,
P62, P63
IOH = −8.0 mA
2.4
⎯
⎯
V
VOL1
Output pins
other than
P05, P06,
P62, P63
IOL = 4.0 mA
⎯
⎯
0.4
V
VOL2
P05, P06,
P62, P63
IOL = 12.0 mA
⎯
⎯
0.4
V
“H” level
input voltage
“L” level
input voltage
Pin name
(Continued)
DS07-12625-3E
23
MB95R203
(Vcc = 3.3 V, Vss = 0.0 V, TA = −20 °C to +70 °C)
Parameter
Input leak
current (Hi-Z
output leak
current)
Symbol
ILI
Pin name
Other than
ports
P64, P65
Condition
Value
Unit
Min
Typ
Max
0.0 V < VI < VCC
−5
⎯
+5
μA
0.0 V < VI <
VSS + 5.5 V
⎯
⎯
+5
μA
Open-drain
output leak
current
ILIOD
P64, P65
Pull-up
resistance
RPULL
P00 to P07,
PG1, PG2
VI = 0.0 V
25
50
100
kΩ
CIN
Other than
Vcc, Vss
f = 1 MHz
⎯
5
15
pF
⎯
6
9
mA
ICC
FCH = 20 MHz,
FMP = 10 MHz
Main clock mode
(divided by 2)
⎯
8
12
mA
ICCS
FCH = 20 MHz,
FMP = 10 MHz
Main sleep mode
(divided by 2)
⎯
3
5
mA
FCL = 32 kHz,
FMPL = 16 kHz
Sub clock mode
(divided by 2)
TA = +25 °C
⎯
30
70
μA
ICCLS
FCL = 32 kHz,
FMPL = 16 kHz
Sub sleep mode
(divided by 2)
TA = +25 °C
⎯
5
40
μA
ICCT
FCL = 32 kHz,
Watch mode
Main stop mode
TA = +25 °C
⎯
3
18
μA
ICCMCR
FCRH = 1 MHz,
FMP = 1 MHz
Main CR clock
mode
⎯
2
⎯
mA
Sub CR clock
mode
(divided by 2)
TA = +25 °C
⎯
80
300
μA
Input
capacitance
ICCL
Power supply
current*2
Vcc
(External
clock
operation)
Vcc
ICCSCR
Remarks
When pull-up
resistance is
disabled
When pull-up
resistance is
enabled
At A/D
conversion
(Continued)
24
DS07-12625-3E
MB95R203
(Continued)
Parameter
(Vcc = 3.3 V, Vss = 0.0 V, TA = −20 °C to +70 °C)
Symbol Pin name
ICCTS
ICCH
Power supply
current*2
Vcc
(External
clock
operation)
ICRH
VCC
ICRL
Condition
Value
Unit
Min
Typ
Max
FCH = 10 MHz,
Timebase timer
mode
TA = +25 °C
⎯
1
3
mA
Sub stop mode
TA = +25 °C
⎯
1
10
μA
Current
consumption of
internal main CR
oscillator
⎯
0.2
0.3
mA
At oscillating
100 kHz current
consumption of
internal sub CR
oscillator
⎯
20
72
μA
Remarks
*1 : P04, P64, P65 can switch the input level to either the “CMOS input level” or “hysteresis input level”.
The switching of the input level can be set by the input level selection register (ILSR) .
*2 : • The power-supply current is determined by the external clock. when Internal CR are selected, the powersupply current will be a value of adding current consumption of internal CR oscillator (ICRL) to the specified
value.
• Refer to “4. AC Characteristics (1) Clock Timing” for FCH and FCL.
• Refer to “4. AC Characteristics (2) Source Clock/Machine Clock” for FMP and FMPL.
DS07-12625-3E
25
MB95R203
4. AC Characteristics
(1) Clock Timing
(Vcc = 3.3 V, Vss = 0.0 V, TA = −20 °C to +70 °C)
Parameter
SymCondiPin name
bol
tion
FCH
Clock frequency
FCRH
Internal CR
oscillation start time
26
10
MHz
When the main
oscillation circuit is used
20
MHz
When the main external
clock is used
Max
X0, X1
1
⎯
X0, X1,
HCLK1,
HCLK2
1
⎯
⎯
When the main internal
CR clock is used
MHz
(3.0 V ≤ VCC ≤ 3.6 V,
+ 5 °C ≤ TA ≤ + 35 °C)
1.05
⎯
32.768
⎯
MHz
When the sub oscillation
circuit is used
⎯
32.768
⎯
kHz
When the sub external
clock is used
⎯
50
100
200
kHz
When the sub internal
CR clock is used
X0, X1
100
⎯
1000
ns
When the main
oscillation circuit is used
X0, X1,
HCLK1,
HCLK2
50
⎯
1000
ns
When the main external
clock is used
tLCYL
X0A, X1A
⎯
30.5
⎯
μs
When using sub clock
tWH1
X0,
HCLK1,
HCLK2
20
⎯
⎯
ns
X0A
⎯
15.2
⎯
μs
When the external clock
is used, the duty ratio
should range between
40% and 60%
tCF
X0, X0A,
HCLK1,
HCLK2
⎯
⎯
5
ns
When the external clock
is used
tCRHWK
⎯
⎯
⎯
10
μs
When the main-internal
CR clock is used
tCRLWK
⎯
⎯
⎯
10
μs
When the sub-internal
CR clock is used
tHCYL
tWL1
tWH2
tWL2
Input clock rise
time and fall time
Remarks
Typ
1
FCRL
Input clock pulse
width
Unit
Min
0.95
FCL
Clock cycle time
Value
tCR
X0A, X1A
⎯
DS07-12625-3E
MB95R203
tHCYL
tWH1
tWL1
tCR
tCF
0.8 VCC 0.8 VCC
X0, HCLK1, HCLK2
0.2 VCC
0.2 VCC
0.2 VCC
• Figure of main clock input port external connection
When using a crystal or
Ceramic oscillator
X0
When using external clock
X1
X0
X1
Open
FCH
FCH
tLCYL
tWH2
tCR
tWL2
tCF
0.8 VCC 0.8 VCC
X0A
0.2 VCC
0.2 VCC
0.2 VCC
• Figure of sub clock input port external connection
When using a crystal
or
Ceramic oscillator
X0A
X1A
FCL
When using external clock
X0A
X1A
Open
FCL
DS07-12625-3E
27
MB95R203
(2) Source Clock/Machine Clock
(Vcc = 3.3 V, Vss = 0.0 V, TA = −20 °C to +70 °C)
Parameter
Source clock
cycle time*1
(Clock before
division)
Symbol
tSCLK
Pin
name
⎯
FSP
Source clock
frequency
⎯
FSPL
Machine clock
cycle time*2
(Minimum
instruction
execution time)
tMCLK
⎯
FMPL
FRAM clock
cycle time*3
(Minimum
instruction
execution time)
tFCLK
Unit
Remarks
Min
Typ
Max
100
⎯
2000
ns
When using main external clock
Min : FCH = 20 MHz, divided by 2
Max : FCH = 1 MHz, divided by 2
⎯
1
⎯
μs
When using main CR oscillation clock
FCRH = 1 MHz
⎯
61
⎯
μs
When using sub oscillation clock
FCL = 32.768 kHz, divided by 2
⎯
20
⎯
μs
When using sub oscillation clock
FCRL = 100 kHz, divided by 2
0.5
⎯
10
MHz When using main oscillation clock
⎯
1
⎯
MHz When using main CR oscillation clock
⎯
16.384
⎯
kHz When using sub oscillation clock
⎯
50
⎯
kHz When using sub CR clock
100
⎯
32000
ns
When using main oscillation clock
Min : FSP = 10 MHz, no division
Max : FSP = 0.5 MHz, divided by 16
1
⎯
16
μs
When using main CR clock
Min : FSP = 1 MHz, no division
Max : FSP = 1 MHz, divided by 16
61
⎯
976.5
μs
When using sub oscillation clock
Min : FSPL = 16.384 kHz, no division
Max : FSPL = 16.384 kHz, divided by 16
20
⎯
320
μs
When using sub CR clock
Min : FSPL = 50 kHz, no division
Max : FSPL = 50 kHz, divided by 16
0.031
⎯
10
MHz When using main oscillation clock
0.0625
⎯
1
MHz When using main CR clock
1.024
⎯
16.384
3.125
⎯
50
300
⎯
96000
ns
When using main oscillation clock
Min : FSP = 10 MHz, divided by 3
Max : FSP = 0.5 MHz, divided by 48
3
⎯
48
μs
When using main CR clock
Min : FSP=1 MHz, divided by 3
Max : FSP=1 MHz, divided by 48
183
⎯
2929.7
μs
When using sub oscillation clock
Min : FSPL = 16.384 kHz, divided by 3
Max : FSPL = 16.384 kHz, divided by 48
60
⎯
960
μs
When using sub CR clock
Min : FSPL = 50 kHz, divided by 3
Max : FSPL = 50 kHz, divided by 48
⎯
FMP
Machine clock
frequency
Value
kHz When using sub oscillation clock
kHz When using sub CR clock
⎯
(Continued)
28
DS07-12625-3E
MB95R203
(Continued)
Parameter
Symbol
Pin
name
FFCLK
FRAM clock
frequency
⎯
FFCLKL
Value
Unit
Remarks
Min
Typ
Max
0.010
⎯
3.3
0.0208
⎯
0.341
⎯
5.461
kHz When using sub oscillation clock
1.042
⎯
16.667
kHz When using sub CR clock
MHz When using main oscillation clock
0.3333 MHz When using main CR clock
*1 : Clock before setting division due to machine clock division ratio selection bit (SYCC : DIV1 and DIV0) .
This source clock is divided by the machine clock division ratio selection bit (SYCC : DIV1 and DIV0) ,
and it becomes the machine clock. Further, the source clock can be selected as follows.
• Main clock divided by 2
• Main CR clock
• Sub clock divided by 2
• Sub CR clock divided by 2
*2 : Operation clock of the microcontroller. Machine clock can be selected as follows.
• Source clock (no division)
• Source clock divided by 4
• Source clock divided by 8
• Source clock divided by 16
*3 : The clock in case of operating code on FRAM, or Read/Write access to FRAM. Its value is machine clock
divided by 3.
• Outline of clock generation block
Divided
by 2
FCH
(main oscillation)
FCRH
(Internal main
CR clock)
FCL
(sub oscillation)
DS07-12625-3E
FCRL
(Internal sub
CR clock)
Divided
by 2
SCLK
(source clock)
Divided
by 2
Clock mode select bit
(SYCC2:RCS1, RCS0)
Division
Circuit
x1
x 1/4
x 1/8
x 1/16
MCLK
(machine clock)
Divided
by 3
FCLK
(FRAM clock)
29
MB95R203
• Operating voltage - Operating frequency (When TA = − 20 °C to + 70 °C)
Operating voltage (V)
3.6
3.3
A/D converter operation range
3.0
2.7
2.4
16 kHz
3 MHz
10 MHz
Source clock frequency (FSP)
30
DS07-12625-3E
MB95R203
(3) External Reset
(Vcc = 3.3 V, Vss = 0.0 V, TA = −20 °C to +70 °C)
Parameter
RST “L” level pulse
width
Value
Symbol
tRSTL
Unit
Remarks
Min
Max
2 tMCLK*1
⎯
ns
At normal operating
Oscillation time of
oscillator*2 + 100
⎯
μs
At stop mode, sub clock mode,
sub sleep mode, and watch
mode
100
⎯
μs
At time-base timer mode
*1 : Refer to “ (2) Source Clock/Machine Clock” for tMCLK.
*2 : Oscillation time of oscillator is the time that the amplitude reaches 90%. In the crystal oscillator, the oscillation
time is between several ms and tens of ms. In ceramic oscillators, the oscillation time is between hundreds of
μs and several ms. In the external clock, the oscillation time is 0 ms.
• At normal operating
tRSTL
RST
0.2 VCC
0.2 VCC
• At stop mode, sub clock mode, sub sleep mode, watch mode, and power-on
RST
90% of
amplitude
tRSTL
0.2 VCC
0.2 VCC
X0
Internal
operating
clock
100 μs
Oscillation time of Oscillation stabilization wait time
oscillator
Internal reset
DS07-12625-3E
Execute instruction
31
MB95R203
(4) Power-on Reset
(Vss = 0.0 V, TA = −20 °C to +70 °C)
Parameter
Symbol
Conditions
Power supply rising time
tR
Power supply cutoff time
tOFF
tR
Value
Unit
Min
Max
⎯
⎯
50
ms
⎯
1
⎯
ms
Remarks
Waiting time until
power-on
tOFF
2.5 V
VCC
0.2 V
0.2 V
0.2 V
Note: Sudden change of power supply voltage may activate the power-on reset function. When changing power
supply voltages during operation, set the slope of rising within 30 mV/ms as shown below.
VCC
Limiting the slope of rising within
30 mV/ms is recommended.
2.6 V
Hold Condition in stop mode
VSS
32
DS07-12625-3E
MB95R203
(5) Peripheral Input Timing
(Vcc = 3.3 V, Vss = 0.0 V, TA = −20 °C to +70 °C)
Parameter
Symbol
Pin name
Peripheral input “H” pulse
tILIH
Peripheral input “L” pulse
tIHIL
INT02 to INT07,
EC0, EC1
Value
Unit
Min
Max
2 tMCLK*
⎯
ns
2 tMCLK*
⎯
ns
* : Refer to “ (2) Source Clock/Machine Clock” for tMCLK.
tILIH
tIHIL
0.8 VCC 0.8 VCC
INT02 to INT07,
EC0, EC1
DS07-12625-3E
0.2 VCC
0.2 VCC
33
MB95R203
(6) UART/SIO, Serial I/O Timing
(Vcc = 3.3 V, Vss = 0.0 V, TA = −20 °C to +70 °C)
Parameter
Symbol
Pin name
Serial clock cycle time
tSCYC
UCK
UCK ↓ → UO time
tSLOV
UCK, UO
Valid UI → UCK ↑
tIVSH
UCK,UI
UCK ↑→ valid UI hold time
tSHIX
Serial clock “H” pulse width
Value
Conditions
Unit
Min
Max
4 tMCLK*
⎯
ns
−190
+190
ns
2 tMCLK*
⎯
ns
UCK, UI
2 tMCLK*
⎯
ns
tSHSL
UCK
4 tMCLK*
⎯
ns
Serial clock “L” pulse width
tSLSH
UCK
4 tMCLK*
⎯
ns
UCK ↓ → UO time
tSLOV
UCK, UO
0
190
ns
Valid UI → UCK ↑
tIVSH
UCK, UI
2 tMCLK*
⎯
ns
UCK ↑→ valid UI hold time
tSHIX
UCK, UI
2 tMCLK*
⎯
ns
Internal clock
operation output pin :
CL = 80 pF + 1 TTL.
External clock
operation output pin :
CL = 80 pF + 1 TTL.
* : Refer to “ (2) Source Clock/Machine Clock” for details on tMCLK.
• Internal shift clock mode
tSCYC
UCK
2.4 V
0.8 V
0.8 V
tSLOV
UO
2.4 V
0.8 V
tIVSH
UI
tSHIX
0.8 VCC 0.8 VCC
0.2 VCC 0.2 VCC
• External shift clock mode
tSLSH
tSHSL
0.8 VCC 0.8 VCC
UCK
0.2 VCC 0.2 VCC
tSLOV
UO
2.4 V
0.8 V
tIVSH
UI
34
tSHIX
0.8 VCC 0.8 VCC
0.2 VCC 0.2 VCC
DS07-12625-3E
MB95R203
(7) I2C Timing
(Vcc = 3.3 V, Vss = 0.0 V, TA = −20 °C to +70 °C)
Value
Parameter
Symbol
Pin
name
Conditions
Standardmode
Fast-mode
Min
Max
Min
Max
Unit
SCL clock frequency
tSCYC
SCL
0
100
0
400
kHz
(Repeat) Start condition hold time
SDA ↓ → SCL ↓
tHD;STA
SCL
SDA
4.0
⎯
0.6
⎯
μs
SCL clock “L” width
tLOW
SCL
4.7
⎯
1.3
⎯
μs
SCL clock “H” width
tHIGH
SCL
4.0
⎯
0.6
⎯
μs
(Repeat) Start condition setup time
SCL ↑ → SDA ↓
tSU;STA
SCL
SDA
4.7
⎯
0.6
⎯
μs
Data hold time SCL ↓ → SDA ↓ ↑
tHD;DAT
SCL
SDA
0
3.45*2
0
0.9*3
μs
Data setup time SDA ↓ ↑ → SCL ↑
tSU;DAT
SCL
SDA
0.25
⎯
0.1
⎯
μs
Stop condition setup time
SCL ↑ → SDA ↓
tSU;STO
SCL
SDA
4.0
⎯
0.6
⎯
μs
tBUF
SCL
SDA
4.7
⎯
1.3
⎯
μs
Bus free time between stop
condition and start condition
R = 1.7 kΩ,
C = 50 pF*1
*1 : R, C : Pull-up resistance and load capacitance of the SCL and SDA lines.
*2 : The maximum value of tHD;DAT is applicable only if the device does not extend the “L” width (tLOW) of the SCL signal.
*3 : A fast-mode I2C-bus device can be used in a standard-mode I2C-bus system, but the requirement tSU;DAT ≥ 250
ns must then be met.
tWAKEUP
SDA
tLOW
tHD;DAT
tHIGH
tHD;STA
tBUF
SCL
tHD;STA
DS07-12625-3E
tSU;DAT
tSU;STA
tSU;STO
35
MB95R203
(Vcc = 3.3 V, Vss = 0.0 V, TA = −20 °C to +70 °C)
Symbol
Pin
name
SCL clock
“L” width
tLOW
SCL clock
“H” width
tHIGH
Parameter
Conditions
Value*2
Unit
Remarks
Min
Max
SCL
(2 + nm / 2) tMCLK
− 20
⎯
ns
Master mode
SCL
(nm / 2) tMCLK −
20
(nm / 2) tMCLK +
20
ns
Master mode
ns
Master mode
maximum value is
applied when m, n
= 1, 8.
Otherwise, the minimum value is applid.
(−1 + nm / 2)
tMCLK − 20
(−1 + nm / 2)
tMCLK + 20
Start condition
hold time
tHD;STA
SCL
SDA
Stop condition
setup time
tSU;STO
SCL
SDA
(1 + nm / 2) tMCLK (1 + nm / 2) tMCLK
− 20
+ 20
ns
Master mode
Start condition
setup time
tSU;STA
SCL
SDA
(1 + nm / 2) tMCLK (1 + nm / 2) tMCLK
− 20
+ 20
ns
Master mode
Bus free time
between stop
condition and
start condition
tBUF
SCL
SDA
(2 nm + 4) tMCLK
− 20
⎯
ns
Data hold time
tHD;DAT
SCL
SDA
3 tMCLK − 20
⎯
ns
Master mode
ns
Master mode
When assuming
that “L” of SCL is
not extended, the
minimum value is
applied to first bit of
continuous data.
Otherwise, the
maximum value is
applied.
Data setup time
tSU;DAT
SCL
SDA
R = 1.7 kΩ,
C = 50 pF*1
(−2 + nm / 2)
tMCLK − 20
(−1 + nm / 2)
tMCLK + 20
tSU;INT
SCL
(nm / 2) tMCLK −
20
(1 + nm / 2) tMCLK
+ 20
ns
Minimum value is
applied to interrupt
at 9th SCL↓.
Maximum value is
applied to interrupt
at 8th SCL↓.
SCL clock
“L” width
tLOW
SCL
4 tMCLK − 20
⎯
ns
At reception
SCL clock
“H” width
tHIGH
SCL
4 tMCLK − 20
⎯
ns
At reception
tHD;STA
SCL
SDA
4 tMCLK − 20
⎯
ns
Undetected when 1
tMCLK is used at reception
Setup time
between
cleaning
interrupt and
SCL rising
Start condition
detection
(Continued)
36
DS07-12625-3E
MB95R203
(Continued)
(Vcc = 3.3 V, Vss = 0.0 V, TA = −20 °C to +70 °C)
Symbol
Pin
name
Stop condition
detection
tSU;STO
Restart condition
detection condition
Parameter
Conditions
Value*2
Unit
Remarks
⎯
ns
Undetected when 1 tMCLK is used at reception
2 tMCLK − 20
⎯
ns
Undetected when 1 tMCLK is used at reception
SCL
SDA
2 tMCLK − 20
⎯
ns
During reception
tHD;DAT
SCL
SDA
2 tMCLK − 20
⎯
ns
In slave transmission
mode
Data setup time
tSU;DAT
SCL
SDA
tLOW − 3 tMCLK −
20
⎯
ns
In slave transmission
mode
Data hold time
tHD;DAT
SCL
SDA
0
⎯
ns
During reception
Data setup time
tSU;DAT
SCL
SDA
tMCLK − 20
⎯
ns
During reception
tWAKEUP
SCL
SDA
Oscillation stabilization wait
time + 2 tMCLK −
20
⎯
ns
Min
Max
SCL
SDA
4 tMCLK − 20
tSU;STA
SCL
SDA
Bus free time
tBUF
Data hold time
SDA ↓ → SCL ↑
(when using wakeup
function)
R = 1.7 kΩ,
C = 50 pF*1
*1 : R, C : Pull-up resistance and load capacitance of the SCL and SDA lines.
*2 : • Refer to “ (2) Source Clock/Machine Clock” for details on tMCLK.
• m is the CS4 and CS3 bits (bit 4 and bit 3) of the I2C clock control register (ICCR0) .
• n is the CS2 to CS0 bits (bit 2 to bit0) of the I2C clock control register (ICCR0) .
• The actual I2C timing is determined by the machine (tMCLK) and the values of m and n configured in bits
CS4 to CS0 of the I2C clock control register (ICCR0) .
• Standard-mode :
m and n can be set in the range : 0.9 MHz < tMCLK (machine clock) < 10 MHz.
The machine clock to be used is determined by the settings of m and n as follows.
(m, n) = (1, 8)
: 0.9 MHz < tMCLK ≤ 1 MHz
(m, n) = (1, 22) , (5, 4) , (6, 4) , (7, 4) , (8, 4)
: 0.9 MHz < tMCLK ≤ 2 MHz
(m, n) = (1, 38) , (5, 8) , (6, 8) , (7, 8) , (8, 8)
: 0.9 MHz < tMCLK ≤ 4 MHz
(m, n) = (1, 98)
: 0.9 MHz < tMCLK ≤ 1 MHz
• Fast-mode :
m and n can be set in the range : 3.3 MHz < tMCLK (machine clock) < 10 MHz.
The machine clock to be used is determined by the settings of m and n as follows.
(m, n) = (1, 8)
: 3.3 MHz < tMCLK ≤ 4 MHz
(m, n) = (1, 22) , (5, 4)
: 3.3 MHz < tMCLK ≤ 8 MHz
(m, n) = (6, 4)
: 3.3 MHz < tMCLK ≤ 10 MHz
DS07-12625-3E
37
MB95R203
(8) Low Voltage Detection
(VSS = 0.0 V, TA = −20 °C to +70 °C) )
Parameter
Symbol
Value
Min
Typ
Max
Unit
Remarks
Release voltage
V1DL+
2.7
2.8
2.9
V
At power-supply rise
Detection voltage
V1DL−
2.6
2.7
2.8
V
At power-supply fall
Hysteresis width
V1HYS
70
100
⎯
mV
Release voltage
V2DL+
2.8
2.9
3.0
V
At power-supply rise
Detection voltage
V2DL−
2.7
2.8
2.9
V
At power-supply fall
Hysteresis width
V2HYS
70
100
⎯
mV
Power-supply start voltage
Voff
⎯
⎯
2.2
V
Power-supply end voltage
Von
3.3
⎯
⎯
V
0.3
⎯
⎯
μs
Slope of power supply that
reset release signal generates
⎯
200
⎯
μs
Slope of power supply that
reset release signal generates
within rating (V1DL+, V2DL+)
0.3
⎯
⎯
μs
Slope of power supply that
reset detection signal generates
⎯
200
⎯
μs
Slope of power supply that
reset detection signal generates
within rating (V1DL−, V2DL−)
Low voltage
detection reset
FRAM power
supply monitor
Power-supply voltage
change time
(at power supply rise)
tr
Power-supply voltage change
time
(at power supply fall)
tf
Reset release delay time
td1
⎯
⎯
300
μs
Reset detection delay time
td2
⎯
⎯
20
μs
38
DS07-12625-3E
MB95R203
VCC
Von
Voff
time
tr
tf
VDL+
VHYS
VDL-
Internal reset
signal
time
td2
DS07-12625-3E
td1
39
MB95R203
5. A/D Converter
(1) A/D Converter Electrical Characteristics
(Vcc = 2.7 V to 3.6 V, Vss = 0.0 V, TA = −20 °C to +70 °C)
Parameter
Symbol
Value
Unit
Min
Typ
Max
Resolution
⎯
⎯
10
bit
Total error
−3.0
⎯
+3.0
LSB
−2.5
⎯
+2.5
LSB
−1.9
⎯
+1.9
LSB
Linearity error
⎯
Differential linear
error
Zero transition
voltage
VOT
VSS − 1.5 LSB VSS + 0.5 LSB VSS + 2.5 LSB
V
Full-scale transition
voltage
VFST
VCC − 3.5 LSB VCC − 1.5 LSB VCC + 0.5 LSB
V
Compare time
⎯
0.6
⎯
140
μs
Sampling time
⎯
0.4
⎯
∞
μs
Analog input current
IAIN
−0.3
⎯
+0.3
μA
Analog input voltage
VAIN
VSS
⎯
VCC
V
40
Remarks
3.0 V ≤ Vcc ≤ 3.6 V
At external impedance
< 1.8 kΩ
DS07-12625-3E
MB95R203
(2) Notes on Using A/D Converter
• About the external impedance of analog input and its sampling time
A/D converter with sample and hold circuit. If the external impedance is too high to keep sufficient sampling
time, the analog voltage charged to the internal sample and hold capacitor is insufficient, adversely affecting
A/D conversion precision. Therefore, to satisfy the A/D conversion precision standard, consider the relationship
between the external impedance and minimum sampling time and either adjust the register value and operating
frequency or decrease the external impedance so that the sampling time is longer than the minimum value. Also,
if the sampling time cannot be sufficient, connect a capacitor of about 0.1 μF to the analog input pin.
• Analog input equivalent circuit
Analog input
Comparator
R
C
During sampling : ON
2.7 V ≤ Vcc ≤ 3.6 V : R =: 1.7 kΩ (Max) , C =: 14.5 pF (Max)
Note : The values are reference values.
• The relationship between external impedance and minimum sampling time.
[External impedance = 0 kΩ to 20 kΩ]
100
90
80
70
60
50
40
30
20
10
0
0
5
10
15
20
25
30
35
40
External impedance [kΩ]
External impedance [kΩ]
[External impedance = 0 kΩ to 100 kΩ]
20
18
16
14
12
10
8
6
4
2
0
Minimum sampling time [μs]
0
1
2
3
Minimum sampling time [μs]
4
• About errors
|VCC − VSS| becomes smaller, values of relative errors grow larger.
DS07-12625-3E
41
MB95R203
(3) Definition of A/D Converter Terms
• Resolution
The level of analog variation that can be distinguished by the A/D converter.
When the number of bits is 10, analog voltage can be divided into 210 = 1024.
• Linearity error (unit : LSB)
The deviation between the value along a straight line connecting the zero transition point
(“00 0000 0000” ←→ “00 0000 0001”) of a device and the full-scale transition point
(“11 1111 1111” ←→ “11 1111 1110”) compared with the actual conversion values obtained.
• Differential linear error (Unit : LSB)
Deviation of input voltage, which is required for changing output code by 1 LSB, from an ideal value.
• Total error (unit : LSB)
Difference between actual and theoretical values, caused by a zero transition error, full-scale transition error,
linearity error, quantum error, and noise.
Ideal I/O characteristics
Total error
VFST
3FF
3FF
3FE
1.5 LSB
3FD
004
VOT
003
002
Digital output
Digital output
3FE
Actual conversion
characteristic
{1 LSB × (N − 1) + 0.5 LSB}
3FD
004
003
002
1 LSB
VNT
Actual conversion
characteristic
Ideal characteristics
001
001
0.5 LSB
VSS
1 LSB =
Analog input
VCC − VSS
1024
(V)
VCC
VSS
Analog input
VCC
Total error of VNT − {1 LSB × (N − 1) + 0.5 LSB}
=
[LSB]
digital output N
1 LSB
N : A/D converter digital output value
VNT : A voltage at which digital output transits from (N - 1) to N
(Continued)
42
DS07-12625-3E
MB95R203
(Continued)
Full-scale transition error
Zero transition error
Ideal
characteristics
004
3FF
Digital output
Digital output
Actual conversion
characteristic
003
Ideal
characteristics
002
Actual conversion
characteristic
Actual conversion
characteristic
3FE
VFST
(measurement
value)
3FD
Actual conversion
characteristic
001
3FC
VOT (measurement value)
VSS
VCC
VSS
VCC
Analog input
Analog input
Differential linear error
Linearity error
Actual conversion
characteristic
3FF
N+1
3FE
{1 LSB × N + VOT}
3FD
VFST
(measurement value)
VNT
004
Actual conversion
characteristic
003
Digital output
Digital output
Ideal characteristics
Actual conversion
characteristic
V (N+1) T
N
N-1
VNT
Actual conversion
characteristic
Ideal characteristics
002
N-2
001
VOT (measurement value)
VSS
Analog input
VCC
Linearity error in = VNT − {1 LSB × N + VOT}
1 LSB
digital output N
VSS
Analog input
Differential linear error = V (N + 1) T − VNT
1 LSB
In digital output N
VCC
−1
N : A/D converter digital output value
VNT : A voltage at which digital output transits from (N - 1) to N.
VOT (Ideal value) = VSS + 0.5 LSB [V]
VFST (Ideal value) = VCC − 2.0 LSB [V]
DS07-12625-3E
43
MB95R203
6. FRAM Characteristics
Parameter
Number of read/write cycle
44
Value
Min
Typ
Max
1010
1011
⎯
Unit
Remarks
cycle
DS07-12625-3E
MB95R203
■ EXAMPLE CHARACTERISTICS
• Power supply current and temperature
ICC − VCC
TA = + 25 °C, FMP = 2, 3, 8, 10 MHz (divided by 2)
Main clock mode, at external clock operating
ICC − TA
VCC = 3.6 V, FMP = 10 MHz (divided by 2)
Main clock mode, at external clock operating
10
10
8
8
10 MHz
8 MHz
4
6
ICC [mA]
ICC [mA]
6
4
4 MHz
2
2
2 MHz
0
0
2.5
3
3.5
4
-40
0
VCC [V]
ICCS − TA
VCC = 3.6 V, FMP = 10 MHz(divided by 2)
Main sleep mode, at external clock operating
8
8
6
6
ICCS [mA]
10
ICCS [mA]
10
4
4
10 MHz
8 MHz
2
2
4 MHz
2 MHz
0
3
3.5
0
-40
4
0
ICCL − VCC
TA = + 25 °C, FMPL = 16 kHz (divided by 2)
Sub clock mode, at external clock operating
+80
ICCL − TA
VCC = 3.6 V, FMPL = 16 kHz (divided by 2)
Sub clock mode, at external clock operating
80
80
60
60
ICCL [μA]
ICCL [μA]
+40
TA [°C]
VCC [V]
40
40
20
20
0
2.5
+80
TA [°C]
ICCS − VCC
TA = + 25 °C, FMP = 2, 3, 8, 10 MHz (divided by 2)
Main sleep mode, at external clock operating
2.5
+40
3
3.5
VCC [V]
4
0
-40
0
+40
+80
TA [°C]
(Continued)
DS07-12625-3E
45
MB95R203
ICCLS − TA
VCC = 3.6 V, FMPL = 16 kHz (divided by 2)
Sub sleep mode, at external clock operating
50
50
40
40
ICCLS [μA]
ICCLS [μA]
ICCLS − VCC
TA = + 25 °C, FMPL = 16 kHz (divided by 2)
Sub sleep mode, at external clock operating
30
20
30
20
10
10
0
0
2.5
3
3.5
-40
4
0
VCC [V]
ICCT
VCC = 3.6 V, FMPL = 16 kHz (divided by 2)
Clock mode, at external clock operating
20
20
15
15
ICCT [μA]
ICCT [μA]
+80
TA [°C]
ICCT − VCC
TA = + 25 °C, FMPL = 16 kHz (divided by 2)
Clock mode, at external clock operating
10
10
5
5
0
0
2.5
3
3.5
-40
4
0
VCC [V]
1.5
1.5
1
10MHz
8MHz
4MHz
2MHz
ICTS [μA]
2
0
1
0.5
0
-40
VCC [V]
+80
ICTS − TA
VCC = 3.6 V, FMP = 10 kHz (divided by 2)
Time-base timer mode, at external clock operating
2
0.5
+40
TA [°C]
ICTS − VCC
TA = + 25 °C, FMP = 2, 4, 8, 10 MHz (divided by 2)
Time-base timer mode, at external clock operating
ICCTS [mA]
+40
0
+40
+80
TA [°C]
(Continued)
46
DS07-12625-3E
MB95R203
(Continued)
ICCH − TA
VCC = 3.6 V, FMPL = (stop)
Sub stop mode, at external clock stopping
20
20
15
15
ICCH [μA]
ICCH [μA]
ICCH − VCC
TA = + 25 °C, FMPL = (stop)
Sub stop mode, at external clock stopping
10
10
5
5
0
2.5
3
3.5
0
-40
4
0
VCC [V]
+40
+80
TA [°C]
2
2
1.5
1.5
ICCMCR [mA]
ICCMCR [mA]
ICCMCR − VCC
ICCMCR − TA
TA = + 25 °C, FMP = 1 MHz (No divided)
VCC = 3.6 V, FMP = 1 MHz (No divided)
Main clock mode, at internal main CR clock operating Main clock mode, at internal main CR clock operating
1
1
0.5
0.5
0
0
2.5
3
3.5
4
-40
0
VCC [V]
ICCSCR − VCC
TA = + 25 °C, FMPL = 50 kHz (divided by 2)
Sub clock mode, at internal sub CR clock operating
+80
ICCSCR − TA
VCC = 3.6 V, FMPL = 50 kHz (divided by 2)
Sub clock mode, at internal sub CR clock operating
200
200
150
150
ICCSCR [μA]
ICCSCR [μA]
+40
TA [°C]
100
100
50
50
0
0
2.5
3
3.5
VCC [V]
DS07-12625-3E
4
-40
0
+40
+80
TA [°C]
47
MB95R203
• Input voltage
VIHI1, VIH2, VIHS1, VIHS2, VIHM − VCC and
VIL, VILS, VILM − VCC
TA = + 25 °C
3.5
3
VIH / VIL [V]
2.5
VIH
2
VIL
1.5
1
0.5
0
2.5
3
3.5
4
VCC [V]
48
DS07-12625-3E
MB95R203
• Output voltage
(VCC − VOH1) − IOH
TA = + 25 °C
VOL1 − IOL
TA = + 25 °C
1.000
1.000
VCC
0.800
2.7 V
3.0 V
3.3 V
3.6 V
0.600
0.400
VCC
VOL1 [V]
VCC-VOH1 [V]
0.800
0.200
0.600
2.7 V
3.0 V
3.3 V
3.6 V
0.400
0.200
0.000
0.000
0
-2
-4
-6
IOH [mA]
-8
-10
0
2
6
8
10
12
IOL [mA]
(VCC − VOH2) − IOH
TA = + 25 °C
VOL2 − IOL
TA = + 25 °C
1.000
1.000
VCC
2.7 V
3.0 V
3.3 V
3.6 V
0.600
0.400
VCC
0.800
VOL2 [V]
0.800
VCC-VOH2 [V]
4
2.7 V
3.0 V
3.3 V
3.6 V
0.600
0.400
0.200
0.200
0.000
0.000
0
DS07-12625-3E
-2
-4
-6
IOH [mA]
-8
-10
0
2
4
6
8
10
12
IOL [mA]
49
MB95R203
• Pull-up
RPULL − VCC
TA = + 25 °C
80
RPULL [kΩ]
60
40
20
0
2.5
3
3.5
4
VCC [V]
50
DS07-12625-3E
MB95R203
■ ORDERING INFORMATION
Part number
Package
MB95R203P-G-SH-JNE2
24-pin plastic SDIP
(DIP-24P-M07)
MB95R203PF-G-JNE2
20-pin plastic SOP
(FPT-20P-M09)
DS07-12625-3E
Remarks
51
MB95R203
■ PACKAGE DIMENSIONS
24-pin plastic DIP
Lead pitch
1.778 mm
Package width ×
package length
6.40 mm × 22.86 mm
Sealing method
Plastic mold
Mounting height
4.80 mm Max
(DIP-24P-M07)
24-pin plastic DIP
(DIP-24P-M07)
Note 1) Pins width and pins thickness include plating thickness.
Note 2) Pins width do not include tie bar cutting remainder.
Note 3) # : These dimensions do not include resin protrusion.
#22.86±0.10(.900±.004)
24
INDEX
13
BTM E-MARK
6.40±0.10
(.252±.004)
1
7.62(.300)
TYP.
12
0.50(.020)
MIN
4.80(.189)MAX
+0.10
+0.20
0.25 –0.04
+.008
+.004
3.00 –0.30 .118 –.012
1.778(.070)
C
.010 –.002
1.00±0.10
(.039±.004)
+0.09
0.43 –0.04
+.004
.017 –.002
2008 FUJITSU MICROELECTRONICS LIMITED D24066S-c-1-1
Dimensions in mm (inches).
Note: The values in parentheses are reference values
Please confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/package/en-search/
(Continued)
52
DS07-12625-3E
MB95R203
(Continued)
20-pin plastic SOP
Lead pitch
1.27 mm
Package width ×
package length
7.50 mm × 12.70 mm
Lead shape
Gullwing
Lead bend
direction
Normal bend
Sealing method
Plastic mold
Mounting height
2.65 mm Max
(FPT-20P-M09)
20-pin plastic SOP
(FPT-20P-M09)
Note 1) Pins width and pins thickness include plating thickness.
Note 2) Pins width do not include tie bar cutting remainder.
Note 3) # : These dimensions do not include resin protrusion.
0.25
#12.70±0.10(.500±.004)
+0.07
–0.02
+.003
.010 –.001
20
11
BTM E-MARK
+0.40
#7.50±0.10 10.2 –0.20
(.295±.004) .402 +.016
–.008
INDEX
Details of "A" part
+0.13
2.52 –0.17
(Mounting height)
+.005
.099 –.007
1
"A"
10
1.27(.050)
0.40
.016
+0.09
–0.05
+.004
–.002
0.25(.010)
M
0~8°
+0.47
0.80 –0.30
+.019
.031 –.012
0.20±0.10
(.008±.004)
(Stand off)
0.10(.004)
C
2008 FUJITSU MICROELECTRONICS LIMITED F20030S-c-1-1
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Please confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/package/en-search/
DS07-12625-3E
53
MB95R203
■ MAIN CHANGES IN THIS EDITION
Page
Section
⎯
⎯
Change Results
Preliminary Data Sheet → Data Sheet
■ PRODUCT OVERVIEW
Corrected number of read/write cycles for FRAM.
1011 times →
(Min)1010 times (Typ)1011 times
9
■ I/O CIRCUIT TYPE
Corrected the remarks of Type G.
CMOS input → CMOS output
12
■ NOTES ON DEBUG
Corrected the address.
F555H → F554H
■ I/O MAP
15
Corrected the register abbreviation and the register name for
address 000BH.
WTCR → WPCR
Watch timer control register →
Watch prescaler control register
17
Changed the register name for address 0F89H, 0F8AH, and
0F8BH to (disabled).
4
24
■ ELECTRICAL CHARACTERISTICS
3. DC Characteristics
Added “TA = + 25 °C” to the condition for “Power supply
current (ICCLS)”.
32
4. AC Characteristics
(4) Power-on Reset
Corrected the voltage for “Hold Condition in stop mode”.
2.3 V → 2.6 V
45 to 50 ■ EXAMPLE CHARACTERISTICS
Added the section.
The vertical lines marked in the left side of the page show the changes.
54
DS07-12625-3E
MB95R203
MEMO
DS07-12625-3E
55
MB95R203
FUJITSU MICROELECTRONICS LIMITED
Shinjuku Dai-Ichi Seimei Bldg., 7-1, Nishishinjuku 2-chome,
Shinjuku-ku, Tokyo 163-0722, Japan
Tel: +81-3-5322-3329
http://jp.fujitsu.com/fml/en/
For further information please contact:
North and South America
FUJITSU MICROELECTRONICS AMERICA, INC.
1250 E. Arques Avenue, M/S 333
Sunnyvale, CA 94085-5401, U.S.A.
Tel: +1-408-737-5600 Fax: +1-408-737-5999
http://www.fma.fujitsu.com/
Asia Pacific
FUJITSU MICROELECTRONICS ASIA PTE. LTD.
151 Lorong Chuan,
#05-08 New Tech Park 556741 Singapore
Tel : +65-6281-0770 Fax : +65-6281-0220
http://www.fmal.fujitsu.com/
Europe
FUJITSU MICROELECTRONICS EUROPE GmbH
Pittlerstrasse 47, 63225 Langen, Germany
Tel: +49-6103-690-0 Fax: +49-6103-690-122
http://emea.fujitsu.com/microelectronics/
FUJITSU MICROELECTRONICS SHANGHAI CO., LTD.
Rm. 3102, Bund Center, No.222 Yan An Road (E),
Shanghai 200002, China
Tel : +86-21-6146-3688 Fax : +86-21-6335-1605
http://cn.fujitsu.com/fmc/
Korea
FUJITSU MICROELECTRONICS KOREA LTD.
206 Kosmo Tower Building, 1002 Daechi-Dong,
Gangnam-Gu, Seoul 135-280, Republic of Korea
Tel: +82-2-3484-7100 Fax: +82-2-3484-7111
http://kr.fujitsu.com/fmk/
FUJITSU MICROELECTRONICS PACIFIC ASIA LTD.
10/F., World Commerce Centre, 11 Canton Road,
Tsimshatsui, Kowloon, Hong Kong
Tel : +852-2377-0226 Fax : +852-2376-3269
http://cn.fujitsu.com/fmc/en/
Specifications are subject to change without notice. For further information please contact each office.
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with sales representatives before ordering.
The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose
of reference to show examples of operations and uses of FUJITSU MICROELECTRONICS device; FUJITSU MICROELECTRONICS
does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating
the device based on such information, you must assume any responsibility arising out of such use of the information.
FUJITSU MICROELECTRONICS assumes no liability for any damages whatsoever arising out of the use of the information.
Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use
or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU MICROELECTRONICS
or any third party or does FUJITSU MICROELECTRONICS warrant non-infringement of any third-party's intellectual property right or
other right by using such information. FUJITSU MICROELECTRONICS assumes no liability for any infringement of the intellectual
property rights or other rights of third parties which would result from the use of information contained herein.
The products described in this document are designed, developed and manufactured as contemplated for general use, including without
limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured
as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to
the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear
facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon
system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite).
Please note that FUJITSU MICROELECTRONICS will not be liable against you and/or any third party for any claims or damages arising
in connection with above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current
levels and other abnormal operating conditions.
Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations of
the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws.
The company names and brand names herein are the trademarks or registered trademarks of their respective owners.
Edited: Sales Promotion Department