SEMICONDUCTOR TECHNICAL DATA The MC14522B BCD counter and the MC14526B binary counter are constructed with MOS P–channel and N–channel enhancement mode devices in a monolithic structure. These devices are presettable, cascadable, synchronous down counters with a decoded “0” state output for divide–by–N applications. In single stage applications the “0” output is applied to the Preset Enable input. The Cascade Feedback input allows cascade divide–by–N operation with no additional gates required. The Inhibit input allows disabling of the pulse counting function. Inhibit may also be used as a negative edge clock. These complementary MOS counters can be used in frequency synthesizers, phase–locked loops, and other frequency division applications requiring low power dissipation and/or high noise immunity. • Supply Voltage Range = 3.0 Vdc to 18 Vdc • Logic Edge–Clocked Design — Incremented on Positive Transition of Clock or Negative Transition of Inhibit • Asynchronous Preset Enable • Capable of Driving Two Low–power TTL Loads or One Low–power Schottky TTL Load Over the Rated Temperature Range ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ MAXIMUM RATINGS* (Voltages Referenced to VSS) Parameter Symbol VDD DC Supply Voltage Value Unit – 0.5 to + 18.0 V L SUFFIX CERAMIC CASE 620 P SUFFIX PLASTIC CASE 648 DW SUFFIX SOIC CASE 751G ORDERING INFORMATION MC14XXXBCP MC14XXXBCL MC14XXXBDW Plastic Ceramic SOIC TA = – 55° to 125°C for all packages. Vin, Vout Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V Iin, Iout Input or Output Current (DC or Transient), per Pin ± 10 mA PD Power Dissipation, per Package† 500 mW Q3 1 16 VDD Tstg Storage Temperature – 65 to + 150 _C P3 2 15 Q2 260 _C TL Lead Temperature (8–Second Soldering) * Maximum Ratings are those values beyond which damage to the device may occur. †Temperature Derating: Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C FUNCTION TABLE Inputs Output Clock Reset Inhibit X X X H H H X X X L H X L L H L H H Asynchronous reset* Asynchronous reset Asynchronous reset X L X H X L Asynchronous preset H L L L L L X X L L Decrement inhibited Decrement inhibited L L L L L L L L L L L L L L L L L No change** (inactive edge) No change** (inactive edge) Decrement** Decrement** H L “0” PE 3 14 P2 INHIBIT 4 13 CF P0 5 12 “0” CLOCK 6 11 P1 Q0 7 10 RESET VSS 8 9 Q1 Resulting Function Preset Enable H Cascade Feedback PIN ASSIGNMENT This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high–impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS (Vin or Vout) VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. v v X = Don’t Care NOTES: * Output “0” is low when reset goes high only it PE and CF are low. ** Output “0” is high when reset is low, only if CF is high and count is 0000. REV 3 1/94 MOTOROLA Motorola, Inc. 1995 CMOS LOGIC DATA MC14522B MC14526B 1 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS) Characteristic Output Voltage Vin = VDD or 0 Symbol – 55_C 25_C 125_C VDD Vdc Min Max Min Typ # Max Min Max Unit “0” Level VOL 5.0 10 15 — — — 0.05 0.05 0.05 — — — 0 0 0 0.05 0.05 0.05 — — — 0.05 0.05 0.05 Vdc “1” Level VOH 5.0 10 15 4.95 9.95 14.95 — — — 4.95 9.95 14.95 5.0 10 15 — — — 4.95 9.95 14.95 — — — Vdc 5.0 10 15 — — — 1.5 3.0 4.0 — — — 2.25 4.50 6.75 1.5 3.0 4.0 — — — 1.5 3.0 4.0 5.0 10 15 3.5 7.0 11 — — — 3.5 7.0 11 2.75 5.50 8.25 — — — 3.5 7.0 11 — — — 5.0 5.0 10 15 – 3.0 – 0.64 – 1.6 – 4.2 — — — — – 2.4 – 0.51 – 1.3 – 3.4 – 4.2 – 0.88 – 2.25 – 8.8 — — — — – 1.7 – 0.36 – 0.9 – 2.4 — — — — IOL 5.0 10 15 0.64 1.6 4.2 — — — 0.51 1.3 3.4 0.88 2.25 8.8 — — — 0.36 0.9 2.4 — — — mAdc Input Current Iin 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µAdc Input Capacitance (Vin = 0) Cin — — — — 5.0 7.5 — — pF Quiescent Current (Per Package) IDD 5.0 10 15 — — — 5.0 10 20 — — — 0.005 0.010 0.015 5.0 10 20 — — — 150 300 600 µAdc IT 5.0 10 15 Vin = 0 or VDD Input Voltage “0” Level (VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc) VIL “1” Level VIH (VO = 0.5 or 4.5 Vdc) (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc) Output Drive Current (VOH = 2.5 Vdc) (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc) (VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 1.5 Vdc) Vdc Vdc IOH Source Sink Total Supply Current**† (Dynamic plus Quiescent, Per Package) (CL = 50 pF on all outputs, all buffers switching) mAdc IT = (1.7 µA/kHz) f + IDD IT = (3.4 µA/kHz) f + IDD IT = (5.1 µA/kHz) f + IDD µAdc #Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance. ** The formulas given are for the typical characteristics only at 25_C. †To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + (CL – 50) Vfk where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.001. MC14522B MC14526B 2 MOTOROLA CMOS LOGIC DATA ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C) Characteristic Output Rise and Fall Time tTLH, tTHL = (1.5 ns/pF) CL + 25 ns tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns Propagation Delay Time (Inhibit Used as Negative Edge Clock) Clock or Inhibit to Q tPLH, tPHL = (1.7 ns/pF) CL + 465 ns tPLH, tPHL = (0.66 ns/pF) CL + 197 ns tPLH, tPHL = (0.5 ns/pF) CL + 135 ns Symbol tTLH, tTHL (Figures 4, 5) VDD Min Typ # Max 5.0 10 15 — — — 100 50 40 200 100 80 ns tPLH, tPHL (Figures 4, 5, 6) Clock or Inhibit to “0” tPLH, tPHL = (1.7 ns/pF) CL + 155 ns tPLH, tPHL = (0.66 ns/pF) CL + 87 ns tPLH, tPHL = (0.5 ns/pF) CL + 65 ns Unit ns 5.0 10 15 — — — 550 225 160 1100 450 320 5.0 10 15 — — — 240 130 100 480 260 200 Propagation Delay Time Pn to Q tPLH, tPHL (Figures 4, 7) 5.0 10 15 — — — 260 120 100 520 240 200 ns Propagation Delay Time Reset to Q tPHL — — — 250 110 80 500 220 160 ns (Figure 8) 5.0 10 15 tPHL, tPLH (Figures 4, 9) 5.0 10 15 — — — 220 100 80 440 200 160 ns tw 5.0 10 15 250 100 80 125 50 40 — — — ns — — — 2.0 5.0 6.6 1.5 3.0 4.0 MHz (Figures 4, 5, 6) 5.0 10 15 tr, tf (Figures 5, 6) 5.0 10 15 — — — — — — 15 5 4 µs tsu 5.0 10 15 90 50 40 40 15 10 — — — ns 5.0 10 15 30 30 30 – 15 –5 0 — — — ns 5.0 10 15 250 100 80 125 50 40 — — — ns 5.0 10 15 350 250 200 175 125 100 — — — ns 5.0 10 15 10 20 30 – 110 – 30 – 20 — — — ns Propagation Delay Time Preset Enable to “0” Clock or Inhibit Pulse Width (Figures 5, 6) Clock Pulse Frequency (with PE = low) Clock or Inhibit Rise and Fall Time Setup Time Pn to Preset Enable fmax (Figure 10) Hold Time Preset Enable to Pn th (Figure 10) Preset Enable Pulse Width tw (Figure 10) Reset Pulse Width tw (Figure 8) Reset Removal Time trem (Figure 8) * The formulas given are for the typical characteristics only at 25_C. #Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance. MOTOROLA CMOS LOGIC DATA MC14522B MC14526B 3 VOL VOH VDD = VGS VDD = –VGS CF PE P0 P1 P2 P3 RESET INHIBIT CLOCK Q0 Q1 Q2 IOH Q3 “0” EXTERNAL POWER SUPPLY VSS Figure 1. Typical Output Source Characteristics Test Circuit CF PE P0 P1 P2 P3 RESET INHIBIT CLOCK Q0 Q1 Q2 IOL Q3 “0” EXTERNAL POWER SUPPLY VSS Figure 2. Typical Output Sink Characteristics Test Circuit VDD CF PE P0 P1 P2 P3 RESET INHIBIT CLOCK Q0 Q1 Q2 CL Q3 CL “0” CL VSS CL PULSE GENERATOR 20 ns CLOCK 20 ns VDD 90% 50% 10% VSS VARIABLE 50% DUTY CYCLE WIDTH Figure 3. Power Dissipation MC14522B MC14526B 4 TEST POINT CL Q or “0” DEVICE UNDER TEST CL* * Includes all probe and jig capacitance. Figure 4. Test Circuit MOTOROLA CMOS LOGIC DATA SWITCHING WAVEFORMS tr CLOCK tf tf VDD 90% 50% 10% tr VDD 90% 50% 10% INHIBIT VSS VSS tw tw 1/fmax tPLH ANY Q OR “0” 1/fmax tPHL tPLH 90% 50% 10% ANY Q OR “0” tTLH tPHL 90% 50% 10% tTHL tTLH Figure 5. tTHL Figure 6. tw VDD RESET 50% VSS tr ANY P tf tPHL VDD 90% 50% 10% VSS tPLH ANY Q 50% tPHL trem ANY Q 50% VDD CLOCK 50% VSS Figure 7. Figure 8. VALID tr PRESET ENABLE tf VDD VDD 90% 50% 10% ANY P 50% VSS GND tPHL VDD PRESET ENABLE “0” th tsu tPLH 50% 50% VSS tw Figure 9. MOTOROLA CMOS LOGIC DATA Figure 10. MC14522B MC14526B 5 PIN DESCRIPTIONS Preset Enable (Pin 3) — If Reset is low, a high level on the Preset Enable input asynchronously loads the counter with the programmed values on P0, P1, P2, and P3. other than all zeroes, the “0” output is valid after the rising edge of Preset Enable (when Cascade Feedback is high). See the Function Table. Inhibit (Pin 4) — A high level on the Inhibit input pre– vents the Clock from decrementing the counter. With Clock (pin 6) held high, Inhibit may be used as a negative edge clock input. Cascade Feedback (Pin 13) — If the Cascade Feedback input is high, a high level is generated at the “0” output when the count is all zeroes. If Cascade Feedback is low, the “0” output depends on the Preset Enable input level. See the Function Table. Clock (Pin 6) — The counter decrements by one for each rising edge of Clock. See the Function Table for level requirements on the other inputs. Reset (Pin 10) — A high level on Reset asynchronously forces Q0, Q1, Q2, and Q3 low and, if Cascade Feedback is high, causes the “0” output to go high. “0” (Pin 12) — The “0” (Zero) output issues a pulse one clock period wide when the counter reaches terminal count (Q0 = Q1 = Q2 = Q3 = low) if Cascade Feedback is high and Preset Enable is low. When presetting the counter to a value P0, P1, P2, P3 (Pins 5, 11, 14, 2) — These are the preset data inputs. P0 is the LSB. Q0, Q1, Q2, Q3 (Pins 7, 9, 15, 1) — These are the synchronous counter outputs. Q0 is the LSB. VSS (Pin 8) — The most negative power supply potential. This pin is usually ground. VDD (Pin 16) — The most positive power supply potential. VDD may range from 3 to 18 V with respect to VSS. STATE DIAGRAMS MC14522B 0 4 0 15 5 15 5 14 6 14 6 13 7 13 7 8 12 12 1 11 2 MC14526B 10 MC14522B MC14526B 6 3 9 1 11 2 10 3 9 4 8 MOTOROLA CMOS LOGIC DATA MC14522B LOGIC DIAGRAM (BCD Down Counter) P0 Q0 5 P1 7 Q1 11 P2 9 Q2 14 P3 15 Q3 2 1 D R D RQ D RQ D RQ C C C C T PE Q T PE Q T PE Q T PE Q VSS CF PE INHIBIT 13 3 4 12 CLOCK RESET 10 “0” 6 MC14526B LOGIC DIAGRAM (Binary Down Counter) P0 Q0 5 P1 7 D R C T PE Q P2 9 Q2 14 P3 15 Q3 2 1 D RQ D RQ D RQ C C C T PE Q T PE Q T PE Q VDD CF Q1 11 VDD 13 PE 3 INHIBIT 4 12 CLOCK RESET 10 “0” 6 MOTOROLA CMOS LOGIC DATA MC14522B MC14526B 7 APPLICATIONS INFORMATION Divide–By–N, Single Stage The Inhibit pin may be used to stop pulse counting. When this pin is taken high, decrementing is inhibited. Figure 11 shows a single stage divide–by–N application. The MC14522B (BCD version) can accept a number greater than 9 and count down in binary fashion. Hence, the BCD and binary single stage divide–by–N counters (as shown in Figure 11) function the same. To initialize counting a number, N is set on the parallel inputs (P0, P1, P2, and P3) and reset is taken high asynchronously. A zero is forced into the master and slave of each bit and, at the same time, the “0” output goes high. Because Preset Enable is tied to the “0” output, preset is enabled. Reset must be released while the Clock is high so the slaves of each bit may receive N before the Clock goes low. When the Clock goes low and Reset is low, the “0” output goes low (if P0 through P3 are unequal to zero). The counter downcounts with each rising edge of the Clock. When the counter reaches the zero state, an output pulse occurs on “0” which presets N. The propagation delays from the Clock’s rising and falling edges to the “0” output’s rising and falling edges are about equal, making the “0” output pulse approximately equal to that of the Clock pulse. Cascaded, Presettable Divide–By–N N VDD fin VSS P0 P1 P2 P3 CF RESET INHIBIT Figure 12 shows a three stage cascade application. Taking Reset high loads N. Only the first stage’s Reset pin (least significant counter) must be taken high to cause the preset for all stages, but all pins could be tied together, as shown. When the first stage’s Reset pin goes high, the “0” output is latched in a high state. Reset must be released while Clock is high and time allowed for Preset Enable to load N into all stages before Clock goes low. When Preset Enable is high and Clock is low, time must be allowed for the zero digits to propagate a Cascade Feedback to the first non–zero stage. Worst case is from the most significant bit (M.S.B.) to the L.S.B., when the L.S.B. is equal to one (i.e. N = 1). After N is loaded, each stage counts down to zero with each rising edge of Clock. When any stage reaches zero and the leading stages (more significant bits) are zero, the “0” output goes high and feeds back to the preceding stage. When all stages are zero, the Preset Enable automatically loads N while the Clock is high and the cycle is renewed. Q0 Q1 Q2 Q3 BUFFER fin “0” N CLOCK PE Figure 11. ÷ N Counter LSB N0 N1 N2 N3 P0 P1 P2 P3 fin VSS VDD P0 P1 P2 P3 Q0 Q1 Q2 Q3 CLOCK Q0 Q1 Q2 Q3 P0 P1 P2 P3 CLOCK CLOCK INHIBIT RESET LOAD N MSB N8 N9 N10 N11 N4 N5 N6 N7 CF “0” PE VSS INHIBIT RESET CF “0” PE VSS INHIBIT RESET Q0 Q1 Q2 Q3 VDD CF “0” PE BUFFER 10 KΩ fin VSS N Figure 12. 3 Stages Cascaded MC14522B MC14526B 8 MOTOROLA CMOS LOGIC DATA OUTLINE DIMENSIONS L SUFFIX CERAMIC DIP PACKAGE CASE 620–10 ISSUE V –A– 16 9 1 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. –B– C L DIM A B C D E F G H K L M N –T– K N SEATING PLANE M E F J G D 16 PL 0.25 (0.010) 16 PL 0.25 (0.010) M T A T B M S INCHES MIN MAX 0.750 0.785 0.240 0.295 ––– 0.200 0.015 0.020 0.050 BSC 0.055 0.065 0.100 BSC 0.008 0.015 0.125 0.170 0.300 BSC 0_ 15 _ 0.020 0.040 MILLIMETERS MIN MAX 19.05 19.93 6.10 7.49 ––– 5.08 0.39 0.50 1.27 BSC 1.40 1.65 2.54 BSC 0.21 0.38 3.18 4.31 7.62 BSC 0_ 15 _ 0.51 1.01 S P SUFFIX PLASTIC DIP PACKAGE CASE 648–08 ISSUE R NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. –A– 16 9 1 8 B F C L S –T– SEATING PLANE K H G D J 16 PL 0.25 (0.010) MOTOROLA CMOS LOGIC DATA M T A M M DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01 MC14522B MC14526B 9 OUTLINE DIMENSIONS DW SUFFIX PLASTIC SOIC PACKAGE CASE 751G–02 ISSUE A –A– 16 9 –B– 8X P 0.010 (0.25) 1 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. M B M 8 16X J D 0.010 (0.25) M T A S B S F R X 45 _ C –T– 14X G K SEATING PLANE M DIM A B C D F G J K M P R MILLIMETERS MIN MAX 10.15 10.45 7.40 7.60 2.35 2.65 0.35 0.49 0.50 0.90 1.27 BSC 0.25 0.32 0.10 0.25 0_ 7_ 10.05 10.55 0.25 0.75 INCHES MIN MAX 0.400 0.411 0.292 0.299 0.093 0.104 0.014 0.019 0.020 0.035 0.050 BSC 0.010 0.012 0.004 0.009 0_ 7_ 0.395 0.415 0.010 0.029 Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. 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Box 20912; Phoenix, Arizona 85036. 1–800–441–2447 or 602–303–5454 JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, 6F Seibu–Butsuryu–Center, 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 03–81–3521–8315 MFAX: [email protected] – TOUCHTONE 602–244–6609 INTERNET: http://Design–NET.com ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298 MC14522B MC14526B 10 ◊ *MC14522B/D* MOTOROLA CMOS LOGIC DATA MC14522B/D