MOTOROLA MC14538BCP

SEMICONDUCTOR TECHNICAL DATA
L SUFFIX
CERAMIC
CASE 620
The MC14538B is a dual, retriggerable, resettable monostable multivibrator. It may be triggered from either edge of an input pulse, and produces an
accurate output pulse over a wide range of widths, the duration and accuracy
of which are determined by the external timing components, CX and RX.
• Unlimited Rise and Fall Time Allowed on the A Trigger Input
• Pulse Width Range = 10 µs to 10 s
• Latched Trigger Inputs
• Separate Latched Reset Inputs
• 3.0 Vdc to 18 Vdc Operational Limits
• Triggerable from Positive (A Input) or Negative–Going Edge (B–Input)
• Capable of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load Over the Rated Temperature Range
• Pin–for–pin Compatible with MC14528B and CD4528B (CD4098)
• Use the MC54/74HC4538A for Pulse Widths Less Than 10 µs with
Supplies Up to 6 V.
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P SUFFIX
PLASTIC
CASE 648
DW SUFFIX
SOIC
CASE 751G
ORDERING INFORMATION
MC14XXXBCP
MC14XXXBCL
*MC14XXXBDW
TA = – 55° to 125°C for all packages.
MAXIMUM RATINGS* (Voltages Referenced to VSS)
Symbol
VDD
Parameter
DC Supply Voltage
Value
Unit
– 0.5 to + 18.0
V
Vin, Vout
Input or Output Voltage (DC or Transient)
– 0.5 to VDD + 0.5
V
Iin, Iout
Input or Output Current (DC or Transient),
per Pin
± 10
mA
PD
Power Dissipation, per Package†
500
mW
Tstg
Storage Temperature
– 65 to + 150
_C
260
_C
TL
Lead Temperature (8–Second Soldering)
Plastic
Ceramic
SOIC
BLOCK DIAGRAM
CX
1
4
5
2
B
Q1
6
Q1
RESET
7
3
CX
15
100 ns
MC14528B
MC14536B
MC14538B
1 µs
10 µs
100 µs
1 ms
10 ms
100 ms
12
1s
11
10 s
23 HR
5 MIN.
MC14541B
MC4538A*
*LIMITED OPERATING VOLTAGE (2 – 6 V)
TOTAL OUTPUT PULSE WIDTH RANGE
RECOMMENDED PULSE WIDTH RANGE
VDD
A
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C
ONE–SHOT SELECTION GUIDE
RX
RX
VDD
14
A
Q2
B
Q2
RESET
10
9
13
RX AND CX ARE EXTERNAL COMPONENTS.
VDD = PIN 16
VSS = PIN 8, PIN 1, PIN 15
* Consult factory for possible “D” suffix SOIC
Case 751B.
REV 3
1/94
MOTOROLA
Motorola, Inc. 1995
CMOS LOGIC DATA
MC14538B
1
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
Characteristic
Output Voltage
Vin = VDD or 0
Symbol
– 55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ #
Max
Min
Max
Unit
“0” Level
VOL
5.0
10
15
—
—
—
0.05
0.05
0.05
—
—
—
0
0
0
0.05
0.05
0.05
—
—
—
0.05
0.05
0.05
Vdc
“1” Level
VOH
5.0
10
15
4.95
9.95
14.95
—
—
—
4.95
9.95
14.95
5.0
10
15
—
—
—
4.95
9.95
14.95
—
—
—
Vdc
5.0
10
15
—
—
—
1.5
3.0
4.0
—
—
—
2.25
4.50
6.75
1.5
3.0
4.0
—
—
—
1.5
3.0
4.0
5.0
10
15
3.5
7.0
11
—
—
—
3.5
7.0
11
2.75
5.50
8.25
—
—
—
3.5
7.0
11
—
—
—
5.0
5.0
10
15
– 3.0
– 0.64
– 1.6
– 4.2
—
—
—
—
– 2.4
– 0.51
– 1.3
– 3.4
– 4.2
– 0.88
– 2.25
– 8.8
—
—
—
—
– 1.7
– 0.36
– 0.9
– 2.4
—
—
—
—
IOL
5.0
10
15
0.64
1.6
4.2
—
—
—
0.51
1.3
3.4
0.88
2.25
8.8
—
—
—
0.36
0.9
2.4
—
—
—
mAdc
Input Current, Pin 2 or 14
Iin
15
—
± 0.05
—
± 0.00001
± 0.05
—
± 0.5
µAdc
Input Current, Other Inputs
Iin
15
—
± 0.1
—
± 0.00001
± 0.1
—
± 1.0
µAdc
Input Capacitance, Pin 2 or 14
Cin
—
—
—
—
25
—
—
—
pF
Input Capacitance, Other Inputs
(Vin = 0)
Cin
—
—
—
—
5.0
7.5
—
—
pF
Quiescent Current
(Per Package)
Q = Low, Q = High
IDD
5.0
10
15
—
—
—
5.0
10
20
—
—
—
0.005
0.010
0.015
5.0
10
20
—
—
—
150
300
600
µAdc
Quiescent Current, Active State
(Both) (Per Package)
Q = High, Q = Low
IDD
5.0
10
15
—
—
—
2.0
2.0
2.0
—
—
—
0.04
0.08
0.13
0.20
0.45
0.70
—
—
—
2.0
2.0
2.0
mAdc
IT
5.0
10
Vin = 0 or VDD
Input Voltage
“0” Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL
“1” Level
VIH
(VO = 0.5 or 4.5 Vdc)
(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
Output Drive Current
(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
Vdc
Vdc
IOH
Source
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Sink
**Total Supply Current at an
external load capacitance (CL) and
at external timing network (RX, CX)
mAdc
IT = (3.5 x 10–2) RXCXf + 4CXf + 1 x 10–5 CLf
IT = (8.0 x 10–2) RXCXf + 9CXf + 2 x 10–5 CLf
IT = (1.25 x 10–1) RXCXf + 12CXf + 3 x 10–5 CLf
where: IT in µA (one monostable switching only),
where: CX in µF, CL in pF, RX in k ohms, and
where: f in Hz is the input frequency.
µAdc
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
** The formulas given are for the typical characteristics only at 25_C.
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However,
precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance
circuit. For proper operation, Vin and Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must
be left open.
MC14538B
2
MOTOROLA CMOS LOGIC DATA
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
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SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C)
Characteristic
Symbol
Output Rise Time
tTLH = (1.35 ns/pF) CL + 33 ns
tTLH = (0.60 ns/pF) CL + 20 ns
tTLH = (0.40 ns/pF) CL + 20 ns
tTLH
Output Fall Time
tTHL = (1.35 ns/pF) CL + 33 ns
tTHL = (0.60 ns/pF) CL + 20 ns
tTHL = (0.40 ns/pF) CL + 20 ns
tTHL
Propagation Delay Time
A or B to Q or Q
tPLH, tPHL = (0.90 ns/pF) CL + 255 ns
tPLH, tPHL = (0.36 ns/pF) CL + 132 ns
tPLH, tPHL = (0.26 ns/pF) CL + 87 ns
tPLH,
tPHL
All Types
VDD
Vdc
Min
Typ #
Max
5.0
10
15
—
—
—
100
50
40
200
100
80
5.0
10
15
—
—
—
100
50
40
200
100
80
Unit
ns
ns
ns
5.0
10
15
—
—
—
300
150
100
600
300
220
5.0
10
15
—
—
—
250
125
95
500
250
190
5
10
15
—
—
—
—
—
—
15
5
4
µs
B Input
5
10
15
—
—
—
300
1.2
0.4
1.0
0.1
0.05
ms
A Input
5
10
15
Reset to Q or Q
tPLH, tPHL = (0.90 ns/pF) CL + 205 ns
tPLH, tPHL = (0.36 ns/pF) CL + 107 ns
tPLH, tPHL = (0.26 ns/pF) CL + 82 ns
Input Rise and Fall Times
Reset
Input Pulse Width
A, B, or Reset
ns
tr, tf
—
No Limit
tWH,
tWL
5.0
10
15
170
90
80
85
45
40
—
—
—
ns
Retrigger Time
trr
5.0
10
15
0
0
0
—
—
—
—
—
—
ns
Output Pulse Width — Q or Q
Refer to Figures 8 and 9
CX = 0.002 µF, RX = 100 kΩ
T
µs
5.0
10
15
198
200
202
210
212
214
230
232
234
CX = 0.1 µF, RX = 100 kΩ
5.0
10
15
9.3
9.4
9.5
9.86
10
10.14
10.5
10.6
10.7
ms
CX = 10 µF, RX = 100 kΩ
5.0
10
15
0.91
0.92
0.93
0.965
0.98
0.99
1.03
1.04
1.06
s
5.0
10
15
—
—
—
± 1.0
± 1.0
± 1.0
± 5.0
± 5.0
± 5.0
%
Pulse Width Match between circuits in
the same package.
CX = 0.1 µF, RX = 100 kΩ
100
[(T1 – T2)/T1]
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
* The formulas given are for the typical characteristics only at 25_C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
OPERATING CONDITIONS
External Timing Resistance
RX
—
5.0
—
External Timing Capacitance
CX
—
0
—
kΩ
No
Limit†
µF
* The maximum usable resistance RX is a function of the leakage of the capacitor CX, leakage of the MC14538B, and leakage due to board layout
and surface resistance. Susceptibility to externally induced noise signals may occur for RX > 1 MΩ..
†If CX > 15 µF, use discharge protection diode per Fig. 11.
MOTOROLA CMOS LOGIC DATA
MC14538B
3
VDD
VDD
P1
RX
2 (14)
CX
+
C1
–
Vref1
1 (15)
Vref2
ENABLE
ENABLE
+
C2
–
N1
A
VSS
4 (12)
6 (10)
R
Q
OUTPUT
LATCH
S
Q
7 (9)
CONTROL
5 (11)
B
RESET
QR
S
3 (13)
RESET LATCH
NOTE: Pins 1, 8 and 15 must
be externally grounded
QR
R
Figure 1. Logic Diagram
(1/2 of DevIce Shown)
VDD
500 pF
0.1 µF
CERAMIC
ID
RX′
CX′
RX
VSS
Vin
CX
VSS
CX/RX
A
B
Q
RESET
Q
A′
Q′
B′
Q′
20 ns
CL
VDD
90%
CL
CL
20 ns
10%
Vin
0V
CL
RESET′
VSS
Figure 2. Power Dissipation Test Circuit and Waveforms
VDD
INPUT CONNECTIONS
RX′
RX
VSS
A
B
Q
PULSE
GENERATOR
RESET
Q
A′
Q′
PULSE
GENERATOR
VSS
CX/RX
PULSE
GENERATOR
B′
CL
CL
CL
Q′
CL
RESET′
VSS
Characteristics
Reset
A
B
tPLH, tPHL, tTLH, tTHL,
T, tWH, tWL
VDD
PG1
VDD
tPLH, tPHL, tTLH, tTHL,
T, tWH, tWL
VDD
VSS
PG2
tPLH(R), tPHL(R),
tWH, tWL
PG3
PG1
PG2
* CL = 50 pF
CX′
CX
* Includes capacitance of probes,
wiring, and fixture parasitic.
PG1 =
NOTE: Switching test waveforms
for PG1, PG2, PG3 are shown
In Figure 4.
PG2 =
PG3 =
Figure 3. Switching Test Circuit
MC14538B
4
MOTOROLA CMOS LOGIC DATA
90%
10%
tTHL
50%
A
tTLH
tWH
50%
tTHL
90%
10%
B
50%
VDD
tTLH
VDD
tWL
tTHL
90%
10%
RESET
tPLH
T
tPLH
50%
50%
Q
tTLH
90%
10%
50%
Q
tPHL
tTHL
50%
90%
10%
50%
VDD
50%
tWL
trr
tPHL
50%
tTHL
tTLH
tPHL
tPHL
tPLH
50%
50%
TA = 25°C
RX = 100 kΩ
CX = 0.1 µF
NORMALIZED PULSE WIDTH CHANGE
WITH RESPECT TO VALUE AT VDD = 10 V (%)
RELATIVE FREQUENCY OF OCCURRENCE
Figure 4. Switching Test Waveforms
0% POINT PULSE WIDTH
VDD = 5.0 V, T = 9.8 ms
VDD = 10 V, T = 10 ms
VDD = 15 V, T = 10.2 ms
1.0
0.8
0.6
0.4
0.2
0
–4 –2
0
2
4
T, OUTPUT PULSE WIDTH (%)
RX = 100 kΩ
CX = 0.1 µF
2
1
0
1
2
5
Figure 5. Typical Normalized Distribution
of Units for Output Pulse Width
6
7
8
9
10
11
12
VDD, SUPPLY VOLTAGE (VOLTS)
TOTAL SUPPLY CURRENT ( µA)
15
FUNCTION TABLE
Inputs
RX = 100 kΩ, CL = 50 pF
ONE MONOSTABLE SWITCHING ONLY
Reset
VDD = 15 V
5.0 V
10
10 V
1.0
0.1
0.001
14
Figure 6. Typical Pulse Width Variation as
a Function of Supply Voltage VDD
1000
100
13
0.1
1.0
10
A
H
H
L
H
H
H
H
H
L
Outputs
B
Q
Q
H
L
Not Triggered
Not Triggered
L, H,
L
H
L, H,
Not Triggered
Not Triggered
X
X
X
X
L
H
Not Triggered
100
OUTPUT DUTY CYCLE (%)
Figure 7. Typical Total Supply Current
versus Output Duty Cycle
MOTOROLA CMOS LOGIC DATA
MC14538B
5
2
VDD = 15 V
1
VDD = 10 V
0
VDD = 5 V
–1
TYPICAL NORMALIZED ERROR
WITH RESPECT TO 25°C VALUE AT VDD = 10 V (%)
TYPICAL NORMALIZED ERROR
WITH RESPECT TO 25°C VALUE AT VDD = 10 V (%)
RX = 100 kΩ
CX = 0.1 µF
3.0
2.0
1.0
0
– 1.0
–2
RX = 100 kΩ
CX = .002 µF
VDD = 15 V
VDD = 10 V
– 2.0
VDD = 5.0 V
– 3.0
– 60 – 40
– 20
0
20
40
60
80 100
TA, AMBIENT TEMPERATURE (°C)
120
140
– 60 – 40
Figure 8. Typical Error of Pulse Width
Equation versus Temperature
– 20
0
20
40
60
80 100
TA, AMBIENT TEMPERATURE (°C)
120
140
Figure 9. Typical Error of Pulse Width
Equation versus Temperature
THEORY OF OPERATION
1
3
4
A
2
B
5
RESET
Vref 2
Vref 2
CX/RX
Vref 1
Vref 2
Vref 2
Vref 1
Vref 1
Vref 1
Q
T
T
T
1
Positive edge trigger
4
Positive edge re–trigger (pulse lengthening)
2
Negative edge trigger
5
Positive edge re–trigger (pulse lengthening)
3
Positive edge trigger
Figure 10. Timing Operation
TRIGGER OPERATION
The block diagram of the MC14538B is shown in Figure 1,
with circuit operation following.
As shown in Figure 1 and 10, before an input trigger
occurs, the monostable is in the quiescent state with the Q
output low, and the timing capacitor CX completely charged
to V DD. When the trigger input A goes from V SS to V DD
(while inputs B and Reset are held to V DD) a valid trigger is
recognized, which turns on comparator C1 and N–channel
transistor N1 ➀. At the same time the output latch is set. With
transistor N1 on, the capacitor CX rapidly discharges toward
V SS until V ref1 is reached. At this point the output of
comparator C1 changes state and transistor N1 turns off.
Comparator C1 then turns off while at the same time
MC14538B
6
comparator C2 turns on. With transistor N1 off, the capacitor
CX begins to charge through the timing resistor, R X, toward
V DD. When the voltage across CX equals Vref 2, comparator
C2 changes state, causing the output latch to reset (Q goes
low) while at the same time disabling comparator C2 ➁. This
ends at the timing cycle with the monostable in the quiescent
state, waiting for the next trigger.
In the quiescent state, CX is fully charged to VDD causing
the current through resistor RX to be zero. Both comparators
are “off” with total device current due only to reverse junction
leakages. An added feature of the MC14538B is that the output latch is set via the input trigger without regard to the
capacitor voltage. Thus, propagation delay from trigger to Q
is independent of the value of CX, RX, or the duty cycle of the
input waveform.
MOTOROLA CMOS LOGIC DATA
RETRIGGER OPERATION
The MC14538B is retriggered if a valid trigger occurs ➂ followed by another valid trigger ➃ before the Q output has
returned to the quiescent (zero) state. Any retrigger, after the
timing node voltage at pin 2 or 14 has begun to rise from
Vref 1, but has not yet reached Vref 2, will cause an increase
in output pulse width T. When a valid retrigger is initiated ➃,
the voltage at C X /R X will again drop to V ref 1 before
progressing along the RC charging curve toward VDD. The Q
output will remain high until time T, after the last valid retrigger.
RESET OPERATION
The MC14538B may be reset during the generation of the
output pulse. In the reset mode of operation, an input pulse
on Reset sets the reset latch and causes the capacitor to be
fast charged to VDD by turning on transistor P1 ➄. When the
voltage on the capacitor reaches Vref 2, the reset latch will
clear, and will then be ready to accept another pulse. It the
Reset input is held low, any trigger inputs that occur will be
inhibited and the Q and Q outputs of the output latch will not
change. Since the Q output is reset when an input low level is
detected on the Reset input, the output pulse T can be made
significantly shorter than the minimum pulse width specification.
POWER–DOWN CONSIDERATIONS
Large capacitance values can cause problems due to the
large amount of energy stored. When a system containing
the MC14538B is powered down, the capacitor voltage may
discharge from V DD through the standard protection diodes
at pin 2 or 14. Current through the protection diodes should
be limited to 10 mA and therefore the discharge time of the
V DD supply must not be faster than (V DD). (C)/ (10 mA). For
example, if V DD = 10 V and CX = 10 µF, the V DD supply
should discharge no faster than (10 V) x (10 µF) / (10 mA) =
10 ms. This is normally not a problem since power supplies
are heavily filtered and cannot discharge at this rate.
When a more rapid decrease of V DD to zero volts occurs,
the MC14538B can sustain damage. To avoid this possibility
use an external clamping diode, D X, connected as shown in
Fig. 11.
Dx
PIN ASSIGNMENT
Cx
Rx VDD
VSS
VDD
Q
Q
RESET
VSS
1
16
VDD
CX/RXA
2
15
VSS
RESET A
3
14
CX/RXB
AA
4
13
RESET B
BA
5
12
AB
QA
6
11
BB
QA
7
10
QB
VSS
8
9
QB
Figure 11. Use of a Diode to Limit
Power Down Current Surge
MOTOROLA CMOS LOGIC DATA
MC14538B
7
TYPICAL APPLICATIONS
CX
CX
RX
RX
VDD
VDD
RISING–EDGE
A
TRIGGER
B
RISING–EDGE
A
TRIGGER
B
Q
Q
Q
Q
RESET = VDD
B = VDD
CX
RESET = VDD
CX
A = VSS
VDD
RX
VDD
Q
A
B
Q
B
RX
Q
FALLING–EDGE
TRIGGER
Q
FALLING–EDGE
TRIGGER
RESET = VDD
RESET = VDD
Figure 12. Retriggerable
Monostables Circuitry
Figure 13. Non–Retriggerable
Monostables Circuitry
NC
A
B
Q
NC
Q
NC
CD
VDD
VDD
Figure 14. Connection of Unused Sections
MC14538B
8
MOTOROLA CMOS LOGIC DATA
OUTLINE DIMENSIONS
L SUFFIX
CERAMIC DIP PACKAGE
CASE 620–10
ISSUE V
–A–
16
9
1
8
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION F MAY NARROW TO 0.76 (0.030)
WHERE THE LEAD ENTERS THE CERAMIC
BODY.
–B–
C
L
DIM
A
B
C
D
E
F
G
H
K
L
M
N
–T–
K
N
SEATING
PLANE
M
E
F
J
G
D
16 PL
0.25 (0.010)
16 PL
0.25 (0.010)
M
T A
T B
M
S
INCHES
MIN
MAX
0.750
0.785
0.240
0.295
–––
0.200
0.015
0.020
0.050 BSC
0.055
0.065
0.100 BSC
0.008
0.015
0.125
0.170
0.300 BSC
0_
15 _
0.020
0.040
MILLIMETERS
MIN
MAX
19.05
19.93
6.10
7.49
–––
5.08
0.39
0.50
1.27 BSC
1.40
1.65
2.54 BSC
0.21
0.38
3.18
4.31
7.62 BSC
0_
15 _
0.51
1.01
S
P SUFFIX
PLASTIC DIP PACKAGE
CASE 648–08
ISSUE R
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
–A–
16
9
1
8
B
F
C
L
S
–T–
SEATING
PLANE
K
H
G
D
J
16 PL
0.25 (0.010)
MOTOROLA CMOS LOGIC DATA
M
T A
M
M
DIM
A
B
C
D
F
G
H
J
K
L
M
S
INCHES
MIN
MAX
0.740
0.770
0.250
0.270
0.145
0.175
0.015
0.021
0.040
0.70
0.100 BSC
0.050 BSC
0.008
0.015
0.110
0.130
0.295
0.305
0_
10 _
0.020
0.040
MILLIMETERS
MIN
MAX
18.80
19.55
6.35
6.85
3.69
4.44
0.39
0.53
1.02
1.77
2.54 BSC
1.27 BSC
0.21
0.38
2.80
3.30
7.50
7.74
0_
10 _
0.51
1.01
MC14538B
9
OUTLINE DIMENSIONS
DW SUFFIX
PLASTIC SOIC PACKAGE
CASE 751G–02
ISSUE A
–A–
16
9
–B–
8X
P
0.010 (0.25)
1
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER
SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN
EXCESS OF D DIMENSION AT MAXIMUM
MATERIAL CONDITION.
M
B
M
8
16X
J
D
0.010 (0.25)
M
T A
S
B
S
F
R X 45 _
C
–T–
14X
G
K
SEATING
PLANE
M
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
10.15
10.45
7.40
7.60
2.35
2.65
0.35
0.49
0.50
0.90
1.27 BSC
0.25
0.32
0.10
0.25
0_
7_
10.05
10.55
0.25
0.75
INCHES
MIN
MAX
0.400
0.411
0.292
0.299
0.093
0.104
0.014
0.019
0.020
0.035
0.050 BSC
0.010
0.012
0.004
0.009
0_
7_
0.395
0.415
0.010
0.029
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MC14538B
10
◊
*MC14538B/D*
MOTOROLA CMOS LOGIC
DATA
MC14538B/D