Freescale Semiconductor, Inc. Order this document by MC68HC812A4EC/D 7/28/98 Technical Supplement MC68C812A4 3.3V Electrical Characteristics Freescale Semiconductor, Inc... The MC68C812A4 is the low-voltage version of the standard MC68HC812A4 microcontroller unit (MCU), a 16-bit device composed of standard on-chip peripheral modules connected by an intermodule bus. Modules include a 16-bit central processing unit (CPU12), a Lite integration module (LIM), two asynchronous serial communications interfaces (SCI0 and SCI1), a serial peripheral interface (SPI), a timer and pulse accumulation module, an 8-bit analog-to-digital converter (ATD), 1-Kbyte RAM, 4-Kbyte EEPROM, and memory expansion logic with chip selects, key wakeup ports, and a phase-locked loop (PLL). This supplement contains the most accurate electrical information for the MC68C812A4 microcontroller available at the time of publication. The information should be considered preliminary and is subject to change. The following characteristics are contained in this document: Table 1 Maximum Ratings Table 2 Thermal Characteristics Table 3 DC Electrical Characteristics Table 4 Supply Current Table 5 ATD Maximum Ratings Table 6 ATD DC Electrical Characteristics Table 7 Analog Converter Characteristics (Operating) Table 8 ATD AC Characteristics (Operating) Table 9 EEPROM Characteristics Table 10 Control Timing Table 11 Peripheral Port Timing Table 12 Non-Multiplexed Expansion Bus Timing Table 13 SPI Timing For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Table 1 Maximum Ratings1 Rating Symbol Value Unit VDD, VDDA, VDDX −0.3 to +6.5 V VIN −0.3 to +6.5 V Operating temperature range MC68C812A4PV5 TA TL to TH 0 to +70 °C Storage temperature range Tstg −55 to +150 °C Current drain per pin3 Excluding VDD and VSS IIN ±25 mA VDD−VDDX 6.5 V Supply voltage Input voltage 2 PRELIMINARY Freescale Semiconductor, Inc... VDD differential voltage NOTES: 1. Permanent damage can occur if maximum ratings are exceeded. Exposures to voltages or currents in excess of recommended values affects device reliability. Device modules may not operate normally while being exposed to electrical extremes. 2. Refer to MC68HC812A4TS/D Technical Summary for complete part numbers. 3. One pin at a time, observing maximum power dissipation limits. Internal circuitry protects the inputs against damage caused by high static voltages or electric fields; however, normal precautions are necessary to avoid application of any voltage higher than maximum-rated voltages to this highimpedance circuit. Extended operation at the maximum ratings can adversely affect device reliability. Tying unused inputs to an appropriate logic voltage level (either GND or VDD) enhances reliability of operation. Table 2 Thermal Characteristics Characteristic Symbol Value Unit Average junction temperature TJ TA + (PD × ΘJA) °C Ambient temperature TA User-determined °C Package thermal resistance (junction-to-ambient) 112-pin thin quad flat pack (TQFP) ΘJA 39 °C/W Total power dissipation1 PD Device internal power dissipation I/O pin power A constant3 dissipation2 PINT + PI/O or K -------------------------T J + 273°C W PINT IDD × VDD W PI/O User-determined W K PD × (TA + 273°C) + ΘJA × PD2 W · °C NOTES: 1. This is an approximate value, neglecting PI/O. 2. For most applications PI/O « PINT and can be neglected. 3. K is a constant pertaining to the device. Solve for K with a known TA and a measured PD (at equilibrium). Use this value of K to solve for PD and TJ iteratively for any value of TA. 2 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Table 3 DC Electrical Characteristics Freescale Semiconductor, Inc... Characteristic Symbol Min Max Unit Input high voltage, all inputs VIH 0.7 × VDD VDD + 0.3 V Input low voltage, all inputs VIL VSS−0.3 0.2 × VDD V Output high voltage All I/O and output pins Normal drive strength IOH = −10.0 µA IOH = −0.8 mA VOH VDD − 0.2 VDD − 0.8 — — V V VDD − 0.2 VDD − 0.8 — — V V — — VSS+0.2 VSS+0.4 V V — — VSS+0.2 VSS+0.4 V V Reduced drive strength IOH = −4.0 µA IOH = −0.3 mA Output low voltage, All I/O and output pins, normal drive strength IOL = 10.0 µA IOL = 1.6 mA PRELIMINARY VDD = 3.3 Vdc ± 0.3V, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted VOL EXTAL, PAD[7:0], VRH, VRL, VFP, XIRQ, reduced drive strength IOL = 3.6 µA IOL = 0.6 mA Input leakage current1 all inputs except IRQ, PAD7, and XFC Vin = VDD or VSS IRQ, PAD7, XFC Iin — — ±1 ±10 µA µA Three-state leakage, I/O ports, BKGD, and RESET IOZ — ±2.5 µA Input capacitance All input pins and ATD pins (non-sampling) ATD pins (sampling) All I/O pins Cin — — — 10 15 20 pF pF pF Output load capacitance All outputs except PS[7:4] PS[7:4] CL — — 90 130 pF pF Active pull-up, pull-down current IRQ, XIRQ, ECLK, LSTRB, R/W , BKGD, MODA, MODB, ARST Ports A, B, C, D, F, G, H, J, S, T IAPU 50 500 µA RAM standby voltage, power down VSB 2.0 — V RAM standby current ISB — 1 mA NOTES: 1. Specification is for parts in the 0 to +70°C range. Higher temperature ranges will result in increased current leakage. For More Information On This Product, Go to: www.freescale.com 3 Freescale Semiconductor, Inc. Table 4 Supply Current VDD = 3.3 Vdc ± 0.3V, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted Characteristic Symbol 4 MHz 5 MHz Unit IDD 15 21 17 25 mA mA WIDD 3 3 3.5 3.5 mA mA SIDD 250 250 µA PD 54 76 62 90 mW mW Maximum total supply current RUN: Single-chip mode Expanded mode WAIT: (All peripheral functions shut down) Single-chip mode Expanded mode Maximum power dissipation1 PRELIMINARY Freescale Semiconductor, Inc... STOP: Single-chip mode, no clocks Single-chip mode Expanded mode NOTES: 1. Includes IDD and IDDA. Note: IDD is tested with a rail-to-rail square wave on EXTAL Table 5 ATD Maximum Ratings Characteristic Symbol Value Units ATD reference voltage VRH ≤ VDDA VRL ≥ VSSA VRH VRL −0.3 to +6.5 −0.3 to +6.5 V V VSS differential voltage |VSS−VSSA| 0.1 V VDD differential voltage |VDD−VDDA| VDD−VDDX 6.5 6.5 V V VREF differential voltage |VRH−VRL| 6.5 V |VRH−VDDA| |VRL−VSSA| 6.5 6.5 V V Reference to supply differential voltage 4 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Table 6 ATD DC Electrical Characteristics Characteristic Analog supply voltage Analog supply current Normal operation Min Max Unit VDDA 3.0 3.6 V 1.0 mA IDDA Reference voltage, low VRL VSSA VDDA/2 V Reference voltage, high VRH VDDA/2 VDDA V VRH−VRL 3.0 3.6 V VINDC VSSA VDDA V VREF differential reference voltage1 Input voltage2 Freescale Semiconductor, Inc... Symbol Input current, off channel3 IOFF 100 nA Reference supply current IREF 250 µA CINN CINS 10 15 pF pF Input capacitance Not Sampling Sampling PRELIMINARY VDD = 3.3 Vdc ± 0.3V, VSS = 0 Vdc, TA = TL to TH, ATD Clock = 2 MHz, unless otherwise noted NOTES: 1. Accuracy is guaranteed at VRH − VRL = 3.3 Vdc ± 0.3V. 2. To obtain full-scale, full-range results, VSSA ≤ VRL ≤ VINDC ≤ VRH ≤ VDDA. 3. Maximum leakage occurs at maximum operating temperature. Current decreases by approximately one-half for each 10°C decrease from maximum temperature. For More Information On This Product, Go to: www.freescale.com 5 Freescale Semiconductor, Inc. Table 7 Analog Converter Characteristics (Operating) VDD = 3.3 Vdc ± 0.3V, VSS = 0 Vdc, TA = TL to TH, ATD Clock = 2 MHz, unless otherwise noted Characteristic Symbol 8-bit resolution1 2 counts Typical Max 24 Unit mV Differential non-linearity2 DNL −0.5 +0.5 count Integral non-linearity2 INL −1 +1 count AE −2 +2 count See note4 KΩ Absolute error2,3 2, 4, 8, and 16 ATD sample clocks Maximum source impedance RS 20 NOTES: 1. VRH − VRL ≥ 3.072V 2. At VREF = 3.072V, one 8-bit count = 12 mV. 3. Eight-bit absolute error of 2 counts (24 mV) includes 1/2 count (6 mV) inherent quantization error and 1 1/2 counts (18 mV) circuit (differential, integral, and offset) error. 4. Maximum source impedance is application-dependent. Error resulting from pin leakage depends on junction leakage into the pin and on leakage due to charge-sharing with internal capacitance. Error from junction leakage is a function of external source impedance and input leakage current. Expected error in result value due to junction leakage is expressed in voltage (VERRJ): PRELIMINARY Freescale Semiconductor, Inc... Min VERRJ = RS × IOFF where IOFF is a function of operating temperature. Charge-sharing effects with internal capacitors are a function of ATD clock speed, the number of channels being scanned, and source impedance. For 8-bit conversions, charge pump leakage is computed as follows: VERRJ = .25pF × VDDA × RS × ATDCLK/(8 × number of channels) Table 8 ATD AC Characteristics (Operating) VDD = 3.3 Vdc ± 0.3V, VSS = 0 Vdc, TA = TL to TH, ATD Clock = 2 MHz, unless otherwise noted Characteristic ATD operating clock frequency Conversion time per channel 0.5 MHz ≤ fATDCLK ≤ 2 MHz 18 ATD clocks 32 ATD clocks Stop recovery time 6 VDDA = 3.3V Symbol Min Max Unit fATDCLK 0.5 2.0 MHz 9.0 16.0 32.0 60.0 µs µs 50 µs tCONV tSR For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Table 9 EEPROM Characteristics VDD = 3.3 Vdc ± 0.3V, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted Characteristic Symbol Min Minimum programming clock frequency1 fPROG 3.0 Programming time tPROG 20 ms tCRSTOP tPROG+ 1 ms tERASE 20 ms Clock recovery time following STOP, to continue programming Erase time Write/erase endurance Typical Unit MHz 10,000 Data retention Max 30,000 cycles 10 years PRELIMINARY Freescale Semiconductor, Inc... NOTES: 1. RC oscillator must be enabled if programming is desired and fSYS < fPROG. Table 10 Control Timing Characteristic Symbol 5.0 MHz Unit Min Max fo dc 5.0 MHz tcyc 200 — ns fXTAL — 10.0 MHz 2fo dc 10.0 MHz tPCSU 130 — ns PWRSTL 32 2 — — tcyc tcyc Mode programming setup time tMPS 4 — tcyc Mode programming hold time tMPH 10 — ns PWIRQ 420 — ns tWRS — 4 tcyc PWTIM 420 — ns Frequency of operation E-clock period Crystal frequency External oscillator frequency Processor control setup time tPCSU = tcyc/2+ 30 Reset input pulse width To guarantee external reset vector Minimum input time (can be preempted by internal reset) Interrupt pulse width, IRQ, edge-sensitive mode, KWU PWIRQ = 2tcyc + 20 Wait recovery startup time Timer pulse width, input capture pulse accumulator input PWTIM = 2tcyc + 20 For More Information On This Product, Go to: www.freescale.com 7 Freescale Semiconductor, Inc. PT[7:0]1 PW TIM PT[7:0]2 PT7 1 PW PA PT7 2 TIMER INPUT TIMING Figure 1 Timer Inputs PRELIMINARY Freescale Semiconductor, Inc... NOTES : 1. Rising edge sensitive input 2. Falling edge sensitive input 8 For More Information On This Product, Go to: www.freescale.com For More Information On This Product, Go to: www.freescale.com NOTE: Reset timing is subject to change. INTERNAL ADDRESS MODA, MODB RESET ECLK EXTAL V DD FFFE 4098 tcyc FREE 1ST PIPE 2ND PIPE 3RD PIPE 1ST EXEC FFFE FFFE tMPS PW RSTL PRELIMINARY FFFE tPCSU Freescale Semiconductor, Inc... FFFE FREE tMPH 1ST PIPE 3RD PIPE POR EXT RESET TIM 2ND PIPE 1ST EXEC Freescale Semiconductor, Inc. Figure 2 POR and External Reset Timing Diagram 9 10 SP-6 SP-6 SP-8 SP-8 SP-9 SP-9 PW IRQ NOTES: 1. Edge Sensitive IRQ pin (IRQE bit = 1) 2. Level sensitive IRQ pin (IRQE bit = 0) 3. tSTOPDELAY = 4098 tcyc if DLY bit = 1 or 2 cyc t if DLY = 0. 4. XIRQ with X bit in CCR = 1. 5. IRQ or (XIRQ with X bit in CCR = 0). ADDRESS 5 ADDRESS 4 ECLK IRQ or XIRQ IRQ 1 INTERNAL CLOCKS tSTOPDELAY 3 FREE FREE OPT FETCH 1ST EXEC FREE 1ST PIPE 2ND PIPE 3RD PIPE 1ST EXEC Resume program with instruction which follows the STOP instruction. VECTOR FREE PRELIMINARY Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. STOP RECOVERY TIM Figure 3 STOP Recovery Timing Diagram For More Information On This Product, Go to: www.freescale.com SP – 2 For More Information On This Product, Go to: www.freescale.com SP – 6 . . . SP – 9 PC, IY, IX, B:A, , CCR STACK REGISTERS SP – 4 SP – 9 SP – 9 . . . SP – 9 SP – 9 tPCSU PRELIMINARY NOTE: RESET also causes recovery from WAIT. R/W ADDRESS IRQ, XIRQ , OR INTERNAL INTERRUPTS ECLK Freescale Semiconductor, Inc... VECTOR ADDRESS tWRS FREE 1ST PIPE 2ND PIPE 3RD PIPE 1ST EXEC Freescale Semiconductor, Inc. WAIT RECOVERY TIM Figure 4 WAIT Recovery Timing Diagram 11 12 PC VECT DATA NOTES: 1. Edge sensitive IRQ pin (IRQE bit = 1) 2. Level sensitive IRQ pin (IRQE bit = 0) R/W SP – 2 VECTOR ADDR PW IRQ tPCSU ADDRESS OR INTERNAL INTERRUPT IRQ 2, XIRQ , IRQ 1 ECLK PROG FETCH 1ST PIPE IY SP – 4 IX SP – 6 PROG FETCH 2ND PIPE B:A SP – 8 PRELIMINARY Freescale Semiconductor, Inc... CCR SP – 9 PROG FETCH 3RD PIPE 1ST EXEC Freescale Semiconductor, Inc. INTERRUPT TIM Figure 5 Interrupt Timing Diagram For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Table 11 Peripheral Port Timing Symbol Unit Min Max fo dc 5.0 MHz tcyc 200 — ns tPDSU 130 — ns Peripheral data hold time MCU read of ports tPDH 0 — ns Delay time, peripheral data write MCU write to ports tPWD — 40 ns Frequency of operation (E-clock frequency) E-clock period Peripheral data setup time MCU read of ports Freescale Semiconductor, Inc... 5.0 MHz tPDSU = tcyc/2 + 30 PRELIMINARY Characteristic MCU READ OF PORT ECLK tPDSU tPDH PORTS PORT RD TIM Figure 6 Port Read Timing Diagram MCU WRITE TO PORT ECLK tPWD PORT A PREVIOUS PORT DATA NEW DATA VALID PORT WR TIM Figure 7 Port Write Timing Diagram For More Information On This Product, Go to: www.freescale.com 13 Freescale Semiconductor, Inc. Table 12 Non-Multiplexed Expansion Bus Timing VDD = 3.3 Vdc ± 0.3V, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted Characteristic1 Num Delay Symbol PRELIMINARY Freescale Semiconductor, Inc... Frequency of operation (E-clock frequency) tcyc = 1/fo 5 MHz Min Max fo dc 5.0 MHz tcyc 200 — ns 1 Cycle time 2 Pulse width, E low PWEL = tcyc/2 + delay −2 PWEL 98 — ns 3 Pulse width, E high2 PWEH = tcyc/2 + delay −2 PWEH 98 — ns 5 Address delay time tAD = tcyc/4 + delay 29 tAD — 79 ns 6 Address hold time — tAH 20 — ns 7 Address valid time to E rise — tAV 28 — ns 11 Read data setup time — tDSR 30 — ns 12 Read data hold time — tDHR 0 — ns 13 Write data delay time 25 tDDW — 75 ns 14 Write data hold time — tDHW 20 — ns 15 Write data setup time2 tDSW = PWEH − tDDW — tDSW 23 — ns 16 Read/write delay time tRWD = tcyc/4 + delay 20 tRWD — 70 ns 17 Read/write valid time to E rise tRWV = PWEL − tRWD — tRWV 28 — ns 18 Read/write hold time — tRWH 20 — ns 19 Low strobe delay time tLSD = tcyc/4 + delay 20 tLSD — 70 ns 20 Low strobe valid time to E rise tLSV = PWEL − tLSD — tLSV 28 — ns 21 Low strobe hold time — tLSH 20 — ns 22 Address access time2 tACCA = tcyc − tAD − tDSR — tACCA — 100 ns 23 Access time from E rise2 tACCE = PWEH − tDSR — tACCE — 68 ns 26 Chip select delay time tCSD = tcyc/4 + delay 29 tCSD — 79 ns 27 Chip select access time2 tACCS = tcyc − tCSD − tDSR — tACCS — 100 ns 28 Chip select hold time — tCSH 0 10 ns 29 Chip select negated time 5 tCSN 55 — ns tAV = PWEL − tAD tDDW = tcyc/4 + delay tCSN = tcyc/4 + delay NOTES: 1. All timings are calculated for normal port drives. 2. This characteristic is affected by clock stretch. Add N × tcyc where N = 0, 1, 2, or 3, depending on the number of clock stretches. 14 Unit For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. 1 2 3 ECLK 22 7 6 5 ADDR[15:0] 23 11 12 13 15 PRELIMINARY Freescale Semiconductor, Inc... DATA[15:0] READ 14 DATA[15:0] WRITE 16 17 18 19 20 21 R/W LSTRB (W/O TAG ENABLED) 29 26 27 28 CS NOTE: Measurement points shown are 20% and 70% of V DD BUS TIM Figure 8 Non-Multiplexed Expansion Bus Timing Diagram For More Information On This Product, Go to: www.freescale.com 15 Freescale Semiconductor, Inc. Table 13 SPI Timing VDD = 3.3 Vdc ± 0.3V, VSS = 0 Vdc, TA = TL to TH , 130 pF load on all SPI pins1 PRELIMINARY Freescale Semiconductor, Inc... Num Function Symbol Min Max Unit Operating Frequency Master Slave fop DC DC 1/2 1/2 1 SCK Period Master Slave tsck 2 2 256 — tcyc tcyc 2 Enable Lead Time Master Slave tlead 1/2 1 — — tsck tcyc 3 Enable Lag Time Master Slave tlag 1/2 1 — — tsck tcyc 4 Clock (SCK) High or Low Time Master Slave twsck tcyc − 60 tcyc − 30 128 tcyc — ns ns 5 Sequential Transfer Delay Master Slave ttd 1/2 1 — — tsck tcyc 6 Data Setup Time (Inputs) Master Slave tsu 30 30 — — ns ns 7 Data Hold Time (Inputs) Master Slave thi 0 30 — — ns ns 8 Slave Access Time ta — 1 tcyc 9 Slave MISO Disable Time tdis — 1 tcyc 10 Data Valid (after SCK Edge) Master Slave tv — — 50 50 ns ns 11 Data Hold Time (Outputs) Master Slave tho 0 0 — — ns ns 12 Rise Time Input Output tri tro — — tcyc − 30 30 ns ns 13 Fall Time Input Output tfi tfo — — tcyc − 30 30 ns ns E-clock frequency NOTES: 1. All AC timing is shown with respect to 20% VDD and 70% VDD levels unless otherwise noted. 16 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. SS 1 (OUTPUT) 5 2 1 SCK (CPOL = 0) (OUTPUT) 4 13 SCK (CPOL = 1) (OUTPUT) 7 MISO (INPUT) MSB IN 2 . .1 BIT 6 . 10 LSB IN 10 MOSI (OUTPUT) MSB OUT 2 11 BIT 6 . . .1 LSB OUT 1. SS output mode (DDS7 = 1, SSOE = 1). 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB. SPI MASTER CPHA0 A) SPI Master Timing (CPHA = 0) SS 1 (OUTPUT) 5 1 2 13 12 12 13 3 SCK (CPOL = 0) (OUTPUT) 4 4 SCK (CPOL = 1) (OUTPUT) 6 MISO (INPUT) 7 MSB IN 2 BIT 6 . 11 10 MOSI (OUTPUT) PORT DATA LSB IN . .1 MASTER MSB OUT 2 BIT 6 . . . 1 MASTER LSB OUT 1. SS output mode (DDS7 = 1, SSOE = 1). 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB. PORT DATA SPI MASTER CPHA1 B) SPI Master Timing (CPHA = 1) Figure 9 SPI Timing Diagram (1 of 2) For More Information On This Product, Go to: www.freescale.com 17 PRELIMINARY 6 Freescale Semiconductor, Inc... 3 12 4 Freescale Semiconductor, Inc. SS (INPUT) 5 1 13 12 12 13 3 SCK (CPOL = 0) (INPUT) 4 2 4 SCK (CPOL = 1) (INPUT) 9 8 MISO (OUTPUT) 10 MOSI (INPUT) PRELIMINARY Freescale Semiconductor, Inc... 6 11 BIT 6 . MSB OUT SLAVE 11 . .1 SLAVE LSB OUT SEE NOTE 7 BIT 6 . MSB IN . .1 LSB IN NOTE: Not defined but normally MSB of character just received. SPI SLAVE CPHA0 A) SPI Slave Timing (CPHA = 0) SS (INPUT) 5 3 1 2 13 12 12 13 SCK (CPOL = 0) (INPUT) 4 4 SCK (CPOL = 1) (INPUT) SEE NOTE 8 MOSI (INPUT) 9 11 10 MISO (OUTPUT) SLAVE MSB OUT 6 BIT 6 . . . 1 SLAVE LSB OUT 7 MSB IN BIT 6 . . .1 LSB IN NOTE: Not defined but normally LSB of character just received. SPI SLAVE CPHA1 B) SPI Slave Timing (CPHA = 1) Figure 10 SPI Timing Diagram (2 of 2) Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. 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