MOTOROLA SEMICONDUCTOR TECHNICAL DATA Advance Information LCD Segment / Common Driver MC141531 CMOS MC141531 is a CMOS LCD Driver which consists of 3 annunciator outputs and 137 high voltage LCD driving signals (17 common and 120 segment). It has parallel interface capability for operating with general MCU. Besides the general LCD driver features, it has on chip LCD bias voltage generator circuits such that limited external component is required during application. • • • • • • • • • • • • • • • • • • Single Supply Operation, 2.4 V - 3.5 V Operating Temperature Range : -30˚C to 85˚C Low Current Stand-by Mode (<500nA) On Chip Bias DC/DC Converter 8 bit Parallel Interface Graphic Mode Operation On Chip 120x17 Graphic Display Data RAM Master clear RAM 120 Segment Drivers, 17 Common Drivers 1/16, 1/17 Multiplex Ratio 1:5 bias ratio Re-mapping of Row and Column Drivers Three Stand Alone Annunciator (Static Icon) Driver Circuits Low Power Icon Mode Driven by Com16 in Special Driving Scheme Selectable LCD Drive Voltage Temperature Coefficients 16 level Internal Contrast Control External Contrast Control Standard TAB (Tape Automated Bonding) Package, Gold Bump Die MC141531T TAB MCC141531Z Gold Bump Die ORDERING INFORMATION MC141531T TAB MCC141531Z Gold Bump Die This document contains information on a new product. Specifications and information herein are subject to change without notice. REV 4 3/97 MOTOROLA MC141531 3–139 Block Diagram Annun0 to Annun2 BP Com0 to Com16 Seg0~Seg119 Level Selector HV Buffer Cell Level Shifter Annunciator Control Circuit VLL6 17 Bit Latch OSC1 VLL2 120 Bit Latch VCC VR Display Timing Generator OSC2 VF GDDRAM 17 x 120Bits LCD Driving DC/DC Converter C2P Tripler, Doubler, Voltage Regulator, Voltage Divider, Contrast Control, Temperature Compensation C1P C2N C1N C+ CAVDD AVSS Command Decoder DVSS DVDD Command Interface RES MC141531 3–140 D/C CS (CLK) Parallel Interface R/W D0~D7 MOTOROLA MC141531T PIN ASSIGNMENT (COPPER VIEW) MOTOROLA MC141531 3–141 DUMMY OSC2 AVSS VR VF VCC CC+ VLL6 VLL5 VLL4 OSC1 VLL3 VLL2 C1N C1P C2N C2P AVDD D7 D6 D5 D4 D3 D2 D1 D0 DVSS CS (CLK) R/W D/C RES DVDD DUMMY 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 174 173 172 171 170 169 . . . . . . . 160 159 158 157 156 155 154 153 152 . . . . . . . . . . . . . . . . . . . . . . . . 39 38 37 36 35 34 33 DUMMY COM16 COM0 COM1 COM2 COM3 COM4 . . . . . . . COM13 COM14 COM15 COM16 SEG0 SEG1 SEG2 SEG3 SEG4 . . . . . . . . . . . . . . . . . . . . . . . . SEG117 SEG118 SEG119 ANNUN0 ANNUN1 ANNUN2 BP DUMMY MC141531 Die Pin Assignment COM10 COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM0 COM16 191 180 179 1 X M Y OSC2 AVSS VR VF VCC CC+ VLL6 VLL5 VLL4 OSC1 VLL3 VLL2 C1N C1P C2N C2P AVDD AVDD DVSS DVSS DVSS D7 DVSS D6 DVSS D5 DVSS D4 DVSS D3 DVSS D2 DVSS D1 DVSS D0 DVSS CS DVSS R/W DVSS D/C RES DVDD BP DVSS ANNUN2 DVSS ANNUN1 DVSS ANNUN0 DVSS 53 COM11 COM12 COM13 COM14 COM15 COM16 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 SEG62 SEG63 SEG64 SEG65 SEG66 SEG67 SEG68 SEG69 SEG70 SEG71 SEG72 SEG73 SEG74 SEG75 SEG76 SEG77 SEG78 SEG79 SEG80 SEG81 SEG82 SEG83 SEG84 SEG85 SEG86 SEG87 SEG88 SEG89 SEG90 SEG91 SEG92 SEG93 SEG94 SEG95 SEG96 SEG97 SEG98 SEG99 SEG100 SEG101 SEG102 SEG103 SEG104 SEG105 SEG106 SEG107 66 54 65 SEG108 SEG109 SEG110 SEG111 SEG112 SEG113 SEG114 SEG115 SEG116 SEG117 SEG118 SEG119 MC141531 3–142 MOTOROLA MAXIMUM RATINGS* (Voltages Referenced to VSS, TA=25˚C) Symbol AVDD,DVDD Parameter Value Supply Voltage VCC Vin Input Voltage I Current Drain Per Pin Excluding VDD and VSS TA Tstg Unit -0.3 to +4.0 V VSS-0.3 to VSS+10.5 V VSS-0.3 to VDD+0.3 V 25 mA Operating Temperature -30 to +85 ˚C Storage Temperature Range -65 to +150 ˚C * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the limits in the Electrical Characteristics tables or Pin Description section. VSS = AVSS = DVSS (DVSS = VSS of Digital circuit, AVSS = VSS of Analogue Circuit) VDD = AVDD = DVDD (DVDD = VDD of Digital circuit, AVDD = VDD of Analogue Circuit) This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions to be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation it is recommended that Vin and Vout be constrained to the range VSS < or = (Vin or Vout) < or = VDD. Reliability of operation is enhanced if unused input are connected to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. This device may be light sensitive. Caution should be taken to avoid exposure of this device to any light source during normal operation. This device is not radiation protected. ELECTRICAL CHARACTERISTICS (Voltage Referenced to VSS, VDD=2.4 to 3.5V, TA=25˚C) Symbol Test Condition Min Typ Max Unit Logic Circuit Supply Voltage Range DC/DC Converter Circuit Supply Voltage Range (Absolute value referenced to VSS) 2.4 2.4 3.0 - 3.5 3.5 V V IAC Access Mode Supply Current Drain (AVDD + DVDD Pins) 0 200 300 µA IDP Display Mode Supply Current Drain (AVDD + DVDD Pins) VDD=3.0V, Internal DC/DC Converter On, Tripler Enabled, Annunciator On/Off, R/W accessing, Tcyc=1MHz, Osc. Freq.=38.4kHz, Display On, 1/7 Mux Ratio VDD=3.0V, Internal DC/DC Converter On, Tripler Enabled, Annunciator On/Off, R/W halt, Osc. Freq.=38.4kHz, Display On, 1/17Mux Ratio 0 75 165 µA ISB1 Standby Mode Supply Current Drain (AVDD + DVDD Pins) 0 300 500 nA 0 5 10 µA 0 - 25 µA DVDD AVDD ISB2 Parameter Annunciator Mode Supply Current Drain (AVDD + DVDD Pins) ISB3 Icon Mode Supply Current Drain (AVDD + DVDD Pins) VCC1 VCC2 VLCD VDD=3.0V, Display off, Oscillator Disabled, R/W halt. VDD=3.0V, Annunciator Mode, Internal Oscillator, Oscillator Enabled, Display Off, R/W halt, Int Osc. Freq.=38.4kHz. VDD=3.0V, Icon Mode, Internal Oscillator, Oscillator Enabled, Display Off, R/W halt, Ext Osc. Freq.=38.4kHz. LCD Driving DC/DC Converter Output (VCC Pin) Display On, Internal DC/DC Converter Enabled, Tripler Enabled, Osc. Freq.=38.4KHz, Regulator Enabled, Divider Enabled. - 3*AVDD 10.5 V LCD Driving DC/DC Converter Output (VCC Pin) Display On, Internal DC/DC Converter Enabled, Doubler Enabled, Osc. Freq.=38.4KHz, Regulator Enabled, Divider Enabled. - 2*AVDD 7 V LCD Driving Voltage Input (VCC Pin) Internal DC/DC Converter Disabled. 5 - 10.5 V MOTOROLA MC141531 3–143 ELECTRICAL CHARACTERISTICS (Voltage Referenced to VSS, VDD=2.4 to 3.5V, TA=25˚C) Symbol Min Typ Max Unit VIH1 Input high voltage (RES, OSC2, CS, D0-D7, R/W, D/C, OSC1) 0.8*VDD - VDD V VIL1 Input Low voltage (RES, OSC2, CS, D0-D7, R/W, D/C, OSC1) 0 - 0.2*VDD V VLL6 VLL5 VLL4 VLL3 VLL2 LCD Display Voltage Output (VLL6, VLL5, VLL4, VLL3, VLL2 Pins) Voltage Divider Enabled - VR 0.8*VR 0.6*VR 0.4*VR 0.2*VR - V V V V V VLL6 VLL5 VLL4 VLL3 VLL2 LCD Display Voltage Input (VLL6, VLL5, VLL4, VLL3, VLL2 Pins) External DC/DC Converter, Voltage Divider Disable 5 0 0 0 0 - VCC VLL6 VLL5 VLL4 VLL3 V V V V V IOH Output High Current Source (D0-D7, Annun0-2, BP, OSC2) Vout=VDD-0.4V 50 - - µA Output Low Current Drain (D0-D7, Annun0-2, BP, OSC2) Vout=0.4V - - -50 µA -1 - 1 µA -1 - 1 µA IOL IOZ Parameter Test Condition Output Tri-state Current Drain Source (D0-D7, OSC2) IIL/IIH Input Current (RES, OSC2, CS, D0-D7, R/W, D/C , OSC1) Ron Channel resistance between LCD driving signal pins (SEG and COM) and driving voltage input pins (VLL2 to VLL6) During Display on, 0.1V apply between two terminals, VCC within operating voltage range - - 10 kΩ VSB Memory Retention Voltage (DVDD) Standby mode, retain all internal configuration and RAM data 2 - - V CIN Input Capacitance (OSC1, OSC2, all logic pins) - 5 7.5 pF TC1=0, TC2=0, Voltage Regulator Disabled TC1=0, TC2=1, Voltage Regulator Enabled TC1=1, TC2=0, Voltage Regulator Enabled TC1=1, TC2=1, Voltage Regulator Enabled - 0.0 -0.18 -0.22 -0.35 - % % % % Regulator Enabled, Internal Contrast control Enabled. (16 Voltage Levels Controlled by Software. Each level is typically 2.25% of the Regulator Output Voltage. ) - ± 18 - % PTC0 PTC1 PTC2 PTC3 VCN Temperature Coefficient Compensation* Flat Temperature Coefficient Temperature Coefficient 1* Temperature Coefficient 2* Temperature Coefficient 3* Internal Contrast Control (VR Output Voltage) *The formula for the temperature coefficient (TC) is: TC(%)= VR at 50˚C - VR at 0˚C 50˚C - 0˚C MC141531 3–144 X 1 X100% VR at 25˚C MOTOROLA AC ELECTRICAL CHARACTERISTICS (TA=25˚C, Voltage referenced to VSS, AVDD=DVDD=3V) Symbol Min Typ Max Unit FOSC Oscillation Frequency of Display timing generator Parameter 60Hz Frame Frequency Either External Clock Input or Internal Oscillator Enabled Test Condition - 38.4 - kHz FANN Backplane Frequency of Annunciator (Annun0-3, BP) 50% duty cycle Annunciator on, Fosc=38.4KHz - 30 - Hz FFRM Frame Frequency Graphic Display Mode, Timing generator freq. = 38.4kHz - 60 - Hz Icon Mode, Timing generator freq. = 38.4kHz OSC Internal Oscillation Frequency with different value of feedback resistor TBD Internal Oscillator Enabled, VDD within operation range See Figure 1 for the relationship Note: FFRM = FOSC / 640 FANN = FOSC / 1280 280k 260k 90k 70k Oscillation Frequency (Hz) 50k 30k 10k 100k 500k 1.0M 1.5M 2.0M Resistor Value between OSC1 and OSC2 (Ω) Figure 1. Internal Oscillator Frequency Relationship with External Resistor Value MOTOROLA MC141531 3–145 TABLE 2a. Parallel Timing Characteristics (Write Cycle) (TA=-30 to 85˚C, DVDD=2.4 to 3.5V, VSS=0V) Symbol Min Typ Max Unit tcycle Enable Cycle Time Parameter 600 - - ns tEH Enable Pulse Width 290 - - ns tAS Address Setup Time 5 - - ns tDS Data Setup Time 290 - - ns tDH Data Hold Time 20 - - ns tAH Address Hold Time 20 - - ns tcycle CS tEH R/W tAH tAS D/C tDS D0-D7 tDH Valid Data Figure 3. Timing Characteristics (Write Cycle) MC141531 3–146 MOTOROLA TABLE 2b. Parallel Timing Characteristics (Read Cycle) (TA=-30 to 85˚C, DVDD=2.4 to 3.5V, VSS=0V) Symbol Min Typ Max Unit tcycle Enable Cycle Time Parameter 600 - - ns tEH Enable Pulse Width 290 - - ns tAS Address Setup Time 5 - - ns tDS Data Setup Time - - 290 ns tDH Data Hold Time 5 - - ns tAH Address Hold Time 20 - - ns tcycle CS tEH R/W tAH tAS D/C tDS D0-D7 tDH Valid Data Figure 4. Timing Characteristics (Read Cycle) MOTOROLA MC141531 3–147 PIN DESCRIPTIONS D/C (Data / Command) This input pin tell the LCD driver the input at D0-D7 is data or command. Input High for data while input Low for command. CS (CLK) (Input Clock) This pin is normal Low clock input. Data on D0-D7 are latched at the falling edge of CS. RES (Reset) An active Low pulse to this pin reset the internal status of the driver (same as power on reset). The minimum pulse width is 10 µs. D0-D7 (Data) This bi-directional bus is used for data / command transferring. R/W (Read / Write) This is an input pin. To read the display data RAM or the internal status (Busy / Idle), pull this pin High. The R/W input Low indicates a write operation to the display data RAM or to the internal setup registers. OSC1 (Oscillator Input) For internal oscillator mode, this is an input for the internal low power RC oscillator circuit. In this mode, an external resistor of certain value should be connected between the OSC1 and OSC2 pins for a range of internal operating frequencies (refer to Figure 1). For external oscillator mode, OSC1 should be left open. OSC2 (Oscillator Output / External Oscillator Input) For internal oscillator mode, this is an output for the internal low power RC oscillator circuit. For external oscillator mode, OSC2 will be an input pin for external clock and no external resistor is needed. VLL6 - VLL2 Group of voltage level pins for driving the LCD panel. They can either be connected to external driving circuit for external bias supply or connected internally to built-in divider circuit if internal divider is enable. For Internal DC/DC Converter enabled, a 0.1 µF capacitor to AVSS is required on each pin. C1N and C1P If Internal DC/DC Converter is enabled, a 0.1 µF capacitor is required to connect these two pins. C2N and C2P If Internal DC/DC Converter and Tripler are enabled, a 0.1 µF capacitor is required between these two pins. Otherwise, leave these pins open. MC141531 3–148 C+ and CIf internal divider circuit is enabled, a 0.1 µF capacitor is required to connect between these two pins. VR and VF This is a feedback path for the gain control (external contrast control) of VLL1 to VLL6. For adjusting the LCD driving voltage, it requires a feedback resistor placed between VR and VF, a gain control resistor placed between VF and AVSS, a 10 µF capacitor placed between VR and AVSS. (Refer to the Application Circuit) COM0-COM16 (Row Drivers) These pins provide the row driving signal to LCD panel. Output is 0V during display off. COM16 also serves as the common driving signal in the icon mode. SEG0-SEG119 (Column Drivers) These 120 pins provide LCD column driving signal to LCD panel. They output 0V during display off. BP (Annunciator Backplane) This pin combines with Annun0-Annun2 pins to form annunciator driving part. When the annunciator circuit is enabled, it will output square wave of 30 Hz. It outputs low when oscillator is disabled. Annun0 - Annun2 (Annunciator Frontplanes) These pins are three independent annunciator driving outputs. The enabled annunciator outputs from its corresponding pin a 30Hz square wave which is 180 degrees out of phase with BP. Disabled annunciator output from its corresponding pin an square wave inphase with BP. When all annunciators are disabled, all these pins output 0V. AVDD and AVSS AVDD is the positive supply to the LCD bias Internal DC/DC Converter. AVSS is ground. VCC For using the Internal DC/DC Converter, a 0.1 µF capacitor from this pin to AVSS is required. It can also be an external bias input pin if Internal DC/DC Converter is not used. Power is supplied to the LCD Driving Level Selector and HV Buffer Cell with this pin. Normally, this pin is not intended to be a power supply to other component. DVDD and DVSS Power is supplied to the digital control circuit of the driver using these two pins. DVDD is power and DVSS is ground. MOTOROLA OPERATION OF LIQUID CRYSTAL DISPLAY DRIVER Description of Block Diagram Module Command Decoder and Command Interface This module determines whether the input data is interpreted as data or command. Data is directed to this module based upon the input of the D/C pin. If D/C high, data is written to Graphic Display Data RAM (GDDRAM). D/C low indicates that the input at D0-D7 is interpreted as a Command. Reset is of same function as Power ON Reset (POR). Once RES received the reset pulse, all internal circuitry will back to its initial status. Refer to Command Description section for more information. MPU Parallel Interface The parallel interface consists of 8 bi-directional data lines (D0D7), R/W, and the CS. The R/W input High indicates a read operation from the Graphic Display Data RAM (GDDRAM). R/W input Low indicates a write operation to Display Data RAM or Internal Command Registers depending on the status of D/C input. The CS input serves as data latch signal (clock). Refer to AC operation conditions and characteristics section for Parallel Interface Timing Description. Graphic Display Data RAM (GDDRAM) The GDDRAM is a bit mapped static RAM holding the bit pattern to be displayed. The size of the RAM is determined by number of row times the number of column (120x17 = 2040 bits). Figure 5 is a description of the GDDRAM address map. For mechanical flexibility, re-mapping on both Segment and Common outputs are provided. Column address 00H (or column address 77H) Row 0 Column address 77H (or column address 00H) Com0 (Com15) LSB Page 1 MSB LSB Page 2 MSB Note : The configuration in parentheses represent the remapping of Rows and Columns Com15 (Com0) Com16 Seg119 Row 16 LSB Page 3 Seg0 Row 15 Figure 5. Graphic Display Data RAM (GDDRAM) Address Map MOTOROLA MC141531 3–149 Display Timing Generator This module is an on chip low power RC oscillator circuitry (Figure 6). The oscillator frequency can be selected in the range of 15kHz to 50kHz by external resistor. One can enable the circuitry by software command. For external clock provided, feed the clock to OSC2 and leave OSC1 open. Annunciator Control Circuit The LCD waveform of the 3 annunciators and BP are generated by this module. The 3 independent annunciators are enabled by software command. Annunciator is also controlled by oscillator circuit. Before turning the annunciators on, the oscillator must be on in advance. Annunciator output waveform shown in Figure 7. Oscillator enable Internal Oscillator selected enable1 enable2 Oscillation Circuit enable Buffer MC141531 OSC2 OSC1 External component Feedback for internal oscillator For external CLK input Figure 6. Oscillator Circuitry DVDD BP DVSS DVDD ANNUN1 DVSS DVDD ANNUN2 DVSS ANNUN1 ON / OFF ON ON ON ON ON / OFF ANNUN2 ON / OFF OFF ON ON OFF ON / OFF OSC DISABLE ENABLE ENABLE ENABLE ENABLE DISABLE Figure 7. Annunciators and BP Display Waveform LCD Driving Internal DC/DC Converter and Regulator This module generates the LCD voltage needed for display output. It takes a single supply input and generate necessary bias voltages. It consists of : 1. Voltage Doubler and Voltage Tripler To generate the Vcc voltage. Either Doubler or Tripler can be enabled. 2. Voltage Regulator Feedback gain control for initial LCD voltage. It can also be used with external contrast control. 3. Voltage Divider Divide the LCD display voltage (VLL2-VLL6) from the regulator output. This is a low power consumption circuit which can save the most display current compare with traditional resistor ladder method. 4. Self adjust temperature compensation circuitry Provide 4 different compensation grade selections to satisfy the various liquid crystal temperature grades. The grading can be selected by software control. 5. Contrast Control Block Software control of 16 voltage levels of LCD voltage. All blocks can be individually turned off if external DC/DC Converter is employed. MC141531 3–150 17 Bit Latch / 120 Bit Latch A 137 bit long register which carry the display signal information. First 17 bits are Common driving signals and other 120 bits are Segment driving signals. Data will be input to the HV-buffer Cell for bumping up to the required level. Level Selector Level Selector is a control of the display synchronization. Display voltage can be separated into two sets and used with different cycles. Synchronization is important since it selects the required LCD voltage level to the HV Buffer Cell for output signal voltage pump. HV Buffer Cell (Level Shifter) HV Buffer Cell works as a level shifter which translates the low voltage output signal to the required driving voltage. The output is shifted out with an internal FRM clock which comes from the Display Timing Generator. The voltage levels are given by the level selector which is synchronized with the internal M signal. MOTOROLA LCD Panel Driving Waveform COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 SEG0 SEG1 SEG2 SEG3 SEG4 The following is an example of how the Common and Segment drivers may be connected to a LCD panel. The waveforms shown in Figure 8a, 8b and 8c illustrate the desired multiplex scheme. Figure 8a. LCD Display Example “0” MOTOROLA MC141531 3–151 TIME SLOT 1 2 3 4 1 2 3 4 COM0 VLL6 VLL5 VLL4 VLL3 VLL2 VLL1 COM1 VLL6 VLL5 VLL4 VLL3 VLL2 VLL1 SEG0 VLL6 VLL5 VLL4 VLL3 VLL2 VLL1 SEG1 VLL6 VLL5 VLL4 VLL3 VLL2 VLL1 Figure 8b. LCD Driving Signal from MC141531 TIME SLOT 1 2 3 4 1 2 3 4 Seg0-Com0 “OFF” Pixel VLL6 VLL5 VLL4 VLL3 VLL2 VLL1 -VLL2 -VLL3 -VLL4 -VLL5 -VLL6 Seg0-Com1 “On” Pixel VLL6 VLL5 VLL4 VLL3 VLL2 VLL1 -VLL2 -VLL3 -VLL4 -VLL5 -VLL6 Figure 8c. Effective LCD waveform on LCD pixel MC141531 3–152 MOTOROLA Command Description Set Display On/Off (Display Mode / Stand-by Mode) The Display On command turns the LCD Common and Segment outputs on and has no effect to the annunciator output. This command starts the conversion of data in GDDRAM to necessary waveforms on the Common and Segment driving outputs. The on-chip bias generator is also turned on by this command. (Note: “Set Oscillator On” command should be sent before “Set Display On”) The Display Off command turn the display off and the states of the LCD driver are as follow during display off: 1. The Common and Segment outputs are fixed at VLL1 (VSS). 2. The bias Internal DC/DC Converter is turned off. 3. The RAM and content of all registers are retained. 4. IC will accept new commands and data. The status of the Annunciators and Oscillator are not affected by this command. Note: DON’T USE ICON DISPLAY MODE DURING DISPLAY OFF. Set GDDRAM Column Address This command positions the address pointer on a column location. The address can be set to location 00H-77H (120 columns). The column address will be increased automatically after a read or write operation. Refer to “Address Increment Table” and command “Set GDDRAM Page Address” for further information. Set GDDRAM Page Address This command positions the row address to 1 of 3 possible positions in GDDRAM. Refer to figure 5. Master Clear GDDRAM This command is to clear the content of page 1 and 2 of the Display Data RAM to zero. Issue this command followed by a dummy write command. Master Clear Icons This command is used to clear the data in page 3 of GDDRAM which stores the icon line data. Before using this command, set the page address to Page 3 by the command “Set GDDRAM Page Address”. A dummy write data is also needed after this “Master Clear Icons” command to make the clear icon action effective. Set Display Mode This command switch the driver to full display mode or low power icon mode. In low power icon mode, only icons (driven by COM16) and annunciators are displayed, and the DC-DC converter, the Internal DC/DC Converter and the regulator are disabled. Do select 1/17 Mux ratio before using the low power icon mode. Note: DON’T USE ICON DISPLAY MODE DURING DISPLAY OFF. Set Multiplex Ratio In normal display mode, the multiplex ratio could be set to be 1/16 or 1/17. For 1/16 Mux Ratio, COM16 signal should not be connected to the panel. Set Icon Mode A/B In Icon mode A, on-pixels are stressed by a voltage with rootmean-square value of 0.87xVDD, whereas off-pixels by 0.5xVDD. In icon mode B, on-pixels are stressed by a voltage with root-meansquare value of 0.71xVDD, whereas off-pixels by 0.41xVDD. This command is used to control the contrast of the icon line (Com16) under icon mode MOTOROLA Set Vertical Scroll Value This command maps the selected GDDRAM row (00H-0FH) to Com0. With scroll value equals to 0, Row 0 of GDDRAM is mapped to Com0 and Row 1 through Row 15 are mapped to Com1 through Com15 respectively. With scroll value equal to 1, Row 1 of GDDRAM is mapped to Com0, then Row 2 through Row 15 will be mapped to Com1 through Com14 respectively and Row 0 will be mapped to Com15. Save / Restore Column Address With bit option = 1 in this command, the Save / Restore Column Address command saves a copy of the Column Address of GDDRAM. With a bit option = 0, this command restores the copy obtained from the previous execution of saving column address. This instruction is very useful for writing full graphics characters that are larger than 8 pixels vertically. Set Column Mapping This instruction selects the mapping of GDDRAM to Segment drivers for mechanical flexibility. There are 2 mappings to select: 1. Column 0 - Column 119 of GDDRAM mapped to Seg0-Seg119 respectively; 2. Column 0 - Column 119 of GDDRAM mapped to Seg119-Seg0 respectively. Detail information please refer to section “Display Output Description”. Set Row Mapping This command selects the mapping of GDDRAM to Common Drivers for mechanical flexibility. There are 2 mappings to select: 1. Row 0 - Row 15 of GDDRAM to Com0 - Com15 respectively; 2. Row 0 - Row 15 of GDDRAM to Com15 - Com0 respectively. Output of Row 16 (Com16) will not be changed by this command. See section “Display Output Description” for related information. Set Annunciator Control Signals This command is used to control the active states of the 3 stand alone annunciator drivers. Set Oscillator Enable / Disable This command is used to either turn on or off the oscillator. For using internal or external oscillator, this command should be executed. The setting for this command is not affected by command “Set Display On/Off” and “Set Annunciator Control Signal”. See command “Set Internal / External Oscillator” for more information Set Internal / External Oscillator This command is used to select either internal or external oscillator. When internal oscillator is selected, feedback resistor between OSC1 and OSC2 is needed. For external oscillation circuit, feed clock input signal to OSC2 and leave OSC1 open. Set Internal DC/DC Converter On/Off Use this command to select the Internal DC/DC Converter to generate the VCC from AVDD. Disable the Internal DC/DC Converter if external Vcc is provided. Set Voltage Doubler / Tripler Use this command to choose Doubler or Tripler when the Internal DC/DC Converter is enabled. MC141531 3–153 Set Internal Regulator On/Off Choose bit option 0 to disable the Internal Regulator. Choose bit option 1 to enable Internal Regulator which consists of the internal contrast control and temperature compensation circuits. Increase / Decrease Contrast Level If the internal contrast control is enabled, this command is used to increase or decrease the contrast level within the 16 contrast levels. The contrast level starts from lowest value after POR. Set Internal Voltage Divider On/Off If the Internal Voltage Divider is disabled, external bias can be used for VLL6 to VLL2. If the Internal Voltage Divider is enabled, the internal circuit will generated the 1:5 bias driving voltage. Set Contrast Level This command is to select one of the 16 contrast levels when internal contrast control circuitry is in use. After power-on reset, the contrast level is the lowest. Set Internal Contrast Control On/Off This command is used to turn on or off the internal control of delta voltage of the bias voltages. With bit option = 1, the software selection for delta bias voltage control is enabled. With bit option = 0, internal contrast control is disabled. Set Temperature Coefficient This command can select 4 different LCD driving voltage temperature coefficients to match various liquid crystal temperature grades. Those temperature coefficients are specified in Electrical Characteristics Tables. COMMAND TABLE Bit Pattern Command Comment 000000X1X0 Set GDDRAM Page Address Set GDDRAM Page Address using X1X0 as address bits. X1X0=00 : page 1 (POR) X1X0=01 : page 2 X1X0=10 : page 3 0001X3X2X1X0 Set Contrast Level With R/W pin input low, set one of the 16 available values to the internal contrast register, using X3X2X1X0 as data bits. The contrast register is reset to 0000 during POR. 0010000X0 Set Voltage Doubler / Tripler X0=0 : Set Voltage Tripler (POR) X0=1 : Set Voltage Doubler 0010001X0 Set Column Mapping X0=0 : Col0 to Seg0 (POR) X0=1 : Col0 to Seg119 0010010X0 Set Row Mapping X0=0 : Row0 to Com0 X0=1 : Row0 to Com15 0010100X0 Set Display On/Off X0=0 : display off (POR) X0=1 : display on 0010101X0 Set Internal DC/DC Converter On/Off X0=0 : Internal DC/DC Converter off(POR) X0=1 : Internal DC/DC Converter on 0010110X0 Set Internal Regulator On/Off X0=0 : Internal Regulator off(POR) X0=1 : Internal Regulator on When application uses a supply with built-in temperature compensation, the regulator should be disabled. 0010111X0 Set Internal Voltage Divider On/Off X0=0 : Internal Voltage Divider off (POR) X0=1 : Internal Voltage Divider on When an external bias network is preferred, the voltage divider should be disabled. 0011000X0 Set Internal Contrast Control On/Off X0=0 : Internal Contrast Control off (POR) X0=1 : Internal Contrast Control on Internal contrast circuits can be disabled if external contrast circuits is preferred. 0011001X0 Set Display Mode X0=0 : normal display mode (1/16 or 1/17 mux) (POR) X0=1 : low power icon display mode 0011010X0 Save/Restore GDDRAM Column Address X0=0 : restore address X0=1 : save address 00110110 Master Clear GDDRAM Master clear page 1 and 2 of GDDRAM 00110111 Master Clear of Icons Master Clear of icon line (Com16) 0011101X0 Reserved. X0=0: normal operation (POR) X0=1: test mode (Note: Make sure to set X0=0 during application) MC141531 3–154 MOTOROLA Bit Pattern Command Comment 0011110X0 Set Multiplex Ratio X0=0 : 1/16 Mux ratio (POR) X0=1 : 1/17 Mux ratio 0011111X0 Set Icon Mode A/B X0=0 : icon mode A (POR) X0=1 : icon mode B 0100X3X2X1X0 Set Vertical Scroll Value Use X3X2X1X0 as number of lines to scroll. Scroll value = 0 upon POR 01100A1A0X0 Set Annunciator Control Signals A1A0=00 : select annunciator 1 (POR) A1A0=01 : select annunciator 2 A1A0=10 : select annunciator 3 X0=0 : turn selected annunciator off (POR) X0=1 : turn selected annunciator on 01101000 Reserved 011011X1X0 Set Temperature Coefficient X1X0= 00 : 0.00% (POR) X1X0= 01 : -0.18% X1X0= 10 : -0.22% X1X0= 11 : -0.35% 0111000X0 Increase / Decrease Contrast Value X0=0 : Decrease by one X0=1 : Increase by one (Note: increment/decrement wraps round among the 16 contrast levels. Start at the lowest level when POR.) 0111011X0 Reserved X0=0: normal operation (POR) X0=1: test mode select (Note: Make sure to set X0=0 during application) 0111101X0 Set External / Internal Oscillator X0=0: External oscillator (POR) X0=1: Internal oscillator. For internal oscillator place a resistor between OSC1 and OSC2. For external oscillator mode, feed clock input to OSC2. 0111111X0 Set Oscillator Disable / Enable X0=0: oscillator master disable (POR) X0=1: oscillator master enable. This is the master control for oscillator circuitry. This command should be issued after the “External / Internal Oscillator” command. 1X6X5X4X3X2X1X0 Set GDDRAM Column Address Set GDDRAM Column Address. Use X6X5X4X3X2X1X0 as address bits. Data Read / Write To read data from the GDDRAM, input High to R/W pin and D/C pin. Data is valid at the falling edge of CS. And the GDDRAM column address pointer will be increased by one automatically. To write data to the GDDRAM, input Low to R/W pin and High to D/C pin. Data is latched at the falling edge of CS. And the GDDRAM column address pointer will be increased by one automatically. No auto address pointer increment will be performed for the Dummy Write Data after Master Clear GDDRAM. (Refer to the “Commands Required for R/W Actions on RAM” Table) MOTOROLA MC141531 3–155 Address Increment Table (Automatic) D/C R/W Comment Address Increment 0 0 Write Command No Remarks 0 1 Read Command No (invalid mode) *1 1 0 Write Data Yes *2 1 1 Read Data Yes Address Increment is done automatically data read write. The column address pointer of GDDRAM*3 is affected. Remarks : *1. Only data is read from RAM. *2. If write data is issued after Command Clear RAM, Address increase is not applied. *3. Column Address will be wrapped round when overflow. Power Up Sequence (Commands Required) Command Required POR Status Set External / Internal Oscillator Set Voltage Tripler / Doubler Internal DC/DC Converter On Set Internal Regulator On Set Temperature Coefficient Set Internal Contrast On Set Contrast Level Set Internal Voltage Divider On Set Column Mapping Set Row Mapping Set Vertical Scroll Value Set Oscillator Enable Set Annunciator Control Signals Master Clear GDDRAM Dummy Write Data Set Display On External Tripler Off Off TC=0% Off Contrast Level = 0 Off Seg. 0 = Col. 0 Com. 0 = Row 0 Scroll Value = 0 Disable Annunciators all off Random MC141531 3–156 Remarks *1 *1 *1 *1 *1, *3 *1, *3 *1, *2, *3 *1 *1 *1 *1 Remarks : *1 -- Required only if desired status differ from POR. *2 -- Effective only if Internal Contrast Control is enabled. *3 -- Effective only if Regulator is enabled. *1 Off MOTOROLA Commands Required for Display Mode Setup Display Mode Commands Required Normal Display Mode Set External / Internal Oscillator Set Oscillator Enable, Set Display On. (0111101X0)* (01111111)* (00101001)* Icon Display Mode Set Internal Oscillator Set Oscillator Enable, Set Display Mode to Icon Display Mode Set Display On. (01111011)* (01111111)* (00110011)* (00101001)* Annunciator Display Set External / Internal Oscillator Set Oscillator Enable, Set Annunciator On/Off. (0111101X0)* (01111111)* (01100A1A0X0)* Standby Mode Set Display Off, Set Oscillator Disable. (00101000)* (01111110)* Other Related Command with Display Mode: Set Column Mapping, Set Row Mapping, Set Vertical Scroll Value. Commands Related to Internal DC/DC Converter: Set Oscillator Disable / Enable, Set Internal Regulator On/Off, Set Temperature Coefficient, Set Internal Contrast Control On/Off, Increase / Decrease Contrast Level, Set Internal Voltage Divider On/Off, Set Display On/Off, Set Internal / External Oscillator, Set Contrast Level, Set Voltage Doubler / Tripler * No need to resend the command again if it is set previously. Commands Required for R/W Actions on RAM R/W Actions on RAMs Commands Required Read/Write Data from/to GDDRAM. Set GDDRAM Page Address Set GDDRAM Column Address Read/Write Data (000000X1X0)* (1X6X5X4X3X2X1X0)* (X7X6X5X4X3X2X1X0) Save/Restore GDDRAM Column Address. Save/Restore GDDRAM Column Address. (0011010X0) Increase GDDRAM Column Address by One Dummy Read Data (X7X6X5X4X3X2X1X0) Master Clear GDDRAM Master Clear GDDRAM Dummy Write Data (00110110) (X7X6X5X4X3X2X1X0) * No need to resend the command again if it is set previously. The read / write action to the Display Data RAM does not depend on the display mode. This means the user can change the RAM content whether the target RAM content is being displayed. MOTOROLA MC141531 3–157 Display Output Description This is an example of output pattern on the LCD panel. The following table is a description of what is inside the CDDRAM, CGRAM and GDDRAM. Figure 9b and 9c are the output pattern on the LCD display with different command enabled. COM0 (Display Mode, Page Swapping, Scrolling, Column Re-map and Row Re-map) COM16 SEG0 SEG119 Figure 9a Content of GDDRAM PAGE 1 5 A 5 A 5 A 5 A - - - - - - - - - - - - - - - - - 0 0 0 0 0 0 0 0 5 A 5 A 5 A 5 A - - - - - - - - - - - - - - - - - 0 0 0 0 0 0 0 0 PAGE 2 3 3 C C 3 3 C C - - - - - - - - - - - - - - - - - 3 3 C C 3 3 C C 3 3 C C 3 3 C C - - - - - - - - - - - - - - - - - 3 3 C C 3 3 C C Figure 9b Column remap disable Row re-map disable Column remap enable Row re-map disable Column remap disable Row re-map enable Column remap disable Row re-map disable Scroll Value = 0Fh Figure 9c. Examples of LCD display with different command enabled MC141531 3–158 MOTOROLA PACKAGE DIMENSIONS MC141531T TAB PACKAGE DIMENSION - 1 98ASL00247A ISSUE0 COPPER SIDE MOTOROLA MC141531 3–159 PACKAGE DIMENSIONS MC141531T TAB PACKAGE DIMENSION - 2 98ASL00247A ISSUE0 MC141531 3–160 MOTOROLA Application Circuit 16/17 MUX Display with Analog Circuitry enabled, Tripler enabled and 1:5 bias DVDD 0.1µF DVSS DVDD AVDD 0.1µF AVDD AVSS 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF VLL2 VLL3 VLL4 VLL5 VLL6 COM0 to COM16 RES D/C CMOS MPU/ MCU with Parallel Interface VCC SEG0 to SEG119 MC141531 CS To LCD Panel Annun 0-2 and BP R/W D0~D7 OSC2 EPROM OSC1 C+ C- VF VR C2P C2N C1P C1N 760kΩ RAM 1MΩ 0.1µF 560pF 200kΩ 0.1µF 4.7µF 0.1µF Remark : 1. Capacitor between C2N and C2P can be omitted only if doubler is enable. 2. Resistor across OSC1 and OSC2 can be omitted if external oscillator is used. 3. VR and VF can be left open for Regulator disable, TC = 0% and Contrast Disable. 4. RES, CS, R/W and D/C should be at a known state. 5. CS line low at Standby Mode. MOTOROLA MC141531 3–161 Application Circuit 16/17 MUX Display with Analog Circuit disabled, External Bias DVDD 0.1µF DVSS DVDD AVDD VCC 0.1µF AVDD AVSS VLL2 VLL3 VLL4 VLL5 VLL6 COM0 to COM16 RES D/C CMOS MPU/ MCU with Parallel Interface VCC SEG0 to SEG119 MC141531 CS To LCD Panel Annun 0-2 and BP R/W D0~D7 OSC2 OSC1 EPROM C+ C- VF VR C2P C2N C1P C1N RAM External Clock Remark : 1. Value of the resistors depends on the LCD panel characteristic. 2. RES, CS, R/W and D/C should be at a known state. 3. CS line low at Standby Mode. MC141531 3–162 MOTOROLA Die Pad Coordinate of MC141531 Pad Pin Name X (um) Y(um) Bump Pad Size (um) Pin Name X (um) Y(um) Bump Pad Size (um) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 OSC2 AVSS VR VF VCC CC+ VLL6 VLL5 VLL4 OSC1 VLL3 VLL2 C1N C1P C2N C2P AVDD AVDD DVSS DVSS DVSS D7 DVSS D6 DVSS D5 DVSS D4 DVSS D3 DVSS D2 DVSS D1 DVSS D0 DVSS CS DVSS R/W DVSS D/C RES DVDD BP DVSS ANNUN2 DVSS ANNUN1 DVSS ANNUN0 DVSS SEG119 -3685 -3487 -3290 -3183 -2985 -2787 -2590 -2392 -2194 -1997 -1789 -1682 -1485 -1287 -1089 -891.6 -693.9 -496.2 -298.5 -99 18 124.8 241.8 348.6 465.6 572.4 689.4 796.2 913.2 1020 1137 1244 1361 1468 1585 1691 1808 1915 2032 2139 2256 2363 2480 2587 2794 2901 3018 3125 3242 3348 3465 3572 3689 4254 -762.9 -762.9 -762.9 -762.9 -762.9 -762.9 -762.9 -762.9 -762.9 -762.9 -762.9 -762.9 -763.2 -762.9 -762.9 -762.9 -762.9 -762.9 -762.9 -762.9 -762.9 -762.9 -762.9 -762.9 -762.9 -762.9 -762.9 -762.9 -762.9 -762.9 -762.9 -762.9 -762.9 -762.9 -762.9 -762.9 -762.9 -762.9 -762.9 -762.9 -762.9 -762.9 -762.9 -762.9 -762.9 -762.9 -762.9 -762.9 -762.9 -762.9 -762.9 -762.9 -762.9 -697.2 76x76 76x76 76x76 76x76 76x76 76x76 76x76 76x76 76x76 76x76 76x76 76x76 76x76 76x76 76x76 76x76 76x76 76x76 76x76 76x76 76x76 76x76 76x76 76x76 76x76 76x76 76x76 76x76 76x76 76x76 76x76 76x76 76x76 76x76 76x76 76x76 76x76 76x76 76x76 76x76 76x76 76x76 76x76 76x76 76x76 76x76 76x76 76x76 76x76 76x76 76x76 76x76 76x76 108x50 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 SEG102 SEG101 SEG100 SEG99 SEG98 SEG97 SEG96 SEG95 SEG94 SEG93 SEG92 SEG91 SEG90 SEG89 SEG88 SEG87 SEG86 SEG85 SEG84 SEG83 SEG82 SEG81 SEG80 SEG79 SEG78 SEG77 SEG76 SEG75 SEG74 SEG73 SEG72 SEG71 SEG70 SEG69 SEG68 SEG67 SEG66 SEG65 SEG64 SEG63 SEG62 SEG61 SEG60 SEG59 SEG58 SEG57 SEG56 SEG55 SEG54 SEG53 SEG52 SEG51 SEG50 SEG49 3925 3849 3773 3697 3620 3544 3468 3392 3316 3239 3163 3087 3011 2935 2858 2782 2706 2630 2554 2477 2401 2325 2249 2173 2096 2020 1944 1868 1792 1715 1639 1563 1487 1411 1334 1258 1182 1106 1030 953.4 877.2 801 724.8 648.6 572.4 496.2 420 343.8 267.6 191.4 115.2 39 -37.2 -113.4 631.5 631.5 631.5 631.5 631.5 631.5 631.5 631.5 631.5 631.5 631.5 631.5 631.5 631.5 631.5 631.5 631.5 631.5 631.5 631.5 631.5 631.5 631.5 631.5 631.5 631.5 631.5 631.5 631.5 631.5 631.5 631.5 631.5 631.5 631.5 631.5 631.5 631.5 631.5 631.5 631.5 631.5 631.5 631.5 631.5 631.5 631.5 631.5 631.5 631.5 631.5 631.5 631.5 631.5 50x108 50x108 50x108 50x108 50x108 50x108 50x108 50x108 50x108 50x108 50x108 50x108 50x108 50x108 50x108 50x108 50x108 50x108 50x108 50x108 50x108 50x108 50x108 50x108 50x108 50x108 50x108 50x108 50x108 50x108 50x108 50x108 50x108 50x108 50x108 50x108 50x108 50x108 50x108 50x108 50x108 50x108 50x108 50x108 50x108 50x108 50x108 50x108 50x108 50x108 50x108 50x108 50x108 50x108 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 SEG118 SEG117 SEG116 SEG115 SEG114 SEG113 SEG112 SEG111 SEG110 SEG109 SEG108 SEG107 SEG106 SEG105 SEG104 SEG103 4254 4254 4254 4254 4254 4254 4254 4254 4254 4254 4254 4306 4230 4154 4078 4001 -621 -544.8 -468.6 -392.4 -316.2 -240 -163.8 -87.6 -11.4 64.8 141 631.5 631.5 631.5 631.5 631.5 108x50 108x50 108x50 108x50 108x50 108x50 108x50 108x50 108x50 108x50 108x50 50x108 50x108 50x108 50x108 50x108 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 SEG48 SEG47 SEG46 SEG45 SEG44 SEG43 SEG42 SEG41 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 -189.6 -265.8 -342 -418.2 -494.4 -570.6 -646.8 -723 -799.2 -875.4 -951.6 -1028 -1104 -1180 -1256 -1333 631.5 631.5 631.5 631.5 631.5 631.5 631.5 631.5 631.5 631.5 631.5 631.5 631.5 631.5 631.5 631.5 50x108 50x108 50x108 50x108 50x108 50x108 50x108 50x108 50x108 50x108 50x108 50x108 50x108 50x108 50x108 50x108 MOTOROLA 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 Pin Name X (um) Y(um) SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 COM16 COM15 COM14 COM13 COM12 COM11 COM10 COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM0 COM16 -1409 -1485 -1561 -1637 -1714 -1790 -1866 -1942 -2018 -2095 -2171 -2247 -2323 -2399 -2476 -2552 -2628 -2704 -2780 -2857 -2933 -3009 -3085 -3161 -3238 -3314 -3390 -3466 -3542 -3619 -3695 -3771 -3847 -3930 -4006 -4082 -4159 -4235 -4311 -4254 -4254 -4254 -4254 -4254 -4254 -4254 -4254 -4254 -4254 -4254 -4254 631.5 631.5 631.5 631.5 631.5 631.5 631.5 631.5 631.5 631.5 631.5 631.5 631.5 631.5 631.5 631.5 631.5 631.5 631.5 631.5 631.5 631.5 631.5 631.5 631.5 631.5 631.5 631.5 631.5 631.5 631.5 631.5 631.5 631.5 631.5 631.5 631.5 631.5 631.5 140.1 63.9 -12.3 -88.5 -164.7 -240.9 -317.1 -393.3 -469.5 -545.7 -621.9 -698.1 Bump Size (um) 50x108 50x108 50x108 50x108 50x108 50x108 50x108 50x108 50x108 50x108 50x108 50x108 50x108 50x108 50x108 50x108 50x108 50x108 50x108 50x108 50x108 50x108 50x108 50x108 50x108 50x108 50x108 50x108 50x108 50x108 50x108 50x108 50x108 50x108 50x108 50x108 50x108 50x108 50x108 108x50 108x50 108x50 108x50 108x50 108x50 108x50 108x50 108x50 108x50 108x50 108x50 Die Size : 358.5 X 78 mil MC141531 3–163