General Description Features The MM82PC12 is a microCMOS 8-bit input/output port contained in a standard 24-pin dual-in-line package. The MM82PC12 can be used to implement latches, gated buffers, or multiplexers. Thus, all of the major peripheral and input/output functions of a microcomputer system can be implemented with this device. The MM82PC12 includes an 8-bit latch with TRI-STATEÉ output buffers, and device selection and control logic. Also included is a service request flip-flop for the generation and control of interrupts to the microprocessor. The MM82PC12 is pinout and function compatible with standard INS8212 and DP8212 devices. For military applications, the MM82PC12 is available with class B screening in accordance with method 5004 of MILSTD-883. Y Y Y Y Y Y Y Y Y Y July 1987 Drive capabilityÐ150 pF load High noise immunity Low power dissipation Full interface to CMOS logic levels microCMOS technology TTL drive capability when VCC e 5V 8-bit data latch and buffer Service request flip-flop for generation and control of interrupts 1 mA input load current Reduces system package count by replacing buffers, latches, and multiplexers in microcomputer systems System Configuration TL/C/5596 – 1 TRI-STATEÉ is a registered trademark of National Semiconductor Corp. C1995 National Semiconductor Corporation TL/C/5596 RRD-B30M105/Printed in U. S. A. MM82PC12 8-Bit Input/Output Port MM82PC12 8-Bit Input/Output Port Absolute Maximum Ratings Note: Absolute maximum ratings are those values beyond which the safety of the device cannot be guaranteed. Continuous operation at these limits is not intended; operation should be limited to those conditions specified under DC Electrical Characteristics. If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Storage Temperature Range Voltage at Any Pin With Respect to Ground b 65§ C to a 150§ C b 0.3V to VCC a 0.3V Lead Temperature (Soldering, 10 seconds) Operating Range VCC e 5V g 10% Ambient Temperature Military Industrial 300§ C 500 mW 7V Power Dissipation Maximum VCC b 55§ C to a 125§ C b 40§ C to a 85§ C 0§ C to a 70§ C Commercial DC Electrical Characteristics VCC e 5V g 10%, GND e 0V, unless otherwise specified Symbol Parameter Test Conditions Max Units 0.7 VCC Min Typ VCC V 0 0.2 VCC V 0.4 V VIH Input High Voltage VIL Input Low Voltage VOH Output High Voltage VCC e 4.5V, VIH e 4.5V, IOH e b2 mA VOL Output Low Voltage VCC e 5.5V, VIL e 0V, VIH e 5.5V, IOL e 2 mA IIH Input High Current VCC e 5.5V, VIN e 5.5V IIL Input Low Current VCC e 5.5V, VIN e 0V IOH Output High Current VCC e 4.5V, VOUT e 2.4V, VIH e 4.5V IOL Output Low Current VCC e 5.5V, VOUT e 0.4V, VIL e 0V ICC Power Supply Current VCC e 5.5V, VIH e 5.5V, VIL e 0V 400 mA IOZL TRI-STATE Low Leakage Current VCC e 5.5V, VOUT e 0V b 10 mA IOZH TRI-STATE High Leakage Current VCC e 4.5V, VOUT e 4.5V 10 mA 2.4 V 10 mA b 10 mA b 2.0 mA 2.0 mA AC Electrical Characteristics TA e b55§ C to a 125§ C, VCC e 5V g 10%, GND e 0V, unless otherwise specified Typ Max Units tPW Symbol Pulse Width (STB, DS1 # DS2, CLR) Parameter Test Conditions 25 40 ns tPD Data In to Data Out 45 60 ns tWE Write Enable to Data Out 55 75 ns tSET Data Setup Time 15 tH Data Hold Time 20 tR Reset to Data Out 50 65 ns tS Select to Interrupt 50 65 ns tC Clear to Data Out 45 60 ns tED Output Enable/Disable Time 50 65 ns 2 Min ns ns Timing Waveforms Read Timing TL/C/5596 – 2 Write Timing TL/C/5596 – 3 Data Setup, Hold Delay Timing TL/C/5596 – 4 Interrupt Timing TL/C/5596 – 5 Clear Timing TL/C/5596 – 6 3 Propagation Delays Pin Descriptions Figure 1 illustrates the calculations of a more useful propagation delay. The figure uses a 5V supply with a tolerance of g 10%, ambient temperature of a 25§ C, and a load capacitance of 100 pF. The AC Characteristics table depicts tPD, at 5V, 25§ C, equalling 25 ns. Use the graph in Figure 1 to get the degradation multiple for 150 pF. The number shown is 1.09. The adjusted propagation delay is, therefore 25 c 1.09 or 27 ns. The following describes the function of all the MM82PC12 input/output pins. Some of these descriptions reference internal circuits. INPUT SIGNALS Device Select (DS1, DS2: When DS1 is low and DS2 is high, the device is selected. The output buffers are enabled and the service request flip-flop is asynchronously reset (cleared) when the device is selected. Mode (MD): When MD is high (output mode), the output buffers are enabled and the source of the data latch clock input is the device selection logic (DS1 # DS2). When MD is low (input mode), the state of the output buffers is determined by the device selection logic (DS1 # DS2) and the source of the data latch clock input is the strobe (STB) input. Strobe (STB): STB is used as the data latch clock input when the mode (MD) input is low (input mode). STB is also used to synchronously set the service request flip-flop, which is negative edge triggered. Data In (DI1 –DI8): Data In is the 8-bit data input to the data latch, which consists of eight D-type flip-flops incorporating a level sensitive clock. While the data latch clock input is high, the Q output of each flip-flop follows the data input. When the clock input returns low, the data latch stores the data input. Clear (CLR) is only effective when the clock is low (latch in the latched state). Clear (CLR): When CLR is low, the data latch is reset (cleared) if the clock is also low. The clock input high overrides the clear (CLR) input data latch reset. CLR being low also resets the service request flip-flop. The service request flip-flop is in the non-interrupting state when reset. TL/C/5596–7 *Including jig and probe capacitance. Output Test Circuit for Propagation Delays TL/C/5596–8 OUTPUT SIGNALS Interrupt (INT): The interrupt pin goes low (interrupting state) when either the service request flip-flop is synchronously set by the strobe (STB) input or the device is selected. Data Out (DO1 –DO8): Data Out is the 8-bit data output of data buffers, which are TRI-STATE, non-inverting stages. These buffers have a common control line that either enables the buffers to transmit the data from the data latch outputs or disables the buffers by placing them in the highimpedance state. TL/C/5596–9 Reliability Information FIGURE 1. Normalized Typical Propagation Delay vs. Load Capacitance Gate Count 108 Transistor Count 248 4 Connection Diagrams Logic Diagram Dual-In-Line Package TL/C/5596–10 Top View Order Number MM82PC12J or N See NS Package Number J24A or N24A Plastic Chip Carrier TL/C/5596 – 11 TL/C/5596–12 Top View Order Number MM82PC12V See NS Package Number V28A Logic Table A Logic Table B STB MD DS1 # DS2 Data Out Equals 0 1 0 1 0 1 0 1 0 0 1 1 0 0 1 1 0 0 0 0 1 1 1 1 TRI-STATE TRI-STATE Data Latch Data Latch Data Latch Data In Data In Data In CLR DS1 # DS2 STB Q* INT 0 RESET 1 1 1 1 0 0 0 1 RESET 0 0 0 K 0 0 0 0 1 0 0 1 1 0 0 1 *Internal Service Request flip-flop. Note: CLR K resets data latch to the output low state. The data latch clock is level sensitive, a low level clock latches the data. 5 Applications in Microcomputer Systems TL/C/5596–13 Gated Buffer (TRI-STATE) TL/C/5596 – 14 Bidirectional Bus Driver TL/C/5596–15 Interrupting Input Port TL/C/5596 – 16 Interrupt Instruction Port TL/C/5596–17 Output Port (with Handshaking) 6 Ordering Information TL/C/5596 – 18 Note 1: Do not specify a temperature option; all parts are screened to military temperature. Physical Dimensions inches (millimeters) Ceramic Dual-In-Line Package (J) Order Number MM82PC12J NS Package J24A Molded Dual-In-Line Package (N) Order Number MM82PC12N NS Package N24A 7 MM82PC12 8-Bit Input/Output Port Physical Dimensions inches (millimeters) (Continued) Plastic Chip Carrier Package (V) Order Number MM82PC12V NS Package V28A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation 1111 West Bardin Road Arlington, TX 76017 Tel: 1(800) 272-9959 Fax: 1(800) 737-7018 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Europe Fax: (a49) 0-180-530 85 86 Email: cnjwge @ tevm2.nsc.com Deutsch Tel: (a49) 0-180-530 85 85 English Tel: (a49) 0-180-532 78 32 Fran3ais Tel: (a49) 0-180-532 93 58 Italiano Tel: (a49) 0-180-534 16 80 National Semiconductor Hong Kong Ltd. 13th Floor, Straight Block, Ocean Centre, 5 Canton Rd. Tsimshatsui, Kowloon Hong Kong Tel: (852) 2737-1600 Fax: (852) 2736-9960 National Semiconductor Japan Ltd. Tel: 81-043-299-2309 Fax: 81-043-299-2408 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.