MP8799 CMOS Very Low Power, 1 MSPS, 10-Bit Analog-to-Digital Converter with 8-Channel Mux FEATURES BENEFITS • • • • • • • • • • • • • • • • 10-Bit Resolution 8-Channel Mux Sampling Rates from <1 kHz to 1 MHz Very Low Power CMOS - 30 mW (typ) Power Down; Lower Consumption – 3 mW (typ) Input Range between GND and VDD No S/H Required for Analog Signals less than 100 kHz No S/H Required for CCD Signals less than 1 MHz Single Power Supply (4 to 6 Volts) Latch-Up Free High ESD Protection: 4000 Volts Minimum 3 V Version: MP87L99 Reduced Board Space (Small Package) Reduced External Parts, No Sample/Hold Needed Suitable for Battery & Power Critical Applications Designer can Adapt Input Range & Scaling APPLICATIONS • • • • µP/DSP Interface and Control Applications High Resolution Imaging – Scanners & Copiers Wireless Digital Communications Multiplexed Data Acquisition GENERAL DESCRIPTION Scaled reference resistor tap @ 1/4 R, 1/2 R and 3/4 R allows for customizing the transfer curve as well as providing a 1/2 span reference voltage. Digital outputs are CMOS and TTL compatible. The MP8799 is a flexible, easy to use, precision 10-bit Analog-to-Digital Converter with 8-channel mux that operates over a wide range of input and sampling conditions. The MP8799 can operate with pulsed “on demand” conversion operation or continuous “pipeline” operation for sampling rates up to 1 MHz. The elimination of the S/H requirements, very low power, and small package size offer the designer a low cost solution. No sample and hold is required for charge couple device applications up to 1 MHz, or multiplexed input applications when the signal source bandwidth is limited to 100 kHz. The input architecture of the MP8799 allows direct interface to any analog input range between AGND and AVDD (0 to 2 V, 1 to 4 V, 0 to 5 V, etc.). The user simply sets VREF(+) and VREF(–) to encompass the desired input range. The MP8799 uses a two-step flash technique. The first segment converts the 4 MSBs and consists of 15 autobalanced comparators, latches, an encoder, and buffer storage registers. The second segment converts the remaining 6 LSBs. When the power down input is “high”, the data outputs DB9 to DB0 hold the current values and VREF(–) is disconnected from VREF1(–). The power consumption during the power down mode is approximately 3mW. ORDERING INFORMATION Package Type Temperature Range Part No. DNL (LSB) INL (LSB) PQFP –40 to +85°C MP8799AE 1 2 Rev. 3.00 1 MP8799 SIMPLIFIED BLOCK AND TIMING DIAGRAM AVDD Coarse Comparators 4 Adder AVDD DVDD φS 5 φB VREF(+) R3 Fine Resolution Comparators R2 R1 VREF(–) CLK OFW DB9-DB0 DFF OE Ladder PD VREF1(–) CLK φS AIN1 1 or 8 MUX AIN8 CLR WR A2 A1 A0 Latch 8 3 to 8 Decoder AGND DGND PIN CONFIGURATIONS See Packaging Section for Package Dimensions 33 23 34 22 See the following page for pin numbers and descriptions Index 44 12 1 11 44-Pin PQFP (10mm x 10mm) QN44 Rev. 3.00 2 N DB9-DB0 N-1 N OFW N-1 N 10 6 φB MP8799 PIN OUT DEFINITIONS PIN NO. NAME DESCRIPTION PIN NO. NAME DESCRIPTION 1 DB6 Data Output Bit 6 23 R3 Reference Ladder Tap 2 DB7 Data Output Bit 7 24 N/C No Connect 3 DGND Digital Ground 25 AIN1 Analog Signal Input 1 4 DGND Digital Ground 26 AIN2 Analog Signal Input 2 5 DVDD Digital VDD 27 AIN3 Analog Signal Input 3 6 CLR Clear (Active Low) 28 AIN4 Analog Signal Input 4 7 WR Write (Active Low) 29 AIN5 Analog Signal Input 5 8 A2 Address 2 30 AGND Analog Ground 9 A1 Address 1 31 AVDD Analog VDD 10 A0 Address 0 32 AVDD Analog VDD 11 CLK Clock Input 33 AIN6 Analog Signal Input 6 12 OE Output Enable (Active Low) 34 AGND Analog Ground 13 N/C No Connect 35 PD Power Down 14 DB8 Data Output Bit 8 36 AIN7 Analog Signal Input 7 15 DB9 Data Output Bit 9 (MSB) 37 DB0 Data Output Bit 0 (LSB) 16 OFW Overflow Output 38 DB1 Data Output Bit 1 17 VREF(+) Upper Reference Voltage 39 DB2 Data Output Bit 2 18 VREF(–) Lower Reference Voltage 40 DB3 Data Output Bit 3 19 VREF1(–) Lower Reference Voltage 41 DB4 Data Output Bit 4 20 R1 Reference Ladder Tap 42 DB5 Data Output Bit 5 21 R2 Reference Ladder Tap 43 N/C No Connect 22 AIN8 Analog Signal Input 8 44 N/C No Connect TRUTH TABLE FOR INPUT CHANNEL SELECTION Selected Analog Input CLR WR A2 A1 A0 L X X X X AIN1 H L L L L AIN1 H L L L H AIN2 H L L H L AIN3 H L L H H AIN4 H L H L L AIN5 H L H L H AIN6 H L H H L AIN7 H L H H H AIN8 H H X X X Previous Selection Note: CLR, WR, A2, A1, A0 are internally connected to ground through 500kΩ resistance. Rev. 3.00 3 MP8799 ELECTRICAL CHARACTERISTICS TABLE Unless Otherwise Specified: AVDD = DVDD = 5 V, FS = 1 MHz (50% Duty Cycle), VREF(+) = 4.6, VREF(–) = AGND, TA = 25°C Parameter Symbol Min FS 10 .001 25°C Typ Max Units Test Conditions/Comments 1 Bits MHz For Rated Performance +1 2 LSB LSB KEY FEATURES Resolution Sampling Rate ACCURACY (A Grade)2 Differential Non-Linearity Integral Non-Linearity DNL INL Zero Scale Error Full Scale Error EZS EFS +0.50 –2.5 LSB LSB LSB Best Fit Line (Max INL – Min INL)/2 Reference from VREF(+) to VREF(–) REFERENCE VOLTAGES Positive Ref. Voltage Negative Ref. Voltage Differential Ref. Voltage5 Ladder Resistance Ladder Temp. Coefficient1 Ladder Switch Resistance1 Ladder Switch Off Leakage1 VREF(+) VREF(–) VREF RL RTCO AVDD AGND 0.5 525 IILKG-SW 675 2000 12 50 AVDD 900 V V V Ω ppm/°C Ω nA ANALOG INPUT1 Input Bandwidth Input Voltage Range7 Input Capacitance3 Aperture Delay 100 VIN CIN tAP VREF(–) VIH VIL IIN 2.0 45 kHz V pF ns 0.8 V V VREF(+) 60 35 DIGITAL INPUTS Logical “1” Voltage Logical “0” Voltage Leakage Currents CLK PD, OE (Internal Res to DGND) Input Capacitance Clock Timing (See Figure 1.)1 Clock Period Rise & Fall Time4 “High” Time6 “Low” Time6 +100 30 –5 5 TS tR, tF tB tS 1000 10 500,000 500,000 250 150 Rev. 3.00 4 µA µA pF ns ns ns ns VIN=DGND to DVDD MP8799 ELECTRICAL CHARACTERISTICS TABLE (CONT’D) 25°C Parameter Symbol Min Typ Max Units DIGITAL OUTPUTS Logical “1” Voltage Logical “0” Voltage Tristate Leakage Data Hold Time (See Figure 1.)1 Data Valid Delay1 Write Pulse Width1 Multiplexer Address Setup Time1 Multiplexer Address Hold Time1 Delay from WR to Multiplexer1 Enable Power Down Time1 Power Up Time1 Test Conditions/Comments COUT=15 pF VOH VOL IOZ tHLD tDL tWR tAS tAH DVDD-0.5 0 30 35 0.4 +5 35 45 40 80 0 tMUXEN1 tPD tPU V V µA ns ns ns ns ns 80 300 200 ns ns ns 1.2 6.5 10 mA V mA ILOAD = 2 mA ILOAD = 4 mA VOUT = 0 to DVDD POWER SUPPLIES8 Power Down (IDD) Operating Voltage (AVDD, DVDD) Current (AVDD + DVDD) IPD-DD VDD IDD 4 0.6 5 6 VIN = 2 V NOTES: Guaranteed. Not tested. Tester measures code transition voltages by dithering the voltage of the analog input (VIN). The difference between the measured code width and the ideal value (VREF/1024) is the DNL error (see Figure 4.). The INL error is the maximum distance (in LSBs) from the best fit line to any transition voltage (See Figure 7.). 3 See VIN input equivalent circuit (see Figure 9.). 4 Clock specification to meet aperture specification (tAP). Actual rise/fall time can be less stringent with no loss of accuracy. 5 Specified values guarantee functional device. Refer to other parameters for accuracy. 6 System can clock MP8799 with any duty cycle as long as all timing conditions are met. 7 Input range where input is converted correctly into binary code. Input voltage outside specified range converts to zero or full scale output. 8 DVDD and AVDD are connected through the silicon substrate. Connect together at the package. 1 2 Specifications are subject to change without notice ABSOLUTE MAXIMUM RATINGS (TA = +25°C unless otherwise noted)1, 2, 3 Storage Temperature . . . . . . . . . . . . . . . . . . . –65 to +150°C VDD (to GND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7 V VREF(+), VREF(–), VREF1(–) . . . . . . . GND –0.5 to VDD +0.5 V All AINs . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 to VDD +0.5 V All Inputs . . . . . . . . . . . . . . . . . . . . . GND –0.5 to VDD +0.5 V All Outputs . . . . . . . . . . . . . . . . . . . GND –0.5 to VDD +0.5 V Lead Temperature (Soldering 10 seconds) . . . . . . . +300°C Package Power Dissipation Rating to 75°C PQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450mW Derates above 75°C . . . . . . . . . . . . . . . . . . . . . 14mW/°C NOTES: 1 Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation at or above this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 2 Any input pin which can see a value outside the absolute maximum ratings should be protected by Schottky diode clamps (HP5082-2835) from input pin to the supplies. All inputs have protection diodes which will protect the device from short transients outside the supplies of less than 100mA for less than 100µs. 3 VDD refers to AVDD and DVDD. GND refers to AGND and DGND. Rev. 3.00 5 MP8799 tR tS when φS disconnects the latches from the comparators. This delay is called aperture delay (tAP). tF tB VIH CLOCK The coarse comparators make the first pass conversion and selects a ladder range for the fine comparators. The fine comparators are connected to the selected range during the next φB phase. VIL SAMPLE N–1 AUTO BALANCE SAMPLE N AUTO BALANCE SAMPLE N+1 φB φS TS ANALOG INPUT φS VIN Latch VOH VTAP DATA N-1 Ref Ladder VOL tDL COARSE COMPARATOR φB φS φS tHLD φB VIN Figure 1. MP8799 Timing Diagram Latch VTAP THEORY OF OPERATION Selected Range Analog-to-Digital Conversion Figure 2. MP8799 Comparators The MP8799 converts analog voltages into 1024 digital codes by encoding the outputs of 15 coarse and 67 fine comparators. Digital logic is used to generate the overflow bit. The conversion is synchronous with the clock and it is accomplished in 2 clock periods. AIN Sampling, Ladder Sampling, and Conversion Timing Figure 3. shows this relationship as a timing chart. AIN sampling, ladder sampling and output data relationships are shown for the general case where the levels which drive the ladder need to change for each sampled AIN time point. The ladder is referenced for both last AIN sample and next AIN sample at the same time. If the ladder’s levels change by more than 1 LSB, one of the samples must be discarded. Also note that the clock low period for the discarded AIN can be reduced to the minimum tS time of 150 ns. The reference resistance ladder is a series of 1025 resistors. The first and the last resistor of the ladder are half the value of the others so that the following relations apply: RREF = 1024 ∗ R FINE COMPARATOR φB VREF = VREF(+) – VREF(–) = 1024 ∗ LSB The clock signal generates the two internal phases, φB (CLK high) and φS (CLK low = sample) (See Figure 2.). The rising edge of the CLK input marks the end of the sampling phase (φS). Internal delay of the clock circuitry will delay the actual instant Hold Reference Value Past Clock Change for tAP Time Short Cycle Sample will be discarded tS External Settle by Clock Update Time Reference Stable Time – For Sample AIN2 Update References Reference Stable Time – For Sample AIN1 Clock Internal AIN Sample Window Ladder Sample Window (MSB Bank) Ladder Compare (LSB Bank) External DATA AINX1 Sample AIN1 S B AINX0 Sample AIN2 Not Used B Sample AIN1 S S B AINX1 Sample AIN2 Sample Ladder for AIN1 Sample Ladder for AINX1 Sample Ladder for AIN2 Sample Ladder for AINX2 Compare Ladder V/S AINX0 Compare Ladder V/S AIN1 Compare Ladder V/S AINX1 Compare Ladder V/S AIN2 DATA AIN0 DATA AINX0 DATA AIN1 Not Used Figure 3. AIN Sampling, Ladder Sampling & Conversion Timing Rev. 3.00 6 DATA AINX1 Not Used MP8799 Accuracy of Conversion: DNL and INL DNL LSB V(N+1) The transfer function for an ideal A/D converter is shown in Figure 4. Analog Input V(N) DIGITAL CODES 0.5 ∗ LSB N+1 Output Codes 0.5 ∗ LSB N N–1 OFW = 0 1 LSB (N+1) Code Width = V(N+1) – V(N) LSB = [ VREF(+) – VREF(–) ] / 1024 OFW = 1 3FF 3FE 001 000 002 DNL(N) = [ V(N+1) – V(N) ] – LSB 3FD LSB Figure 5. DNL Measurement On Production Tester V VREF(–) V001 V002 V3FE V3FF V0FW VREF(+) Figure 4. Ideal A/D Transfer Function The formulas for Differential Non-linearity (DNL), Integral Non-Linearity (INL) and zero and full scale errors (EZS, EFS) are: The overflow transition (VOFW) takes place at: DNL (001) = V002 – V001 – LSB VIN = VOFW = VREF(+) – 0.5 ∗ LSB : : : The first and the last transitions for the data bits take place at: DNL (3FE) = V3FF – V3FE – LSB VIN = V001 = VREF(–) + 0.5 ∗ LSB EFS (full scale error) = V3FF – [VREF(+) –1.5 ∗ LSB] VIN = V3FF = VREF(–) – 1.5 ∗ LSB EZS (zero scale error) = V001 – [VREF(–) + 0.5 ∗ LSB] LSB = VREF / 1024 = (V3FF – V001) / 1022 DIGITAL CODES 0.5 ∗ LSB Note that the overflow transition is a flag and has no impact on the data bits. In a “real” converter the code-to-code transitions don’t fall exactly every VREF/1024 volts. 1.5 ∗ LSB EZS EFS 3FF A positive DNL (Differential Non-Linearity) error means that the real width of a particular code is larger than 1 LSB. This error is measured in fractions of LSBs. 002 3FE 001 000 A Max DNL specification guarantees that ALL code widths (DNL errors) are within the stated value. A specification of Max DNL = + 0.5 LSB means that all code widths are within 0.5 and 1.5 LSB. If VREF = 4.608 V then 1 LSB = 4.5 mV and every code width is within 2.25 and 6.75 mV. VREF(–) V001 V002 V3FE V V3FF VREF(+) Figure 6. Real A/D Transfer Curve Figure 6. shows the zero scale and full scale error terms. Rev. 3.00 7 MP8799 Figure 7. gives a visual definition of the INL error. The chart shows a 3-bit converter transfer curve with greatly exaggerated DNL errors to show the deviation of the real transfer curve from the ideal one. A system will clock the MP8799 continuously or it will give clock pulses intermittently when a conversion is desired. The timing of Figure 8a shows normal operation, while the timing of Figure 8b keeps the MP8799 in balance and ready to sample the analog input. After a tester has measured all the transition voltages, the computer draws a line parallel to the ideal transfer line. By definition the best fit line makes equal the positive and the negative INL errors. For example, an INL error of –1 to +2 LSB’s relative to the Ideal Line would be +1.5 LSB’s relative to the best fit line. CLOCK N N+1 DATA N N+1 a. Continuous sampling Output Codes Best Fit Line 7 CLOCK N BALANCE Real Transfer Line 6 DATA 5 N b. Single sampling EFS INL 4 Figure 8. Relationship of Data to Clock Ideal Transfer Line 3 Analog Input 2 The MP8799 has very flexible input range characteristics. The user may set VREF(+) and VREF(–) to two fixed voltages and then vary the input DC and AC levels to match the VREF range. Another method is to first design the analog input circuitry and then adjust the reference voltages for the analog input range. One advantage is that this approach may eliminate the need for external gain and offset adjust circuitry which may be required by fixed input range A/Ds. LSB 1 Analog Input (Volt) EZS Figure 7. INL Error Calculation The MP8799’s performance is optimized by using analog input circuitry that is capable of driving the AIN input. Figure 9. shows the equivalent circuit for AIN. Clock and Conversion Timing 40 Ω AVDD R Series 40W AIN 15 pF φS R MUX 500W 4 1 pF 60 pF 87 pF 160 Ω φS 10 pF 8 Control 87 pF 300 Ω Channel Selection Figure 9. Analog Input Equivalent Circuit Rev. 3.00 8 φB + 4 pF 1/2 [ VREF(+) + VREF(–) ] MP8799 Analog Input Multiplexer Reference Voltages The input/output relationship is a function of VREF: The MP8799 includes a 8-Channel analog input multiplexer. The relationship between the clock, the multiplexer address, the WR and the output data is shown in Figure 10. AIN = VIN – VREF(–) VREF = VREF(+) – VREF(–) DATA = 1023 ∗ (AIN/VREF) A system can increase total gain by reducing VREF. Digital Interfaces Clock Sample N Old Address Sample M New Address tCLKS2 tWR Sample M+1 tCLKH2 The logic encodes the outputs of the comparators into a binary code and latches the data in a D-type flip-flop for output. tAH The functional equivalent of the MP8799 (Figure 12.) is composed of: WR tAS ÉÉ ÉÉÉÉÉÉÉÉÉÉ ÉÉ ÉÉÉÉÉÉÉÉÉÉ Delay stage (tAP) from the clock to the sampling phase (φS). An ideal analog switch which samples VIN. An ideal A/D which tracks and converts VIN with no delay. A series of two DFF’s with specified hold (tHLD) and delay (tDL) times. 1) Address DB0-DB9 N-2 Valid N-1 Valid Old Address N Valid Old Address 2) 3) M Valid New Address 4) tCLKS2 = tCLKH2 = 0 Figure 10. MUX Address Timing tAP, tHLD and tDL are specified in the Electrical Characteristics table. φS VIN tAS D Q D Q DB9-DB0 tAH tAP A2, A1, A0 WR A/D CLK MP8799 tWR CLK tMUXEN1 MUXEN (Internal Signal) N VIN N+1 tHLD tDL DB9-DB0 N-1 N Figure 11. Analog MUX Timing Figure 12. MP8799 Functional Equivalent Circuit and Interface Timing Rev. 3.00 9 MP8799 Power Down Figure 13. shows the relationship between the clock, sampled AIN to output data relationship and the effect of power down. CLK SAMPLE N SAMPLE M VIN DB0-DB9 N-2 Valid N-1 Valid N Valid tCLKS1 SAMPLE M+1 ÇÇÇÇÇÇ ÇÇÇÇÇÇ M Valid tCLKH1 PD tPD tPU IDD, IVREF(+) Figure 13. Power Down Timing Diagram Rev. 3.00 10 MP8799 APPLICATION NOTES C1 = 4.7 or 10µF Tantalum C2 = 0.1µF Chip Cap or low inductance cap RT = Clock Transmission Line Termination +5 V C1A, C2A AVDD 1 of 8 AIN C1D, C2D DVDD Z 100W Buffer Resistive Isolation of 50 to 100W AIN1 (Substrate) OFW AIN8 DB9 - DB0 OE MP8799 WR CLK Reference Voltage Source VREF(+) + C1 – C2 C1 CLK 3/4 R C2 C1 1/4 R C2 VREF(–) VREF1(–) AGND DGND RT A2 A1 A0 Figure 14. Typical Circuit Connections The following information will be useful in maximizing the performance of the MP8799. shield for parasitics and not a return path for signals. To reduce noise levels, use separate low impedance ground paths. DGND should not be shared with other digital circuitry. If separate low impedance paths cannot be provided, DGND should be connected to AGND next to the MP8799. 1. All signals should not exceed AVDD +0.5 V or AGND –0.5 V or DVDD +0.5 V or DGND –0.5 V. 2. Any input pin which can see a value outside the absolute maximum ratings (AVDD or DVDD+0.5 V or AGND –0.5 V) should be protected by diode clamps (HP5082-2835) from input pin to the supplies. All MP8799 inputs have input protection diodes which will protect the device from short transients outside the supply ranges. 7. DVDD should not be shared with other digital circuitry to avoid conversion errors caused by digital supply transients. DVDD for the MP8799 should be connected to AVDD next to the MP8799. 8. DVDD and AVDD are connected inside the MP8799 through the N – doped silicon substrate. Any DC voltage difference between DVDD and AVDD will cause undesirable internal currents. 3. The design of a PC board will affect the accuracy of MP8799. Use of wire wrap is not recommended. 4. The analog input signal (VIN) is quite sensitive and should be properly routed and terminated. It should be shielded from the clock and digital outputs so as to minimize cross coupling and noise pickup. 9. Each power supply and reference voltage pin should be decoupled with a ceramic (0.1µF) and a tantalum (10µF) capacitor as close to the device as possible. 10. The digital output should not drive long wires. The capacitive coupling and reflection will contribute noise to the conversion. When driving distant loads, buffers should be used. 100Ω resistors in series with the digital outputs in some applications reduces the digital output disruption of AIN. 5. The analog input should be driven by a low impedance (less than 50Ω). 6. Analog and digital ground planes should be substantial and common at one point only. The ground plane should act as a Rev. 3.00 11 MP8799 +5 V 5k 0.1µF + MP5010 100k + – – Figure 15. Example of a Reference Voltage Source +5 V 1 of 8 5 V R +5 V R VREF(+) AVDD + VIN DB0 AIN1 – AIN8 VREF(–) AGND For R = 5k use Beckman Instruments #694-3-R10k resistor array or equivalent. NOTE: High R values affect the input BW of ADC due to the (R ∗ CIN of ADC) time constant. Therefore, for different applications the R value needs to be selected as a tradeoff between AIN settling time and power dissipation. Figure 16. 5 V Analog Input +5 V 1 of 8 10 V 2R +5 V R VREF(+) AVDD + VIN DB0 AIN1 – 2R AIN8 VREF(–) AGND For R = 5k use Beckman Instruments #694-3-R10k resistor array or equivalent. NOTE: High R values affect the input BW of ADC due to the (R ∗ CIN of ADC) time constant. Therefore, for different applications the R value needs to be selected as a tradeoff between AIN settling time and power dissipation. Figure 17. 10 V Analog Input Rev. 3.00 12 MP8799 MP8799 MP7641 DAC0 AIN1 DAC7 AIN8 + – VIN + – VIN MP7226 DAC4 VREF(+) DAC3 3/4 DAC2 1/4 VREF(+) DAC1 VREF1(–) @ Power Down write values to DAC 3, 2, 1 = DAC 4 to minimize power consumption. Only AIN and Ladder detail shown. Figure 18. A/D Ladder and AIN with Programmed Control (of VREF(+), VREF(–), 1/4 and 3/4 TAP.) Rev. 3.00 13 MP8799 PERFORMANCE CHARACTERISTICS Graph 1. DNL vs. Sampling Frequency Graph 2. INL vs. Sampling Frequency Graph 3. Supply Current vs. Sampling Frequency Graph 4. Power Down Current vs. Sampling Frequency Graph 5. DNL vs. Reference Voltage Graph 6. DNL vs. Temperature Rev. 3.00 14 MP8799 Graph 7. Supply Current vs. Temperature Graph 8. Power Down Current vs. Temperature Graph 9. Reference Resistance vs. Temperature Rev. 3.00 15 MP8799 44 LEAD PLASTIC QUAD FLAT PACK (10mm X 10mm PQFP, METRIC) QN44 D D1 33 23 34 22 D1 D 44 12 1 11 B e A2 C A α A1 L MILLIMETERS SYMBOL A INCHES MIN MAX MIN MAX –– 2.45 –– 0.096 A1 0.25 –– 0.01 –– A2 1.9 2.1 0.100 0.108 B 0.3 0.4 0.012 0.018 C 0.13 0.23 0.005 0.009 D 12.95 13.45 0.510 0.530 9.9 10.1 0.392 0.396 D1 e 0.8 BSC 0.0315 BSC L 0.65 1.03 0.026 0.037 α 0° 7° 0° 7° Coplanarity = 4 mil max. Rev. 3.00 16 MP8799 Notes Rev. 3.00 17 MP8799 Notes Rev. 3.00 18 MP8799 Notes Rev. 3.00 19 MP8799 NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contains here in are only for illustration purposes and may vary depending upon a user’s specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 1993 EXAR Corporation Datasheet April 1995 Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited. Rev. 3.00 20