Freescale Semiconductor Technical Data 3.3 V 1:12 LVCMOS PLL Clock Generator The MPC9773 is a 3.3 V compatible, 1:12 PLL based clock generator targeted for high-performance low-skew clock distribution in mid-range to highperformance networking, computing, and telecom applications. With output frequencies up to 240 MHz and output skews less than 250 ps the device meets the needs of the most demanding clock applications. MPC9773 Rev 5, 08/2005 MPC9773 3.3 V 1:12 LVCMOS PLL CLOCK GENERATOR Features • • • • • • • • • • • • • • • 1:12 PLL based low-voltage clock generator 3.3 V power supply Internal power-on reset Generates clock signals up to 242.5 MHz Maximum output skew of 250 ps Differential PECL reference clock input Two LVCMOS PLL reference clock inputs External PLL feedback supports zero-delay capability Various feedback and output dividers (refer to Application Section) Supports up to three individual generated output clock frequencies Synchronous output clock stop circuitry for each individual output for power down support Drives up to 24 clock lines Ambient temperature range -40°C to +85°C Pin and function compatible to the MPC973 52-lead Pb-free package available FA SUFFIX 52-LEAD LQFP PACKAGE CASE 848D-03 AE SUFFIX 52-LEAD LQFP PACKAGE Pb-FREE PACKAGE CASE 848D-03 Functional Description The MPC9773 utilizes PLL technology to frequency lock its outputs onto an input reference clock. Normal operation of the MPC9773 requires the connection of the PLL feedback output QFB to feedback input FB_IN to close the PLL feedback path. The reference clock frequency and the divider for the feedback path determine the VCO frequency. Both must be selected to match the VCO frequency range. The MPC9773 features an extensive level of frequency programmability between the 12 outputs as well as the output to input relationships, for instance 1:1, 2:1, 3:1, 3:2, 4:1, 4:3, 5:1, 5:2, 5:3, 5:4, 5:6, 6:1, 8:1 and 8:3. The QSYNC output will indicate when the coincident rising edges of the above relationships will occur. The selectability of the feedback frequency is independent of the output frequencies. This allows for very flexible programming of the input reference versus output frequency relationship. The output frequencies can be either odd or even multiples of the input reference. In addition, the output frequency can be less than the input frequency for applications where a frequency needs to be reduced by a nonbinary factor. The MPC9773 also supports the 180° phase shift of one of its output banks with respect to the other output banks. The QSYNC outputs reflect the phase relationship between the QA and QC outputs and can be used for the generation of system baseline timing signals. The REF_SEL pin selects the LVPECL or the LVCMOS compatible inputs as the reference clock signal. Two alternative LVCMOS compatible clock inputs are provided for clock redundancy support. The PLL_EN control selects the PLL bypass configuration for test and diagnosis. In this configuration, the selected input reference clock is routed directly to the output dividers, bypassing the PLL. The PLL bypass is fully static and the minimum clock frequency specification and all other PLL characteristics do not apply. The outputs can be individually disabled (stopped in logic low state) by programming the serial CLOCK_STOP interface of the MPC9773. The MPC9773 has an internal power-on reset. The MPC9773 is fully 3.3 V compatible and requires no external loop filter components. All inputs (except PCLK) accept LVCMOS signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50 Ω transmission lines. For series terminated transmission lines, each of the MPC9773 outputs can drive one or two traces, giving the devices an effective fanout of 1:24. The device is pin and function compatible to the MPC973 and is packaged in a 52-lead LQFP package. © Freescale Semiconductor, Inc., 2005. All rights reserved. QA0 All input resistors have a value of 25 kΩ PCLK PCLK 1 VCC CCLK0 0 CCLK1 1 CCLK_SEL Bank A 0 Ref VCO ÷2 0 ÷1 1 PLL ÷4, ÷6, ÷8, ÷12 1 ÷4, ÷6, ÷8, ÷10 CLK Stop VCC QB0 SYNC PULSE CLK Stop QB1 QB2 QB3 VCO_SEL PLL_EN Bank C VCC QC0 CLK Stop 2 2 2 3 FSEL_A[0:1] FSEL_B[0:1] FSEL_C[0:1] FSEL_FB[0:2] 0 1 CLK Stop Power-On Reset CLK Stop Clock Stop QC1 QC2 QC3 QFB INV_CLK STOP_DATA STOP_CLK MR/OE QA2 Bank B FB VCC QA1 QA3 ÷2, ÷4, ÷6, ÷8 ÷4, ÷6, ÷8, ÷10 ÷12, ÷16, ÷20 200–485 MHz REF_SEL FB_IN 0 QSYNC 12 GND QB0 VCC QB1 GND QB2 VCC QB3 FB_IN GND QFB VCC FSEL_FB0 Figure 1. MPC9773 Logic Diagram FSEL_FB1 QSYNC GND QC0 VCC QC1 FSEL_C0 FSEL_C1 QC2 VCC QC3 GND INV_CLK VCC_PLL PCLK PCLK 39 38 37 36 35 34 33 32 31 30 29 28 27 26 40 25 41 24 42 23 43 22 44 21 45 MPC9773 20 46 19 47 18 48 17 49 16 50 15 51 14 52 1 2 3 4 5 6 7 8 9 10 11 12 13 GND MR/OE STOP_CLK STOP_DATA FSEL_FB2 PLL_EN REF_SEL CCLK_SEL CCLK0 CCLK1 FSEL_B1 FSEL_B0 FSEL_A1 FSEL_A0 QA3 VCC QA2 GND QA1 VCC QA0 GND VCO_SEL Figure 2. MPC9773 52-Lead Package Pinout (Top View) MPC9773 2 Advanced Clock Drivers Device Data Freescale Semiconductor Table 1. Pin Configuration Pin I/O Type Function CCLK0 Input LVCMOS PLL reference clock CCLK1 Input LVCMOS Alternative PLL reference clock PCLK, PCLK Input LVPECL Differential LVPECL reference clock FB_IN Input LVCMOS PLL feedback signal input, connect to an QFB CCLK_SEL Input LVCMOS LVCMOS clock reference select REF_SEL Input LVCMOS LVCMOS/PECL reference clock select VCO_SEL Input LVCMOS VCO operating frequency select PLL_EN Input LVCMOS PLL enable/PLL bypass mode select MR/OE Input LVCMOS Output enable/disable (high-impedance tristate) and device reset FSEL_A[0:1] Input LVCMOS Frequency divider select for bank A outputs FSEL_B[0:1] Input LVCMOS Frequency divider select for bank B outputs FSEL_C[0:1] Input LVCMOS Frequency divider select for bank C outputs FSEL_FB[0:2] Input LVCMOS Frequency divider select for the QFB output INV_CLK Input LVCMOS Clock phase selection for outputs QC2 and QC3 STOP_CLK Input LVCMOS Clock input for clock stop circuitry STOP_DATA Input LVCMOS Configuration data input for clock stop circuitry QA[0-3] Output LVCMOS Clock outputs (Bank A) QB[0-3] Output LVCMOS Clock outputs (Bank B) QC[0-3] Output LVCMOS Clock outputs (Bank C) QFB Output LVCMOS PLL feedback output. Connect to FB_IN. QSYNC Output LVCMOS Synchronization pulse output GND Supply Ground VCC_PLL Supply VCC PLL positive power supply (analog power supply). It is recommended to use an external RC filter for the analog power supply pin VCC_PLL. Please refer to applications section for details. VCC Supply VCC Positive power supply for I/O and core. All VCC pins must be connected to the positive power supply for correct operation Negative power supply Table 2. Function Table (Configuration Controls) Control Default 0 1 REF_SEL 1 Selects CCLKx as the PLL reference clock Selects the LVPECL inputs as the PLL reference clock CCLK_SEL 1 Selects CCLK0 Selects CCLK1 VCO_SEL 1 Selects VCO ÷ 2. The VCO frequency is scaled by a factor of 2 (low VCO frequency range). Selects VCO ÷ 1 (high VCO frequency range) PLL_EN 1 Test mode with the PLL bypassed. The reference clock is substituted for the Normal operation mode with PLL internal VCO output. MPC9773 is fully static and no minimum frequency limit enabled. applies. All PLL related AC characteristics are not applicable. INV_CLK 1 QC2 and QC3 are in phase with QC0 and QC1 MR/OE 1 Outputs disabled (high-impedance state) and device is reset. During reset/ Outputs enabled (active) output disable the PLL feedback loop is open and the internal VCO is tied to its lowest frequency. The MPC9773 requires reset after any loss of PLL lock. Loss of PLL lock may occur when the external feedback path is interrupted. The length of the reset pulse should be greater than one reference clock cycle (CCLKx). The device is reset by the internal power-on reset (POR) circuitry during power-up. QC2 and QC3 are inverted (180° phase shift) with respect to QC0 and QC1 VCO_SEL, FSEL_A[0:1], FSEL_B[0:1], FSEL_C[0:1], FSEL_FB[0:2] control the operating PLL frequency range and input/output frequency ratios. See Table 3 to Table 6 and the Applications Section for supported frequency ranges and output to input frequency ratios. MPC9773 Advanced Clock Drivers Device Data Freescale Semiconductor 3 Table 3. Output Divider Bank A (NA) VCO_SEL FSEL_A1 FSEL_A0 0 0 0 0 0 Table 5. Ouput Divider Bank C (NC) QA[0:3] VCO_SEL FSEL_C1 FSEL_C0 QC[0:3] 0 VCO ÷ 8 0 0 0 VCO ÷ 4 1 VCO ÷ 12 0 0 1 VCO ÷ 8 1 0 VCO ÷ 16 0 1 0 VCO ÷ 12 0 1 1 VCO ÷ 24 0 1 1 VCO ÷ 16 1 0 0 VCO ÷ 4 1 0 0 VCO ÷ 2 1 0 1 VCO ÷ 6 1 0 1 VCO ÷ 4 1 1 0 VCO ÷ 8 1 1 0 VCO ÷ 6 1 1 1 VCO ÷ 12 1 1 1 VCO ÷ 8 Table 4. Output Divider Bank B (NB) VCO_SEL FSEL_B1 FSEL_B0 QB[0:3] 0 0 0 VCO ÷ 8 0 0 1 VCO ÷ 12 0 1 0 VCO ÷ 16 0 1 1 VCO ÷ 20 1 0 0 VCO ÷ 4 1 0 1 VCO ÷ 6 1 1 0 VCO ÷ 8 1 1 1 VCO ÷ 10 Table 6. Output Divider PLL Feedback (M) VCO_SEL FSEL_FB2 FSEL_FB1 FSEL_FB0 QFB 0 0 0 0 VCO ÷ 8 0 0 0 1 VCO ÷ 12 0 0 1 0 VCO ÷ 16 0 0 1 1 VCO ÷ 20 0 1 0 0 VCO ÷ 16 0 1 0 1 VCO ÷ 24 0 1 1 0 VCO ÷ 32 0 1 1 1 VCO ÷ 40 1 0 0 0 VCO ÷ 4 1 0 0 1 VCO ÷ 6 1 0 1 0 VCO ÷ 8 1 0 1 1 VCO ÷ 10 1 1 0 0 VCO ÷ 8 1 1 0 1 VCO ÷ 12 1 1 1 0 VCO ÷ 16 1 1 1 1 VCO ÷ 20 MPC9773 4 Advanced Clock Drivers Device Data Freescale Semiconductor Table 7. General Specifications Symbol Characteristics Min Typ Max VCC ÷ 2 Unit Condition VTT Output Termination Voltage MM ESD Protection (Machine Model) 200 V V HBM ESD Protection (Human Body Model) 2000 V LU Latch-Up Immunity 200 mA CPD Power Dissipation Capacitance 12 pF Per output CIN Input Capacitance 4.0 pF Inputs Table 8. Absolute Maximum Ratings(1) Symbol Characteristics Min Max Unit VCC Supply Voltage –0.3 3.9 V VIN DC Input Voltage –0.3 VCC + 0.3 V DC Output Voltage –0.3 VCC + 0.3 V ±20 mA ±50 mA 125 °C VOUT IIN IOUT TS DC Input Current DC Output Current Storage Temperature –65 Condition 1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied. Table 9. DC Characteristics (VCC = 3.3 V ± 5%, TA = -40°C to 85°C) Symbol Characteristics Min Typ Max Unit Condition VCC_PLL PLL Supply Voltage 3.0 VCC V LVCMOS VIH Input High Voltage 2.0 VCC + 0.3 V LVCMOS VIL Input Low Voltage 0.8 V LVCMOS VPP Peak-to-Peak Input Voltage mV LVPECL V LVPECL V IOH = –24 mA(2) V V IOL = 24 mA IOL = 12 mA VCMR Common Mode Range(1) VOH Output High Voltage VOL Output Low Voltage ZOUT Output Impedance IIN ICC_PLL ICCQ Input Current PCLK, PCLK 250 PCLK, PCLK 1.0 VCC – 0.6 2.4 0.55 0.30 Maximum PLL Supply Current Maximum Quiescent Supply Current Ω 14 – 17 (3) 8.0 ±200 µA VIN = VCC or GND 13.5 mA VCC_PLL Pin 35 mA All VCC Pins 1. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP (DC) specification. 2. The MPC9773 is capable of driving 50 Ω transmission lines on the incident edge. Each output drives one 50 Ω parallel terminated transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50 Ω series terminated transmission lines. 3. Inputs have pull-down resistors affecting the input current. MPC9773 Advanced Clock Drivers Device Data Freescale Semiconductor 5 Table 10. AC Characteristics (VCC = 3.3 V ± 5%, TA = -40°C to 85°C)(1), (2) Symbol fREF Characteristics Min ÷ 4 feedback ÷ 6 feedback ÷ 8 feedback ÷ 10 feedback ÷ 12 feedback ÷ 16 feedback ÷ 20 feedback ÷ 24 feedback ÷ 32 feedback ÷ 40 feedback Input Reference Frequency Typ Max Unit 121.2 80.8 60.6 48.5 40.4 30.3 24.2 20.2 15.1 12.1 MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz 250 MHz 200 485 MHz 100.0 50.0 33.3 25.0 20.0 16.6 12.5 10.0 8.33 242.5 121.2 80.8 60.6 48.5 40.4 30.3 24.2 20.2 MHz MHz MHz MHz MHz MHz MHz MHz MHz 20 MHz 50.0 33.3 25.0 20.0 16.6 12.5 10.0 8.33 6.25 5.00 Input Reference Frequency in PLL Bypass Mode fVCO VCO Frequency Range fMAX Output Frequency fSTOP_CLK VPP VCMR tPW,MIN tR, tF t(∅) tSK(O) ÷ 2 output ÷ 4 output ÷ 6 output ÷ 8 output ÷ 10 output ÷ 12 output ÷ 16 output ÷ 20 output ÷ 24 output Serial Interface Clock Frequency Peak-to-Peak Input Voltage Common Mode Range(3) Input Reference Pulse mV LVPECL PCLK, PCLK 1.2 VCC – 0.9 V LVPECL 2.0 Propagation Delay (static phase 6.25 MHz < fREF < 65.0 MHz 65.0 MHz < fREF < 125 MHz fREF = 50 MHz and feedback = ÷8 ns 1.0 ns +3 +4 +166 ° ° ps 100 100 100 250 ps ps ps ps (T÷2) +200 ps 1.0 ns within QA outputs within QB outputs within QC outputs all outputs Output Duty Cycle(8) (T÷2) –200 tR, tF Output Rise/Fall Time 0.1 tPLZ, HZ Output Disable Time 8.0 ns tPZL, LZ Output Enable Time 8.0 ns 150 ps 100 ps 11 86 13 88 16 19 21 22 27 30 ps ps ps ps ps ps ps ps ps ps Jitter(9) Period Jitter(10) tJIT(∅) I/O Phase Jitter RMS (1 σ)(11) ÷ 4 feedback ÷ 6 feedback ÷ 8 feedback ÷ 10 feedback ÷ 12 feedback ÷ 16 feedback ÷ 20 feedback ÷ 24 feedback ÷ 32 feedback ÷ 40 feedback 0.8 to 2.0 V PLL locked –3 –4 –166 DC Cycle-to-cycle PLL locked 1000 offset)(6) tJIT(CC) PLL bypass 400 CCLKx Input Rise/Fall Time(5) tJIT(PER) PLL locked PCLK, PCLK Width(4) Output-to-Output Skew(7) Condition T÷2 0.55 to 2.4 V (VCO = 400 MHz) MPC9773 6 Advanced Clock Drivers Device Data Freescale Semiconductor Table 10. AC Characteristics (VCC = 3.3 V ± 5%, TA = -40°C to 85°C)(1), (2) Symbol Characteristics Bandwidth(12) BW PLL Closed Loop tLOCK Maximum PLL Lock Time Min ÷ 4 feedback ÷ 6 feedback ÷ 8 feedback ÷ 10 feedback ÷ 12 feedback ÷ 16 feedback ÷ 20 feedback ÷ 24 feedback ÷ 32 feedback ÷ 40 feedback Typ Max 1.20 – 3.50 0.70 – 2.50 0.50 – 1.80 0.45 – 1.20 0.30 – 1.00 0.25 – 0.70 0.20 – 0.55 0.17 – 0.40 0.12 – 0.30 0.11 – 0.28 Unit Condition MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz 10 ms 1. AC characteristics apply for parallel output termination of 50 Ω to VTT. 2. The input reference frequency must match the VCO lock range divided by the feedback divider ratio: fREF = fVCO ÷ (M ⋅ VCO_SEL). 3. VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP (AC) specification. Violation of VCMR or VPP impacts static phase offset t(∅). 4. Calculation of reference duty cycle limits: DCREF,MIN = tPW,MIN ⋅ fREF ⋅ 100% and DCREF,MAX = 100% – DCREF,MIN. 5. The MPC9773 will operate with input rise/fall times up to 3.0 ns, but the AC characteristics, specifically t(∅), tPW,MIN, DC and fMAX can only be guaranteed if tR, tF are within the specified range. 6. CCLKx or PCLK to FB_IN. Static phase offset depends on the reference frequency. t(∅) [s] = t(∅) [°] ÷ (fREF ⋅ 360°). 7. Excluding QSYNC output. Refer to APPLICATIONS INFORMATION for part-to-part skew calculation. 8. Output duty cycle is DC = (0.5 ± 200 ps ⋅ fOUT) ⋅ 100%. E.g., the DC range at fOUT = 100 MHz is 48% < DC < 52%. T = output period. 9. Cycle jitter is valid for all outputs in the same divider configuration. 10. Period jitter is valid for all outputs in the same divider configuration. 11. I/O jitter is valid for a VCO frequency of 400 MHz. Refer to APPLICATIONS INFORMATION for I/O jitter vs. VCO frequency. 12. –3 dB point of PLL transfer characteristics. MPC9773 Advanced Clock Drivers Device Data Freescale Semiconductor 7 APPLICATIONS INFORMATION MPC9773 Configurations Configuring the MPC9773 amounts to properly configuring the internal dividers to produce the desired output frequencies. The output frequency can be represented by this formula: fOUT = fREF ⋅ M ÷ N fREF ÷VCO_SEL PLL the specified frequency range. This divider is controlled by the VCO_SEL pin. VCO_SEL effectively extends the usable input frequency range while it has no effect on the output to reference frequency ratio. The output frequency for each bank can be derived from the VCO frequency and output divider: fQA[0:3] = fVCO ÷ (VCO_SEL ⋅ NA) fQB[0:3] = fVCO ÷ (VCO_SEL ⋅ NB) fQC[0:3] = fVCO ÷ (VCO_SEL ⋅ NC) fOUT ÷N Table 11. MPC9773 Divider ÷M where fREF is the reference frequency of the selected input clock source (CCLKO, CCLK1 or PCLK), M is the PLL feedback divider and N is an output divider. The PLL feedback divider is configured by the FSEL_FB[2:0] and the output dividers are individually configured for each output bank by the FSEL_A[1:0], FSEL_B[1:0] and FSEL_C[1:0] inputs. The reference frequency fREF and the selection of the feedback-divider M is limited by the specified VCO frequency range. fREF and M must be configured to match the VCO frequency range of 200 to 480 MHz in order to achieve stable PLL operation: fVCO,MIN ≤ (fREF ⋅ VCO_SEL ⋅ M) ≤ fVCO,MAX The PLL post-divider VCO_SEL is either a divide-by-one or a divide-by-two and can be used to situate the VCO into CCLK0 CCLK1 CCLK_SEL QA[3:0] 33.3 MHz 1 VCO_SEL FB_IN QB[3:0] 100 MHz QC[3:0] 200 MHz fREF = 33.3 MHz 11 00 00 101 FSEL_A[1:0] FSEL_B[1:0] FSEL_C[1:0] FSEL_FB[2:0] QFB Divider Function VCO_SEL Values M PLL Feedback FSEL_FB[0:3] ÷1 4, 6, 8, 10, 12, 16 ÷2 8, 12, 16, 20, 24, 32, 40 Bank A Output Divider FSEL_A[0:1] ÷1 4, 6, 8, 12 ÷2 8, 12, 16, 24 Bank B Output Divider FSEL_B[0:1] ÷1 4, 6, 8, 10 ÷2 8, 12, 16, 20 Bank C Output Divider FSEL_C[0:1] ÷1 2, 4, 6, 8 ÷2 4, 8, 12, 16 NA NB NC Table 11 shows the various PLL feedback and output dividers, and Figure 3 and Figure 4 display example configurations for the MPC9773. CCLK0 CCLK1 CCLK_SEL fREF = 25 MHz 1 VCO_SEL FB_IN 00 00 00 011 FSEL_A[1:0] FSEL_B[1:0] FSEL_C[1:0] FSEL_FB[2:0] QA[3:0] 62.5 MHz QB[3:0] 62.5 MHz QC[3:0] 125 MHz QFB MPC9773 MPC9773 33.3 MHz (Feedback) 25 MHz (Feedback) MPC9773 example configuration (feedback of QFB = 33.3 MHz, fVCO = 400 MHz, VCO_SEL = ÷1, M = 12, NA = 12, NB = 4, NC = 2). MPC9773 example configuration (feedback of QFB = 25 MHz, fVCO = 250 MHz, VCO_SEL = ÷1, M = 10, NA = 4, NB = 4, NC = 2). Frequency Range Min Max Frequency Range Min Max Input 16.6 MHz 40 MHz Input 20 MHz 48 MHz QA outputs 16.6 MHz 40 MHz QA outputs 50 MHz 120 MHz QB outputs 50 MHz 120 MHz QB outputs 50 MHz 120 MHz QC outputs 100 MHz 240 MHz QC outputs 100 MHz 240 MHz Figure 3. Example Configuration Figure 4. Example Configuration MPC9773 8 Advanced Clock Drivers Device Data Freescale Semiconductor MPC9773 Individual Output Disable (Clock Stop) Circuitry The individual clock stop (output enable) control of the MPC9773 allows designers, under software control, to implement power management into the clock distribution design. A simple serial interface and a clock stop control logic provides a mechanism through which the MPC9773 clock outputs can be individually stopped in the logic ‘0’ state: The clock stop mechanism allows serial loading of a 12-bit serial input register. This register contains one programmable clock stop bit for 12 of the 14 output clocks. The QC0 and QFB outputs cannot be stopped (disabled) with the serial port. The user can program an output clock to stop (disable) by writing logic ‘0’ to the respective stop enable bit. Likewise, the user may programmably enable an output clock by writing logic ‘1’ to the respective enable bit. The clock stop logic enables or disables clock outputs during the time when the output would normally be in logic low state, eliminating the possibility of short or ‘runt’ clock pulses. The user can write to the serial input register through the STOP_DATA input by supplying a logic ‘0’ start bit followed serially by 12 NRZ disable/enable bits. The period of each STOP_DATA bit equals the period of the free-running STOP_CLK signal. The STOP_DATA serial transmission should be timed so the MPC9773 can sample each STOP_DATA bit with the rising edge of the free-running STOP_CLK signal. (See Figure 5.) STOP_CLK STOP_DATA START QA0 QA1 QA2 QA3 QB0 QB1 QB2 QB3 QC1 QC2 QC3 QSYNC Figure 5. Clock Stop Circuit Programing MPC9773 Advanced Clock Drivers Device Data Freescale Semiconductor 9 SYNC Output Description The MPC9773 has a system synchronization pulse output QSYNC. In configurations for which the output frequency relationships are not integer multiples of each other, QSYNC provides a signal for system synchronization purposes. The MPC9773 monitors the relationship between the A bank and the B bank of outputs. The QSYNC output is asserted (logic low) one period in duration and one period prior to the coincident rising edges of the QA and QC outputs. The duration and the placement of the pulse is dependent on QA and QC output frequencies: the QSYNC pulse width is equal to the period of the higher of the QA and QC output frequencies. Figure 6 shows various waveforms for the QSYNC output. The QSYNC output is defined for all possible combinations of the bank A and bank C outputs. fVCO 1:1 Mode QA QC QSYNC 2:1 Mode QA QC QSYNC 3:1 Mode QC(÷2) QA(÷6) QSYNC 3:2 Mode QA(÷4) QC(÷6) QSYNC 4:1 Mode QC(÷2) QA(÷8) QSYNC 4:3 Mode QA(÷6) QC(÷8) QSYNC 6:1 Mode QA(÷12) QC(÷2) QSYNC Figure 6. QSYNC Timing Diagram MPC9773 10 Advanced Clock Drivers Device Data Freescale Semiconductor Power Supply Filtering The MPC9773 is a mixed analog/digital product. Its analog circuitry is naturally susceptible to random noise, especially if this noise is seen on the power supply pins. Random noise on the VCC_PLL power supply impacts the device characteristics, for instance I/O jitter. The MPC9773 provides separate power supplies for the output buffers (VCC) and the phase-locked loop (VCC_PLL) of the device. The purpose of this design technique is to isolate the high switching noise digital outputs from the relatively sensitive internal analog phase-locked loop. In a digital system environment where it is more difficult to minimize noise on the power supplies, a second level of isolation may be required. The simple but effective form of isolation is a power supply filter on the VCCA_PLL pin for the MPC9773. Figure 7 illustrates a typical power supply filter scheme. The MPC9773 frequency and phase stability is most susceptible to noise with spectral content in the 100-kHz to 20-MHz range. Therefore, the filter should be designed to target this range. The key parameter that needs to be met in the final filter design is the DC voltage drop across the series filter resistor RF. From the data sheet the ICC_PLL current (the current sourced through the VCC_PLL pin) is typically 8 mA (13.5 mA maximum), assuming that a minimum of 3.0 V must be maintained on the VCC_PLL pin. The resistor RF shown in Figure 7 must have a resistance of 5–10 Ω to meet the voltage drop criteria. RF = 5–10 Ω VCC CF = 22 µF RF Using the MPC9773 in Zero-Delay Applications Nested clock trees are typical applications for the MPC9773. Designs using the MPC9773 as an LVCMOS PLL fanout buffer with zero insertion delay will show significantly lower clock skew than clock distributions developed from CMOS fanout buffers. The external feedback option of the MPC9773 clock driver allows for its use as a zero delay buffer. The PLL aligns the feedback clock output edge with the clock input reference edge, resulting in a near zero delay through the device (the propagation delay through the device is virtually eliminated). The maximum insertion delay of the device in zero-delay applications is measured between the reference clock input and any output. This effective delay consists of the static phase offset, I/O jitter (phase or longterm jitter), feedback path delay and the output-to-output skew error relative to the feedback output. Calculation of Part-to-Part Skew The MPC9773 zero delay buffer supports applications where critical clock signal timing can be maintained across several devices. If the reference clock inputs of two or more MPC9773 are connected together, the maximum overall timing uncertainty from the common CCLKx input to any output is: tSK(PP) = t(∅) + tSK(O) + tPD, LINE(FB) + tJIT(∅) ∗ CF This maximum timing uncertainty consists of 4 components: static phase offset, output skew, feedback board trace delay, and I/O (phase) jitter: VCC_PLL CF 10 nF MPC9773 CCLKCommon tPD,LINE(FB) –t(∅) VCC 33...100 nF Figure 7. VCC_PLL Power Supply Filter The minimum values for RF and the filter capacitor CF are defined by the required filter characteristics: the RC filter should provide an attenuation greater than 40 dB for noise whose spectral content is above 100 kHz. In the example RC filter shown in Figure 7, the filter cut-off frequency is around 4.5 kHz and the noise attenuation at 100 kHz is better than 42 dB. As the noise frequency crosses the series resonant point of an individual capacitor, its overall impedance begins to look inductive and thus increases with increasing frequency. The parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the bandwidth of the PLL. Although the MPC9773 has several design features to minimize the susceptibility to power supply noise (isolated power and grounds and fully differential PLL), there still may be applications in which overall performance is being degraded due to system power supply noise. The power supply filter schemes discussed in this section should be adequate to eliminate power supply noise related problems in most designs. QFBDevice 1 tJIT(∅) Any QDevice 1 +tSK(O) +t(∅) QFBDevice2 Any QDevice 2 Max. skew tJIT(∅) +tSK(O) tSK(PP) Figure 8. MPC9773 Maximum Device-to-Device Skew MPC9773 Advanced Clock Drivers Device Data Freescale Semiconductor 11 Due to the statistical nature of I/O jitter, an RMS value (1 σ) is specified. I/O jitter numbers for other confidence factors (CF) can be derived from Table 12. Maximum I/O Phase Jitter versus Frequency Parameter: PLL Feedback Divider FB 120 Table 12. Confidence Factor CF 0.68268948 ± 2σ 0.95449988 ± 3σ 0.99730007 ± 4σ 0.99993663 ± 5σ 0.99999943 ± 6σ 0.99999999 tjit[φ] [ps] RMS ± 1σ 100 250 300 350 400 450 480 FB = ÷32 FB = ÷16 FB = ÷8 FB =÷4 450 Maximum I/O Phase Jitter versus Frequency Parameter: PLL Feedback Divider FB 140 120 FB = ÷10 100 80 FB = ÷40 60 40 20 0 200 FB = ÷20 250 300 350 400 450 480 VCO frequency [MHz] Figure 11. MPC9773 I/O Jitter Driving Transmission Lines The MPC9773 clock driver was designed to drive high speed signals in a terminated transmission line environment. To provide the optimum flexibility to the user, the output drivers were designed to exhibit the lowest impedance possible. With an output impedance of less than 20 Ω, the drivers can drive either parallel or series terminated transmission lines. For more information on transmission lines the reader is referred to Freescale Semiconductor application note AN1091. In most high-performance clock networks point-to-point distribution of signals is the method of choice. In a point-to-point scheme, either series terminated or parallel terminated transmission lines can be used. The parallel technique terminates the signal at the end of the line with a 50-Ω resistance to VCC ÷ 2. Maximum I/O Phase Jitter versus Frequency Parameter: PLL Feedback Divider FB tjit[φ] [ps] RMS FB = ÷12 20 Figure 10. MPC9773 I/O Jitter tSK(PP) = [–455ps...455ps] + tPD, LINE(FB) 300 350 400 VCO frequency [MHz] 40 VCO frequency [MHz] tSK(PP) = [–166ps...166ps] + [–250ps...250ps] + [(13ps ⋅ –3)...(13ps ⋅ 3)] + tPD, LINE(FB) 250 FB = ÷24 60 200 The feedback trace delay is determined by the board layout and can be used to fine-tune the effective delay through each device. Due to the frequency dependence of the static phase offset and I/O jitter, using Figure 9 to Figure 11 to predict a maximum I/O jitter and the specified t(∅) parameter relative to the input reference frequency results in a precise timing performance analysis. In the following example calculation an I/O jitter confidence factor of 99.7% (± 3σ) is assumed, resulting in a worst-case timing uncertainty from the common input reference clock to any output of –455 ps to +455 ps relative to CCLK (PLL feedback = ÷8, reference frequency = 50 MHz, VCO frequency = 400 MHz, I/O jitter = 13 ps RMS max., static phase offset t(∅) = ± 166 ps): 160 140 120 100 80 60 40 20 0 200 FB = ÷6 80 0 tjit[φ] [ps] RMS CF Probability of Clock Edge within the Distribution 480 Figure 9. MPC9773 I/O Jitter MPC9773 12 Advanced Clock Drivers Device Data Freescale Semiconductor This technique draws a fairly high level of DC current and thus only a single terminated line can be driven by each output of the MPC9773 clock driver. For the series terminated case, however, there is no DC current draw; thus the outputs can drive multiple series terminated lines. Figure 12 illustrates an output driving a single series terminated line versus two series terminated lines in parallel. When taken to its extreme the fanout of the MPC9773 clock driver is effectively doubled due to its capability to drive multiple lines. MPC9773 Output Buffer 14 Ω 3.0 2.5 OutA tD = 3.8956 OutB tD = 3.9386 2.0 RS = 36 Ω ZO = 50 Ω OutA Voltage (V) In At the load end the voltage will double, due to the near unity reflection coefficient, to 2.6 V. It will then increment towards the quiescent 3.0 V in steps separated by one round trip delay (in this case 4.0 ns). 1. Final skew data pending specification. In 1.5 1.0 MPC9773 Output Buffer In RS = 36 Ω ZO = 50 Ω RS = 36 Ω ZO = 50 Ω OutB0 14 Ω 0.5 0 OutB1 2 4 6 8 Time (ns) 10 12 14 Figure 13. Single versus Dual Waveforms Figure 12. Single versus Dual Transmission Lines The waveform plots in Figure 13 show the simulation results of an output driving a single line versus two lines. In both cases the drive capability of the MPC9773 output buffer is more than sufficient to drive 50-Ω transmission lines on the incident edge. Note from the delay measurements in the simulations that a delta of only 43 ps exists between the two differently loaded outputs. This suggests that the dual line driving need not be used exclusively to maintain the tight output-to-output skew of the MPC9773. The output waveform in Figure 13 shows a step in the waveform. This step is caused by the impedance mismatch seen looking into the driver. The parallel combination of the 36-Ω series resistor plus the output impedance does not match the parallel combination of the line impedances. The voltage wave launched down the two lines will equal: VL = Z0 = RS = R0 = VL = = VS (Z0 ÷ (RS + R0 + Z0)) 50 Ω || 50 Ω 36 Ω || 36 Ω 14 Ω 3.0 (25 ÷ (18+17+25) 1.31 V Since this step is well above the threshold region it will not cause any false clock triggering; however, designers may be uncomfortable with unwanted reflections on the line. To better match the impedances when driving multiple lines, the situation in Figure 14 should be used. In this case the series terminating resistors are reduced such that when the parallel combination is added to the output buffer impedance, the line impedance is perfectly matched. MPC9773 Output Buffer RS = 22 Ω ZO = 50 Ω RS = 22 Ω ZO = 50 Ω 14 Ω 14 Ω + 22 Ω || 22 Ω = 50 Ω || 50 Ω 25 Ω = 25 Ω Figure 14. Optimized Dual Line Termination MPC9773 Advanced Clock Drivers Device Data Freescale Semiconductor 13 MPC9773 DUT Pulse Generator Z = 50 Ω ZO = 50 Ω ZO = 50 Ω RT = 50 Ω RT = 50 Ω VTT VTT Figure 15. CCLK MPC9773 AC Test Reference Differential Pulse Generator Z = 50 Ω ZO = 50 Ω MPC9773 DUT ZO = 50 Ω RT = 50 Ω VTT RT = 50 Ω VTT Figure 16. PCLK MPC9773 AC Test Reference MPC9773 14 Advanced Clock Drivers Device Data Freescale Semiconductor VCC VCC ÷ 2 GND VCC VCC ÷ 2 GND tSK(O) VCC VCC ÷ 2 CCLKx GND VCC VCC ÷ 2 FB_IN GND The pin-to-pin skew is defined as the worst case difference in propagation delay between any similar delay path within a single device Figure 17. Output-to-Output Skew tSK(O) VCC VCC ÷ 2 t(∅) Figure 18. Propagation Delay (t(∅), Static Phase Offset) Test Reference CCLKx GND tP FB_IN T0 DC = tP/T0 x 100% TJIT(∅) = |T0-T1mean| The time from the PLL controlled edge to the non controlled edge, divided by the time between PLL controlled edges, expressed as a percentage The deviation in t0 for a controlled edge with respect to a t0 mean in a random sample of cycles Figure 19. Output Duty Cycle (DC) TN TN+1 Figure 20. I/O Jitter TJIT(CC) = |TN–TN+1| The variation in cycle time of a signal between adjacent cycles, over a random sample of adjacent cycle pairs TJIT(PER) = |TN–1/f0| T0 The deviation in cycle time of a signal with respect to the ideal period over a random sample of cycles Figure 21. Cycle-to-Cycle Jitter Figure 22. Period Jitter VCC = 3.3 V 2.4 0.55 tF tR Figure 23. Output Transition Time Test Reference MPC9773 Advanced Clock Drivers Device Data Freescale Semiconductor 15 PACKAGE DIMENSIONS CASE 848D-03 ISSUE F 52-LEAD LQFP PACKAGE PAGE 1 OF 3 MPC9773 16 Advanced Clock Drivers Device Data Freescale Semiconductor PACKAGE DIMENSIONS CASE 848D-03 ISSUE F 52-LEAD LQFP PACKAGE PAGE 2 OF 3 MPC9773 Advanced Clock Drivers Device Data Freescale Semiconductor 17 PACKAGE DIMENSIONS CASE 848D-03 ISSUE F 52-LEAD LQFP PACKAGE PAGE 3 OF 3 MPC9773 18 Advanced Clock Drivers Device Data Freescale Semiconductor How to Reach Us: Home Page: www.freescale.com E-mail: [email protected] USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. 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