MOTOROLA MPC9352

Freescale Semiconductor, Inc.
SEMICONDUCTOR TECHNICAL DATA
The MPC9352 is a 3.3V or 2.5V compatible, 1:11 PLL based clock
generator targeted for high performance clock tree applications. With
output frequencies up to 200 MHz and output skews lower than 200 ps
the device meets the needs of most demanding clock applications.
Freescale Semiconductor, Inc...
Features
• Configurable 11 outputs LVCMOS PLL clock generator
• Fully integrated PLL
• Wide range of output clock frequency of 16.67 MHz to 200 MHz
• Multiplication of the input reference clock frequency by 3, 2, 1, 3B2,
•
•
•
•
Order Number: MPC9352/D
Rev 3, 06/2003
LOW VOLTAGE
3.3V/2.5V LVCMOS 1:11
CLOCK GENERATOR
2B3, 1B3 and 1B2
2.5V and 3.3V LVCMOS compatible
Maximum output skew of 200 ps
Supports zero–delay applications
Designed for high–performance telecom, networking and computing
applications
• 32 lead LQFP package
• Ambient Temperature Range –40°C to +85°C
FA SUFFIX
Functional Description
32 LEAD LQFP PACKAGE
The MPC9352 is a fully 3.3V or 2.5V compatible PLL clock generator
CASE 873A
and clock driver. The device has the capability to generate output clock
signals of 16.67 to 200 MHz from external clock sources. The internal PLL
optimized for its frequency range and does not require external look filter
components. One output of the MPC9352 has to be connected to the PLL
feedback input FB_IN to close the external PLL feedback path. The
output divider of this output setting determines the PLL frequency
multiplication factor. This multiplication factor, F_RANGE and the
reference clock frequency must be selected to situate the VCO in its
specified lock range. The frequency of the clock outputs can be
configured individually for all three output banks by the FSELx pins
supporting systems with different but phase-aligned clock frequencies.
The PLL of the MPC9352 minimizes the propagation delay and therefore supports zero-delay applications. All inputs and
outputs are LVCMOS compatible. The outputs are optimized to drive parallel terminated 50Ω transmission lines. Alternatively,
each output can drive up to two series terminated transmission lines giving the device an effective fanout of 22.
The device also supports output high-impedance disable and a PLL bypass mode for static system test and diagnosis. The
MPC9352 is package in a 32 ld LQFP.
 Motorola, Inc. 2003
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MPC9352
1
÷6
1
0
÷4
0
$.
PLL
+(5 ÷2
1
0
÷2
+(5 1
+(5 1
0
6+-- !(1* #$"!"&#" /+7$ + 7+-*$ &. 5W8
Figure 1. MPC9352 Logic Diagram
MPC9352
Freescale Semiconductor, Inc...
0
!" #$%&''$()$) & *"$ +( $,$#(+- .!-$# .&# /$ +(+-&0 1&2$# "*11-3 1!( 4 -$+"$ "$$ +11-!%+!&( "$%!&( .&# )$+!-"4
Figure 2. MPC9352 32–Lead Package Pinout (Top View)
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TIMING SOLUTIONS
Freescale Semiconductor, Inc.
MPC9352
Table 1: PIN CONFIGURATION
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Pin
I/O
Type
Function
CCLK
Input
LVCMOS
PLL reference clock signal
FB_IN
Input
LVCMOS
PLL feedback signal input, connect to an output
F_RANGE
Input
LVCMOS
PLL frequency range select
FSELA
Input
LVCMOS
Frequency divider select for bank A outputs
FSELB
Input
LVCMOS
Frequency divider select for bank B outputs
FSELC
Input
LVCMOS
Frequency divider select for bank C outputs
PLL_EN
Input
LVCMOS
PLL enable/disable
MR/OE
Input
LVCMOS
Output enable/disable (high–impedance tristate) and device reset
QA0–4, QB0–3, QC0–1
Output
LVCMOS
Clock outputs
GND
Supply
Ground
Negative power supply
VCCA
Supply
VCC
PLL positive power supply (analog power supply). It is recommended to use an
external RC filter for the analog power supply pin VCCA. Please see
applications section for details.
VCC
Supply
VCC
Positive power supply for I/O and core
Table 2: FUNCTION TABLE
Control
Default
0
1
F_RANGE, FSELA, FSELB, and FSELC control the operating PLL frequency range and input/output frequency ratios.
See Table 1 and Table 2 for supported frequency ranges and output to input frequency ratios.
F_RANGE
0
VCO ÷ 1 (High input frequency range)
VCO ÷ 2 (Low input frequency range)
FSELA
0
Output divider ÷ 4
Output divider ÷ 6
FSELB
0
Output divider ÷ 4
Output divider ÷ 2
FSELC
0
Output divider ÷ 2
Output divider ÷ 4
MR/OE
0
Outputs enabled (active)
Outputs disabled (high–impedance state) and
reset of the device. During reset, the PLL
feedback loop is open and the VCO is operating
at its lowest frequency. The MPC9352 requires
reset at power–up and after any loss of PLL
lock. Loss of PLL lock may occur when the
external feedback path is interrupted. The length
of the reset pulse should be greater than two
reference clock cycles (CCLK).
PLL_EN
0
Normal operation mode with PLL enabled.
Test mode with PLL disabled. CCLK is
substituted for the internal VCO output.
MPC9352 is fully static and no minimum
frequency limit applies. All PLL related AC
characteristics are not applicable.
TIMING SOLUTIONS
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MPC9352
Table 3: GENERAL SPECIFICATIONS
Symbol
Characteristics
Min
Typ
Max
Unit
VCC B 2
VTT
Output Termination Voltage
MM
ESD Protection (Machine Model)
200
HBM
Condition
V
V
ESD Protection (Human Body Model)
2000
V
LU
Latch–Up Immunity
200
mA
CPD
Power Dissipation Capacitance
10
pF
Per output
CIN
Input Capacitance
4.0
pF
Inputs
Table 4: ABSOLUTE MAXIMUM RATINGSa
Freescale Semiconductor, Inc...
Symbol
Characteristics
Min
Max
Unit
VCC
Supply Voltage
-0.3
3.6
V
VIN
DC Input Voltage
-0.3
VCC+0.3
V
DC Output Voltage
-0.3
VCC+0.3
V
±20
mA
±50
mA
125
°C
VOUT
IIN
IOUT
TS
DC Input Current
DC Output Current
Storage Temperature
-65
Condition
a. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions
or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not
implied.
Table 5: DC CHARACTERISTICS (VCC = 3.3V ± 5%, TA = –40° to 85°C)
Symbol
Input high voltage
VIL
Input low voltage
VOH
Output High Voltage
VOL
Output Low Voltage
ZOUT
Output impedance
IIN
a
b
c
Characteristics
VIH
Min
Typ
2.0
Max
Unit
VCC + 0.3
V
LVCMOS
0.8
V
LVCMOS
V
IOH=-24 mAa
0.55
0.30
V
V
IOL= 24 mA
IOL= 12 mA
±200
µA
VIN=VCC or VIN=GND
5.0
mA
VCCA Pin
1.0
mA
All VCC Pins
2.4
W
14 - 17
Input Currentb
ICCA
Maximum PLL Supply Current
3.0
ICCQc
Maximum Quiescent Supply Current
Condition
The MPC9352 is capable of driving 50Ω transmission lines on the incident edge. Each output drives one 50Ω parallel terminated
transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50Ω series terminated transmission lines.
Inputs have pull-down resistors affecting the input current.
ICCQ is the DC current consumption of the device with all outputs open in high impedance state and the inputs in its default state or open.
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Freescale Semiconductor, Inc.
MPC9352
Table 6: AC CHARACTERISTICS (VCC = 3.3V ± 5%, TA = –40° to 85°C)a
Symbol
fref
Characteristics
Input reference frequency in PLL modeb
Min
÷4 feedback
÷6 feedback
÷8 feedback
÷12 feedback
Typ
Max
Unit
100.0
66.6
50.0
33.3
MHz
MHz
MHz
MHz
250.0
MHz
200
400
MHz
100
50
33.3
25
16.67
200
100
66.6
50
33.3
MHz
MHz
MHz
MHz
MHz
50.0
33.3
25.0
16.67
Freescale Semiconductor, Inc...
Input reference frequency in PLL bypass modec
fVCO
VCO lock frequency
fMAX
Output Frequency
frefDC
Reference Input Duty Cycle
tr, tf
CCLK Input Rise/Fall Time
t(∅)
Propagation Delay CCLK to FB_IN
(static phase offset)
tsk(O)
÷2 outpute
÷4 output
÷6 output
÷8 output
÷12 output
Output-to-output Skewf
25
fref > 40 MHz
fref < 40 MHz
-50
-200
all outputs, any frequency
within QA output bank
within QB output bank
within QC output bank
DC
Output duty cycle
47
tr, tf
Output Rise/Fall Time
0.1
tPLZ, HZ
tPZL, LZ
tJIT(CC)
Cycle-to-cycle jitter
tJIT(PER)
tJIT(∅)
BW
tLOCK
a
b
c
d
e
f
g
h
ranged
75
%
1.0
ns
0.8 to 2.0V
+150
+150
ps
ps
PLL locked
200
200
100
100
ps
ps
ps
ps
53
%
1.0
ns
Output Disable Time
8
ns
Output Enable Time
10
ns
output frequencies mixed
outputs are in any ÷4 and ÷6 combination
all outputs same frequency
400
250
100
ps
ps
ps
output frequencies mixed
outputs are in any ÷4 and ÷6 combination
all outputs same frequency
200
150
75
ps
ps
ps
Period Jitter
I/O Phase Jitter
÷4 feedback divider RMS (1 σ)g
÷6 feedback divider RMS (1 σ)
÷8 feedback divider RMS (1 σ)
÷12 feedback divider RMS (1 σ)
PLL closed loop bandwidthh
÷4 feedback
÷6 feedback
÷8 feedback
÷12 feedback
50
15
20
18 - 20
25
ps
ps
ps
ps
3.0 - 10.0
1.5 - 6.0
1.0 - 3.5
0.5 - 2.0
MHz
MHz
MHz
MHz
Maximum PLL Lock Time
Condition
10
0.55 to 2.4V
ms
AC characteristics apply for parallel output termination of 50Ω to VTT.
PLL mode requires PLL_EN=0 to enable the PLL and zero-delay operation. It is not recommended to use a ÷2 divider for feedback.
In PLL bypass mode, the MPC9352 divides the input reference clock.
The input frequency fref on CCLK must match the VCO frequency range divided by the feedback divider ratio FB: fref = fVCO ÷ FB.
See Table 9 and Table 10 for output divider configurations.
See application section for part-to-part skew calculation.
See application section for a jitter calculation for other confidence factors than 1 s.
-3 dB point of PLL transfer characteristics.
TIMING SOLUTIONS
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Freescale Semiconductor, Inc.
MPC9352
Table 7: DC CHARACTERISTICS (VCC = 2.5V ± 5%, TA = –40° to 85°C)
Symbol
Max
Unit
VIH
Input high voltage
1.7
VCC + 0.3
V
LVCMOS
VIL
Input low voltage
-0.3
0.7
V
LVCMOS
VOH
Output High Voltage
1.8
V
IOH=-15 mAa
VOL
Output Low Voltage
V
IOL= 15 mA
ZOUT
Output impedance
IIN
ICCA
ICCQb
a
Min
Typ
0.6
W
17 - 20
Input Current
Maximum PLL Supply Current
2.0
Maximum Quiescent Supply Current
Condition
±200
µA
VIN=VCC or GND
5.0
mA
VCCA Pin
1.0
mA
All VCC Pins
The MPC9352 is capable of driving 50Ω transmission lines on the incident edge. Each output drives one 50Ω parallel terminated
transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50Ω series terminated transmission lines per
output.
ICCQ is the DC current consumption of the device with all outputs open in high impedance state and the inputs in its default state or open.
Freescale Semiconductor, Inc...
b
Characteristics
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TIMING SOLUTIONS
Freescale Semiconductor, Inc.
MPC9352
Table 8: AC CHARACTERISTICS (VCC = 2.5V ± 5%, TA = –40° to 85°C)a
Symbol
fref
Characteristics
Input reference frequency in PLL modeb
Min
÷4 feedback
÷6 feedback
÷8 feedback
÷12 feedback
Typ
Max
Unit
100.0
66.6
50.0
33.3
MHz
MHz
MHz
MHz
250.0
MHz
200
400
MHz
100
50
33.3
25
16.67
200
100
66.6
50
33.3
MHz
MHz
MHz
MHz
MHz
50.0
33.3
25.0
16.67
Freescale Semiconductor, Inc...
Input reference frequency in PLL bypass modec
fVCO
VCO lock frequency
fMAX
Output Frequency
frefDC
Reference Input Duty Cycle
tr, tf
CCLK Input Rise/Fall Time
t(∅)
Propagation Delay CCLK to FB_IN
(static phase offset)
tsk(O)
÷2 outpute
÷4 output
÷6 output
÷8 output
÷12 output
Output-to-output Skewf
25
fref > 40 MHz
fref < 40 MHz
-50
-200
all outputs, any frequency
within QA output bank
within QB output bank
within QC output bank
DC
Output duty cycle
47
tr, tf
Output Rise/Fall Time
0.1
tPLZ, HZ
tPZL, ZH
tJIT(CC)
Cycle-to-cycle jitter
tJIT(PER)
tJIT(∅)
BW
tLOCK
a
b
c
d
e
f
g
h
ranged
75
%
1.0
ns
0.8 to 2.0V
+150
+150
ps
ps
PLL locked
200
200
100
100
ps
ps
ps
ps
53
%
1.0
ns
Output Disable Time
8
ns
Output Enable Time
10
ns
output frequencies mixed
outputs are in any ÷4 and ÷6 combination
all outputs same frequency
400
250
100
ps
ps
ps
output frequencies mixed
outputs are in any ÷4 and ÷6 combination
all outputs same frequency
200
150
75
ps
ps
ps
Period Jitter
I/O Phase Jitter
50
÷4 feedback divider RMS (1 σ)g
÷6 feedback divider RMS (1 σ)
÷8 feedback divider RMS (1 σ)
÷12 feedback divider RMS (1 σ)
15
20
18 - 20
25
ps
ps
ps
ps
÷4 feedback
÷6 feedback
÷8 feedback
÷12 feedback
1.0 - 8.0
0.7 - 3.0
0.5 - 2.5
0.4 - 1.0
MHz
MHz
MHz
MHz
PLL closed loop bandwidthh
Maximum PLL Lock Time
Condition
10
0.6 to 1.8V
ms
AC characteristics apply for parallel output termination of 50Ω to VTT.
PLL mode requires PLL_EN=0 to enable the PLL and zero-delay operation. It is not recommended to use a ÷2 divider for feedback.
In PLL bypass mode, the MPC9352 divides the input reference clock.
The input frequency fref on CCLK must match the VCO frequency range divided by the feedback divider ratio FB: fref = fVCO ÷ FB.
See Table 9 and Table 10 for output divider configurations.
See application section for part-to-part skew calculation.
See application section for a jitter calculation for other confidence factors than 1 s.
-3 dB point of PLL transfer characteristics.
TIMING SOLUTIONS
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MPC9352
APPLICATIONS INFORMATION
Programming the MPC9352
The MPC9352 supports output clock frequencies from
16.67 to 200 MHz. Different feedback and output divider
configurations can be used to achieve the desired input to
output frequency relationship. The feedback frequency and
divider should be used to situate the VCO in the frequency
lock range between 200 and 400 MHz for stable and optimal
operation. The FSELA, FSELB, FSELC pins select the
desired output clock frequencies. Possible frequency ratios
of the reference clock input to the outputs are 1:1, 1:2, 1:3, 3:2
as well as 2:3, 3:1 and 2:1. Table 1 illustrates the various
output configurations and frequency ratios supported by the
MPC9352. See also Table 9, Table 10 and Figure 3 to Figure
6 for further reference. A ÷2 output divider cannot be used for
feedback.
Table 9: MPC9352 Example Configuration (F_RANGE = 0)
PLL Feedback
Freescale Semiconductor, Inc...
VCO ÷
4b
VCO ÷ 6c
a.
b.
c.
frefa [MHz]
FSELA
FSELB
FSELC
50-100
0
0
0
fref
(50-100 MHz)
fref
(50-100 MHz)
fref ⋅ 2 (100-200 MHz)
0
0
1
fref
(50-100 MHz)
fref
(50-100 MHz)
fref
1
0
0
fref ⋅ 2÷3 (33-66 MHz)
fref
(50-100 MHz)
fref ⋅ 2 (100-200 MHz)
1
0
1
fref ⋅ 2÷3 (33-66 MHz)
fref
(50-100 MHz)
fref
1
0
0
fref
(33-66 MHz)
fref ⋅3÷2 (50-100 MHz)
fref ⋅ 3 (100-200 MHz)
1
0
1
fref
(33-66 MHz)
fref ⋅3÷2 (50-100 MHz)
fref ⋅3÷2 (50-100 MHz)
1
1
0
fref
(33-66 MHz)
fref ⋅ 3 (100-200 MHz)
fref ⋅ 3 (100-200 MHz)
1
1
1
fref
(33-66 MHz)
fref ⋅ 3 (100-200 MHz)
fref ⋅3÷2 (50-100 MHz)
33.3-66.67
QA[0:4]:fref ratio
QB[0:3]:fref ratio
QC[0:1]:fref ratio
(50-100 MHz)
(50-100 MHz)
fref is the input clock reference frequency (CCLK)
QAx connected to FB_IN and FSELA=0
QAx connected to FB_IN and FSELA=1
Table 10: MPC9352 Example Configurations (F_RANGE = 1)
PLL Feedback
VCO ÷
8b
VCO ÷ 12c
a.
b.
c.
frefa [MHz]
FSELA
FSELB
FSELC
25-50
0
0
0
fref
(25-50 MHz)
fref
(25-50 MHz)
fref ⋅ 2 (50-100 MHz)
0
0
1
fref
(25-50 MHz)
fref
(25-50 MHz)
fref
1
0
0
fref ⋅2÷3 (16-33 MHz)
fref
(25-50 MHz)
fref ⋅ 2 (50-100 MHz)
1
0
1
fref ⋅2÷3 (16-33 MHz)
fref
(25-50 MHz)
fref
1
0
0
fref
(16-33 MHz)
fref ⋅3÷2 (25-50 MHz)
fref ⋅ 3 (50-100 MHz)
1
0
1
fref
(16-33 MHz)
fref ⋅3÷2 (25-50 MHz)
fref ⋅3÷2 (25-50 MHz)
1
1
0
fref
(16-33 MHz)
fref ⋅ 3 (50-100 MHz)
fref ⋅ 3 (50-100 MHz)
1
1
1
fref
(16-33 MHz)
fref ⋅ 3 (50-100 MHz)
fref ⋅3÷2 (25-50 MHz)
16.67-33.3
QA[0:4]:fref ratio
QB[0:3]:fref ratio
QC[0:1]:fref ratio
(25-50 MHz)
(25-50 MHz)
fref is the input clock reference frequency (CCLK)
QAx connected to FB_IN and FSELA=0
QAx connected to FB_IN and FSELA=1
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MPC9352
Example Configurations for the MPC9352
Figure 3. MPC9352 Default Configuration
.#$. 9 :;
:;
:;
:;
Freescale Semiconductor, Inc...
MPC9352
Figure 4. MPC9352 Zero Delay Buffer Configuration
.#$. 9 4 :;
4 :;
4 :;
4 :;
MPC9352
:; 6$$)<+%58
4 :; 6$$)<+%58
MPC9352 default configuration (feedback of QB0 = 100 MHz).
All control pins are left open.
MPC9352 zero–delay (feedback of QB0 = 62.5 MHz). All
control pins are left open except FSELC = 1. All outputs
are locked in frequency and phase to the input clock.
Frequency range
Min
Max
Frequency range
Min
Max
Input
50 MHz
100 MHz
Input
50 MHz
100 MHz
QA outputs
50 MHz
10 MHz
QA outputs
50 MHz
10 MHz
QB outputs
50 MHz
100 MHz
QB outputs
50 MHz
100 MHz
QC outputs
100 MHz
200 MHz
QC outputs
50 MHz
100 MHz
Figure 5. MPC9352 Default Configuration
:;
:;
.#$. 9 4 :;
MPC9352
Figure 6. MPC9352 Zero Delay Buffer Config. 2
4 :;
4 :;
4 :;
.#$. 9 4 :;
4 :;
MPC9352
4 :; 6$$)<+%58
4 :; 6$$)<+%58
MPC9352 configuration to multiply the reference frequency
by 3, 3÷2 and 1. PLL feedback of QA4 = 33.3 MHz.
MPC9352 zero–delay (feedback of QB0 = 33.3 MHz).
Equivalent to Table 2 except F_RANGE = 1 enabling a
lower input and output clock frequency.
Frequency range
Min
Max
Frequency range
Min
Max
Input
25 MHz
50 MHz
Input
25 MHz
50 MHz
50 MHz
QA outputs
50 MHz
10 MHz
QA outputs
25 MHz
QB outputs
50 MHz
100 MHz
QB outputs
25 MHz
50 MHz
QC outputs
100 MHz
200 MHz
QC outputs
25 MHz
50 MHz
TIMING SOLUTIONS
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MPC9352
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Power Supply Filtering
supply noise. The power supply filter schemes discussed in
this section should be adequate to eliminate power supply
noise related problems in most designs.
The MPC9352 is a mixed analog/digital product. Its analog
circuitry is naturally susceptible to random noise, especially if
this noise is seen on the power supply pins. Random noise
on the VCCA (PLL) power supply impacts the device
characteristics, for instance I/O jitter. The MPC9352 provides
separate power supplies for the output buffers (VCC) and the
phase-locked loop (VCCA) of the device. The purpose of this
design technique is to isolate the high switching noise digital
outputs from the relatively sensitive internal analog
phase-locked loop. In a digital system environment where it is
more difficult to minimize noise on the power supplies a
second level of isolation may be required. The simple but
effective form of isolation is a power supply filter on the VCCA
pin for the MPC9352. Figure 7. illustrates a typical power
supply filter scheme. The MPC9352 frequency and phase
stability is most susceptible to noise with spectral content in
the 100kHz to 20MHz range. Therefore the filter should be
designed to target this range. The key parameter that needs
to be met in the final filter design is the DC voltage drop
across the series filter resistor RF. From the data sheet the
ICCA current (the current sourced through the VCCA pin) is
typically 3 mA (5 mA maximum), assuming that a minimum of
2.325V (VCC=3.3V or VCC=2.5V) must be maintained on the
VCCA pin. The resistor RF shown in Figure 7. “VCCA Power
Supply Filter” should have a resistance of 5–15W (VCC=3.3V)
or 9-10W (VCC=2.5V) to meet the voltage drop criteria.
9 =Ω .&# 9 4
9 =
Ω .&# 9 4
Nested clock trees are typical applications for the
MPC9352. Designs using the MPC9352 as LVCMOS PLL
fanout buffer with zero insertion delay will show significantly
lower clock skew than clock distributions developed from
CMOS fanout buffers. The external feedback option of the
MPC9352 clock driver allows for its use as a zero delay
buffer. One example configuration is to use a ÷4 output as a
feedback to the PLL and configuring all other outputs to a
divide-by-4 mode. The propagation delay through the device
is virtually eliminated. The PLL aligns the feedback clock
output edge with the clock input reference edge resulting a
near zero delay through the device. The maximum insertion
delay of the device in zero-delay applications is measured
between the reference clock input and any output. This
effective delay consists of the static phase offset, I/O jitter
(phase or long-term jitter), feedback path delay and the
output-to-output skew error relative to the feedback output.
Calculation of part-to-part skew
The MPC9352 zero delay buffer supports applications
where critical clock signal timing can be maintained across
several devices. If the reference clock inputs of two or more
MPC9352 are connected together, the maximum overall
timing uncertainty from the common CCLK input to any
output is:
9 µ .&# 9 4
9 µ .&# 9 4
Using the MPC9352 in zero–delay applications
tSK(PP) = t( ∅) + tSK(O) + tPD, LINE(FB) + tJIT( ∅) CF
This maximum timing uncertainty consist of 4
components: static phase offset, output skew, feedback
board trace delay and I/O (phase) jitter:
(
MPC9352
&''&(
444
(
$7!%$ Figure 7. VCCA Power Supply Filter
The minimum values for RF and the filter capacitor CF are
defined by the required filter characteristics: the RC filter
should provide an attenuation greater than 40 dB for noise
whose spectral content is above 100 kHz. In the example RC
filter shown in Figure 7. “VCCA Power Supply Filter”, the filter
cut-off frequency is around 3-5 kHz and the noise attenuation
at 100 kHz is better than 42 dB.
?@6∅8
(3 $7!%$ At68
A6∅8
$7!%$
As the noise frequency crosses the series resonant point
of an individual capacitor its overall impedance begins to look
inductive and thus increases with increasing frequency. The
parallel capacitor combination shown ensures that a low
impedance path to ground exists for frequencies well above
the bandwidth of the PLL. Although the MPC9352 has
several design features to minimize the susceptibility to
power supply noise (isolated power and grounds and fully
differential PLL) there still may be applications in which
overall performance is being degraded due to system power
MOTOROLA
>68
B6∅8
(3 $7!%$ +,4 "5$2
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68
Figure 8. MPC9352 max. device-to-device skew
Due to the statistical nature of I/O jitter a RMS value (1 s) is
specified. I/O jitter numbers for other confidence factors (CF)
can be derived from Table 11.
10
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This technique draws a fairly high level of DC current and
thus only a single terminated line can be driven by each
output of the MPC9352 clock driver. For the series terminated
case however there is no DC current draw, thus the outputs
can drive multiple series terminated lines. Figure 10. “Single
versus Dual Transmission Lines” illustrates an output driving
a single series terminated line versus two series terminated
lines in parallel. When taken to its extreme the fanout of the
MPC9352 clock driver is effectively doubled due to its
capability to drive multiple lines.
Table 11: Confidence Facter CF
CF
Probability of clock edge within the distribution
± 1s
0.68268948
± 2s
0.95449988
± 3s
0.99730007
± 4s
0.99993663
± 5s
0.99999943
± 6s
0.99999999
Freescale Semiconductor, Inc...
The feedback trace delay is determined by the board
layout and can be used to fine-tune the effective delay
through each device. In the following example calculation a
I/O jitter confidence factor of 99.7% (± 3s) is assumed,
resulting in a worst case timing uncertainty from input to any
output of -445 ps to 395 ps relative to CCLK:
tSK(PP) =
[–200ps...150ps] + [–200ps...200ps] +
[(15ps @ –3)...(15ps @ 3)] + tPD, LINE(FB)
tSK(PP) =
[–445ps...395ps] + tPD, LINE(FB)
MPC9352
C@C@
C
Ω
C@C@
C
Due to the frequency dependence of the I/O jitter,
Figure 9. “Max. I/O Jitter versus frequency” can be used for a
more precise timing performance analysis.
9 Ω
D 9 Ω
9 Ω
D 9 Ω
9 Ω
D 9 Ω
*
*
Ω
*
Figure 10. Single versus Dual Transmission Lines
The waveform plots in Figure 11. “Single versus Dual
Line Termination Waveforms” show the simulation results of
an output driving a single line versus two lines. In both cases
the drive capability of the MPC9352 output buffer is more
than sufficient to drive 50Ω transmission lines on the incident
edge. Note from the delay measurements in the simulations a
delta of only 43ps exists between the two differently loaded
outputs. This suggests that the dual line driving need not be
used exclusively to maintain the tight output-to-output skew
of the MPC9352. The output waveform in Figure 11. “Single
versus Dual Line Termination Waveforms” shows a step in
the waveform, this step is caused by the impedance
mismatch seen looking into the driver. The parallel
combination of the 36Ω series resistor plus the output
impedance does not match the parallel combination of the
line impedances. The voltage wave launched down the two
lines will equal:
Figure 9. Max. I/O Jitter versus frequency
Driving Transmission Lines
The MPC9352 clock driver was designed to drive high
speed signals in a terminated transmission line environment.
To provide the optimum flexibility to the user the output
drivers were designed to exhibit the lowest impedance
possible. With an output impedance of less than 20Ω the
drivers can drive either parallel or series terminated
transmission lines. For more information on transmission
lines the reader is referred to Motorola application note
AN1091. In most high performance clock networks
point-to-point distribution of signals is the method of choice.
In a point-to-point scheme either series terminated or parallel
terminated transmission lines can be used. The parallel
technique terminates the signal at the end of the line with a
50Ω resistance to VCC÷2.
TIMING SOLUTIONS
= VS ( Z0 ÷ (RS+R0 +Z0))
= 50Ω || 50Ω
= 36Ω || 36Ω
= 14Ω
= 3.0 ( 25 ÷ (18+17+25)
= 1.31V
At the load end the voltage will double, due to the near
unity reflection coefficient, to 2.6V. It will then increment
towards the quiescent 3.0V in steps separated by one round
trip delay (in this case 4.0ns).
VL
Z0
RS
R0
VL
11
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Freescale Semiconductor, Inc.
MPC9352
4
@E68
4
*
9 4
4
match the impedances when driving multiple lines the
situation in Figure 12. “Optimized Dual Line Termination”
should be used. In this case the series terminating resistors
are reduced such that when the parallel combination is added
to the output buffer impedance the line impedance is perfectly
matched.
*
9 4
(
C@C@
C
4
4
D 9 Ω
9 Ω
D 9 Ω
Ω
4
Freescale Semiconductor, Inc...
9 Ω
@ 6(8
14Ω + 22Ω k 22Ω = 50Ω k 50Ω
25Ω = 25Ω
Figure 12. Optimized Dual Line Termination
Figure 11. Single versus Dual Waveforms
Since this step is well above the threshold region it will not
cause any false clock triggering, however designers may be
uncomfortable with unwanted reflections on the line. To better
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Figure 13. CCLK MPC9352 AC test reference for Vcc = 3.3V and Vcc = 2.5V
MOTOROLA
12
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TIMING SOLUTIONS
Freescale Semiconductor, Inc.
MPC9352
B
B
B
B
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Figure 14. Output–to–output Skew tSK(O)
Figure 15. Propagation delay (t(∅), static phase
offset) test reference
B
@
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Figure 17. I/O Jitter
Figure 16. Output Duty Cycle (DC)
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Figure 18. Cycle–to–cycle Jitter
F F
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Figure 19. Period Jitter
94
94
4
4
4
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Figure 20. Output Transition Time Test Reference
TIMING SOLUTIONS
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Freescale Semiconductor, Inc.
MPC9352
OUTLINE DIMENSIONS
FA SUFFIX
LQFP PACKAGE
CASE 873A-02
ISSUE A
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Freescale Semiconductor, Inc...
V1
17
8
SECTION AE–AE
MOTOROLA
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Freescale Semiconductor, Inc.
MPC9352
Freescale Semiconductor, Inc...
NOTES
TIMING SOLUTIONS
15
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Freescale Semiconductor, Inc...
MPC9352
Freescale Semiconductor, Inc.
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MPC9352/D
TIMING
SOLUTIONS