Freescale Semiconductor Advance Information MR2A16A/D Rev. 0.1, 7/2004 256K x 16-Bit 3.3-V Asynchronous Magnetoresistive RAM Introduction The MR2A16A is a 4,194,304-bit magnetoresistive random access memory (MRAM) device organized as 262,144 words of 16 bits. The MR2A16A is equipped with chip enable (E), write enable (W), and output enable (G) pins, allowing for significant system design flexibility without bus contention. Because the MR2A16A has separate byte-enable controls (LB and UB), individual bytes can be written and read. MRAM is a nonvolatile memory technology that protects data in the event of power loss and does not require periodic refreshing. The MR2A16A is the ideal memory solution for applications that must permanently store and retrieve critical data quickly. The MR2A16A is available in a 400-mil, 44-lead plastic small-outline TSOP type-II package with an industry-standard center power and ground SRAM pinout. Features • Single 3.3-V power supply • Commercial temperature range (0°C to 70°C) • Symmetrical high-speed read and write with fast access time (25 ns) • Flexible data bus control — 8 bit or 16 bit access • Equal address and chip-enable access times • Automatic data protection with low-voltage inhibit circuitry to prevent writes on power loss • All inputs and outputs are transistor-transistor logic (TTL) compatible • Fully static operation • Full nonvolatile operation with 10 years minimum data retention © Freescale Semiconductor, Inc., 2004. All rights reserved. This document contains information on a new product. Specifications and information herein are subject to change without notice. Device Pin Assignment OUTPUT ENABLE BUFFER G UPPER BYTE OUTPUT ENABLE LOWER BYTE OUTPUT ENABLE 8 A[17:0] ADDRESS BUFFERS 18 10 ROW DECODER COLUMN DECODER CHIP ENABLE BUFFER E UB SENSE AMPS 8 LOWER BYTE OUTPUT BUFFER 256K x 16 BIT MEMORY ARRAY 16 UB 8 FINAL WRITE DRIVERS 8 UPPER BYTE WRITE ENABLE BYTE ENABLE BUFFER LB LB 8 16 WRITE ENABLE BUFFER W UPPER BYTE OUTPUT BUFFER 8 8 UPPER BYTE WRITE DRIVER 8 LOWER BYTE WRITE DRIVER DQU[15:8] 8 DQL[7:0] LOWER BYTE WRITE ENABLE Figure 1. Block Diagram Device Pin Assignment A16 A17 A10 A11 A12 E DQL0 DQL1 DQL2 DQL3 VDD VSS DQL4 DQL5 DQL6 DQL7 W A0 A1 A2 A3 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A15 A14 A13 G UB LB DQU15 DQU14 DQU13 DQU12 VSS VDD DQU11 DQU10 DQU9 DQU8 NC A9 A8 A7 A6 A5 Table 1. Pin Functions Signal Name Function A[17:0] Address input E Chip enable W Write enable G Output enable UB Upper byte select LB Lower byte select DQL[7:0] Data I/O, lower byte DQU[15:8] Data I/O, upper byte VDD +3.3-V power supply VSS Ground NC Do not connect this pin Figure 2. MR2A16A in 44-Pin TSOP Type II Package MR2A16A/D, Rev. 0.1 2 Freescale Semiconductor Electrical Specifications Table 2. Operating Modes Mode VDD Current DQL[7:0] DQU[15:8] X Not selected ISB1, ISB2 Hi-Z Hi-Z X X Output disabled IDDA Hi-Z Hi-Z X H H Output disabled IDDA Hi-Z Hi-Z L H L H Lower byte read IDDA DOut Hi-Z L L H H L Upper byte read IDDA Hi-Z DOut L L H L L Word read IDDA DOut DOut L X L L H Lower byte write IDDA DIn Hi-Z L X L H L Upper byte write IDDA Hi-Z DIn L X L L L Word write IDDA DIn DIn E G W LB UB H X X X L H H L X L NOTES: 1. H = high, L = low, X = don’t care 2. Hi-Z = high impedance Electrical Specifications Absolute Maximum Ratings This device contains circuitry to protect the inputs against damage caused by high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage greater than maximum rated voltages to these high-impedance (Hi-Z) circuits. The device also contains protection against external magnetic fields. Precautions should be taken to avoid application of any magnetic field more intense than the maximum field intensity specified in the maximum ratings. Table 3. Absolute Maximum Ratings Parameter Symbol Value Unit Supply voltage VDD –0.5 to 4.6 V Voltage on any pin VIn –0.5 to VDD + 0.5 V Output current per pin IOut ±20 mA Package power dissipation PD TBD W Temperature under bias TBias –10 to 85 °C Storage temperature Tstg –55 to 150 °C Lead temperature during solder (3 minute max) TLead 235 °C Maximum magnetic field at package surface Hmax 20 oe NOTES: 1. Permanent device damage may occur if absolute maximum ratings are exceeded. Functional operation should be restricted to recommended operating conditions. Exposure to excessive voltages or magnetic fields could affect device reliability. 2. All voltages are referenced to VSS. 3. Power dissipation capability depends on package characteristics and use environment. MR2A16A/D, Rev. 0.1 Freescale Semiconductor 3 Electrical Specifications Table 4. Operating Conditions Parameter Symbol Power supply voltage VDD Min 3.0 (1) Typ Max Unit 3.3 3.6 V (1) Write inhibit voltage VWI 2.5 2.7 Input high voltage VIH 2.2 — VDD + 0.3(2) V — 0.8 V 70 °C Input low voltage VIL –0.5 Operating temperature TA 0 (3) 3.0 V NOTES: 1. After power up or if VDD falls below V WI, a waiting period of 1 µs must be observed. Memory is designed to prevent writing for all input pin conditions if VDD falls below minimum VWI. 2. VIH (max) = V DD + 0.3 Vdc; VIH (max) = VDD + 2.0 Vac (pulse width ≤ 10 ns) for I ≤ 20.0 mA. 3. VIL (min) = –0.5 Vdc; VIL (min) = –2.0 Vac (pulse width ≤ 10 ns) for I ≤ 20.0 mA. Direct Current (dc) Table 5. dc Characteristics Parameter Symbol Min Typ Max Unit Input leakage current Ilkg(I) — — ±1 µA Output leakage current Ilkg(O) — — ±1 µA Output low voltage (IOL = +4 mA) (IOL = +100 µA) VOL — — 0.4 VSS + 0.2 V Output high voltage (IOH = –4 mA) (IOH = –100 mA) VOH 2.4 VDD – 0.2 — — V Table 6. Power Supply Characteristics Parameter ac active supply current — Read Modes (IOut = 0 mA, VDD = max) ac active supply current — Write Modes (VDD = max) ac standby current (VDD = max, E = VIH) (no other restrictions on other inputs) CMOS standby current (E ≥ VDD – 0.2 V and VIn ≤ VSS + 0.2 V or ≥ VDD – 0.2 V) (VDD = max, f = 0 MHz) Timing Set Symbol Typ Max Unit 20 IDDR TBD TBD mA 25 IDDR TBD TBD mA 35 IDDR TBD TBD mA 20 IDDW TBD TBD mA 25 IDDW TBD TBD mA 35 IDDW TBD TBD mA 20 ISB1 TBD TBD mA 25 ISB1 TBD TBD mA 35 ISB1 TBD TBD mA ISB2 TBD TBD mA MR2A16A/D, Rev. 0.1 4 Freescale Semiconductor Electrical Specifications Table 7. Capacitance Parameter Symbol Typ Max Unit Address input capacitance CIn — 6 pF Control input capacitance CIn — 6 pF Input/Output capacitance CI/O — 8 pF NOTES: 1. (f = 1.0 MHz, dV = 3.0 V, TA = 25°C, periodically sampled rather than 100% tested) Table 8. ac Measurement Conditions Parameter Value Logic input timing measurement reference level 1.5 V Logic output timing measurement reference level 1.5 V Logic input pulse levels 0 or 3.0 V Input rise/fall time 2 ns Output load for low and high impedance parameters See Figure 3A Output load for all other timing parameters See Figure 3B +3.3 V ZD = 50 Ω 725 Ω OUTPUT OUTPUT RL = 50 Ω 600 Ω 5 pF VL = 1.5 V A B Figure 3. Output Load for ac Test MR2A16A/D, Rev. 0.1 Freescale Semiconductor 5 Timing Specifications Timing Specifications Read Mode Table 9. Read Cycle Timing (See Notes 1 and 2) Timing Set Parameter Symbol 20 25 35 Unit Min Max Min Max Min Max Notes Read cycle time tAVAV 20 — 25 — 35 — ns Address access time tAVQV — 20 — 25 — 35 ns Enable access time tELQV — 20 — 25 — 35 ns Output enable access time tGLQV — 10 — 11 — 15 ns Byte enable access time tBLQV — 10 — 11 — 15 ns Output hold from address change tAXQX 3 — 3 — 3 — ns Enable low to output active tELQX 3 — 3 — 3 — ns 4, 5 Output enable low to output active tGLQX 0 — 0 — 0 — ns 4, 5 Byte enable low to output active tBLQX 0 — 0 — 0 — ns 4, 5 Enable high to output Hi-Z tEHQZ 0 10 0 11 0 15 ns 4, 5 Output enable high to output Hi-Z tGHQZ 0 6 0 7 0 10 ns 4, 5 Byte high to output Hi-Z tBHQZ 0 6 0 7 0 10 ns 4, 5 3 NOTES: 1. W is high for read cycle. 2. Due to product sensitivities to noise, power supplies must be properly grounded and decoupled and bus contention conditions must be minimized or eliminated during read and write cycles. 3. Addresses valid before or at the same time E goes low. 4. This parameter is sampled and not 100% tested. 5. Transition is measured ±200 mV from steady-state voltage. MR2A16A/D, Rev. 0.1 6 Freescale Semiconductor Timing Specifications tAVAV A (ADDRESS) tAXQX Q (DATA OUT) PREVIOUS DATA VALID DATA VALID tAVQV NOTES: 1. Device is continuously selected (E ≤ VIL, G ≤ VIL). Figure 4. Read Cycle 1 tAVAV A (ADDRESS) tAVQV tELQV E (CHIP ENABLE) tEHQZ tELQX G (OUTPUT ENABLE) tGHQZ tGLQV tGLQX LB, UB (BYTE ENABLE) tBHQZ tBLQV tBLQX DATA VALID Q (DATA OUT) Figure 5. Read Cycle 2 MR2A16A/D, Rev. 0.1 Freescale Semiconductor 7 Timing Specifications Write Mode Table 10. Write Cycle Timing 1 (W Controlled; See Notes 1, 2, 3, and 4) Timing Set Parameter Symbol 20 25 35 Min Max Min Max Min Max Unit Notes 8 Write cycle time tAVAV 20 — 25 — 35 — ns Address set-up time tAVWL 0 — 0 — 0 — ns Address valid to end of write (G high) tAVWH 12 — 15 — 18 — ns Address valid to end of write (G low) tAVWH 15 — 17 — 20 — ns Write pulse width (G high) tWLWH tWLEH 8 — 10 — 15 — ns Write pulse width (G low) tWLWH tWLEH 8 — 10 — 15 — ns Data valid to end of write tDVWH 5 — 6 — 10 — ns Data hold time tWHDX 0 — 0 — 0 — ns Write low to data Hi-Z tWLQZ 0 7 0 9 0 12 ns 5, 6, 7 Write high to output active tWHQX 3 — 3 — 3 — ns 5, 6, 7 Write recovery time tWHAX 8 — 10 — 12 — ns NOTES: 1. A write occurs during the overlap of E low and W low. 2. Due to product sensitivities to noise, power supplies must be properly grounded and decoupled and bus contention conditions must be minimized or eliminated during read and write cycles. 3. If G goes low at the same time or after W goes low, the output will remain in a high-impedance state. 4. After W, E, or UB/LB has been brought high, the signal must remain in steady-state high for a minimum of 2 ns. 5. This parameter is sampled and not 100% tested. 6. Transition is measured ±200 mV from steady-state voltage. 7. At any given voltage or temperature, tWLQZ max < tWHQX min. 8. All write cycle timings are referenced from the last valid address to the first transition address. MR2A16A/D, Rev. 0.1 8 Freescale Semiconductor Timing Specifications tAVAV A (ADDRESS) tAVWH tWHAX E (CHIP ENABLE) tWLEH tWLWH W (WRITE ENABLE) tAVWL LB, UB (BYTE ENABLE) tDVWH D (DATA IN) tWHDX DATA VALID tWLQZ Q (DATA OUT) Hi-Z Hi-Z tWHQX Figure 6. Write Cycle 1 (W Controlled) MR2A16A/D, Rev. 0.1 Freescale Semiconductor 9 Timing Specifications Table 11. Write Cycle Timing 2 (E Controlled; See Notes 1,2,3, and 4) Timing Set Parameter Symbol 20 25 35 Min Max Min Max Min Max Unit Notes 7 Write cycle time tAVAV 20 — 25 — 35 — ns Address set-up time tAVEL 0 — 0 — 0 — ns Address valid to end of write (G high) tAVEH 12 — 15 — 18 — ns Address valid to end of write (G low) tAVEH 15 — 17 — 20 — ns Enable to end of write (G high) tELEH tELWH 8 — 10 — 15 — ns Enable to end of write (G low) tELEH tELWH 8 — 10 — 15 — ns Data valid to end of write tDVEH 5 — 6 — 10 — ns Data hold time tEHDX 0 — 0 — 0 — ns Write recovery time tEHAX 8 — 10 — 12 — ns 5, 6 NOTES: 1. A write occurs during the overlap of E low and W low. 2. Due to product sensitivities to noise, power supplies must be properly grounded and decoupled and bus contention conditions must be minimized or eliminated during read and write cycles. 3. If G goes low at the same time or after W goes low, the output will remain in a high-impedance state. 4. After W, E, or UB/LB has been brought high, the signal must remain in steady-state high for a minimum of 2 ns. 5. If E goes low at the same time or after W goes low, the output will remain in a high-impedance state. 6. If E goes high at the same time or before W goes high, the output will remain in a high-impedance state. 7. All write cycle timings are referenced from the last valid address to the first transition address. MR2A16A/D, Rev. 0.1 10 Freescale Semiconductor Timing Specifications tAVAV A (ADDRESS) tAVEH tEHAX tELEH E (CHIP ENABLE) tAVEL tELWH W (WRITE ENABLE) LB, UB (BYTE ENABLE) tDVEH D (DATA IN) Q (DATA OUT) tEHDX DATA VALID Hi-Z Figure 7. Write Cycle 2 (E Controlled) MR2A16A/D, Rev. 0.1 Freescale Semiconductor 11 Timing Specifications Table 12. Write Cycle Timing 3 (LB/UB Controlled; See Notes 1, 2, 3, 4, and 5) Timing Set Parameter Symbol 20 25 35 Min Max Min Max Min Max Unit Notes 6 Write cycle time tAVAV 20 — 25 — 35 — ns Address set-up time tAVBL 0 — 0 — 0 — ns Address valid to end of write (G high) tAVBH 12 — 15 — 18 — ns Address valid to end of write (G low) tAVBH 15 — 17 — 20 — ns Byte pulse width (G high) tBLEH tBLWH 8 — 10 — 15 — ns Byte pulse width (G low) tBLEH tBLWH 8 — 10 — 15 — ns Data valid to end of write tDVBH 5 — 6 — 10 — ns Data hold time tBHDX 0 — 0 — 0 — ns Write recovery time tBHAX 8 — 10 — 12 — ns NOTES: 1. A write occurs during the overlap of E low and W low. 2. Due to product sensitivities to noise, power supplies must be properly grounded and decoupled and bus contention conditions must be minimized or eliminated during read and write cycles. 3. If G goes low at the same time or after W goes low, the output will remain in a high-impedance state. 4. After W, E, or UB/LB has been brought high, the signal must remain in steady-state high for a minimum of 2 ns. 5. If both byte control signals are asserted, the two signals must have no more than 2 ns skew between them. 6. All write cycle timings are referenced from the last valid address to the first transition address. MR2A16A/D, Rev. 0.1 12 Freescale Semiconductor Timing Specifications tAVAV A (ADDRESS) tAVBH tBHAX E (CHIP ENABLE) tAVBL tBLEH tBLWH LB, UB (BYTE ENABLE) tBHDX W (WRITE ENABLE) tDVBH D (DATA IN) Q (DATA OUT) DATA VALID Hi-Z Hi-Z Figure 8. Write Cycle 3 (LB/UB Controlled) MR2A16A/D, Rev. 0.1 Freescale Semiconductor 13 Ordering Information Ordering Information (Order by Full Part Number) MR 2 A 16 A TS 25 C Operating Temperature Range (C = 0° C to 70° C) Timing Set Package Type (TS = TSOP) Revision (A = rev 1) I/O Configuration (08 = 8 bits, 16 = 16 bits) Freescale MRAM Memory Prefix Density Code (2 = 4 Mb, 4 = 16 Mb) Memory Type (A = Asynch, S = Sync) Commercial Device Numbers — MR2A16ATS25C MR2A16ATS35C TS Package (44-Lead, TSOP Type II, Case 924A-02) VIEW D B 44 23 0.15 0.05 0.60 0.40 5_ 0_ VIEW D ROTATED 90 _ CLOCKWISE 10.29 10.03 3 E E 1 1.05 0.95 1.20 MAX 22 18.54 18.28 A 0.21 0.12 11.96 11.56 0.2 M C B 22X 3 ÉÉÉÉÉ ÉÉÉÉÉ ÉÉÉÉÉ 0.45 0.30 0.2 M C A 4 SECTION E–E 40 PLACES 44X 0.1 C SEATING PLANE 4X 0.8 /2 42X 0.8 C NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. DIMENSIONS IN MILLIMETERS. 3. DIMENSIONS DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE MOLD PROTRUSION IS 0.15 PER SIDE. 4. DIMENSIONS DO NOT INCLUDE DAMBAR PROTRUSIONS. DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED 0.58. Notes MR2A16A/D, Rev. 0.1 14 Freescale Semiconductor Notes This page is intentionally blank MR2A16A/D, Rev. 0.1 Freescale Semiconductor 15 How to Reach Us: Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted USA/Europe/Locations not listed: Freescale Semiconductor Literature Distribution P.O. Box 5405, Denver, Colorado 80217 1-800-521-6274 or 480-768-2130 hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the Japan: Freescale Semiconductor Japan Ltd. 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