in im el Pr ¡ Semiconductor MSC23V26457TA-xxBS8/MSC23V26457SA-xxBS8 y ar ¡ Semiconductor MSC23V26457TA-xxBS8/ MSC23V26457SA-xxBS8 2,097,152-Word ¥ 64-Bit DRAM MODULE : FAST PAGE MODE TYPE WITH EDO DESCRIPTION The Oki MSC23V26457TA-xxBS8/MSC23V26457SA-xxBS8 is a fully decoded 2,097,152-word ¥ 64-bit CMOS dynamic random access memory composed of eight 16-Mb DRAMs (2M ¥ 8) in TSOP or SOJ packages mounted with decoupling capacitors on an 168-pin glass epoxy DIMM Package supports any application where high density and large capacity of storage memory are required. FEATURES • 2,097,152-word ¥ 64-bit (8 Byte) organization • 168-pin DIMM MSC23V26457TA-xxBS8 : TSOP type MSC23V26457SA-xxBS8 : SOJ type • Single 3.3 V supply ±0.3 V tolerance • Input : LVTTL compatible • Output : LVTTL compatible, 3-state, nonlatch • Refresh : 2048 cycles/32 ms • CAS before RAS refresh, CAS before RAS hidden refresh, RAS-only refresh capability • Multi-bit test mode capability • Fast Page Mode with EDO capability • Serial Presence Detect PRODUCT FAMILY Family MSC23V26457TA-60BS8 MSC23V26457SA-60BS8 MSC23V26457TA-70BS8 MSC23V26457SA-70BS8 Access Time (Max.) tRAC tAA tCAC tOEA Power Dissipation Cycle Time Operating (Max.) Standby (Max.) (Min.) 60 ns 30 ns 15 ns 15 ns 110 ns 4320 mW 70 ns 35 ns 20 ns 20 ns 130 ns 3744 mW 28.8 mW 631 8 MSC23V26457TA-xxBS8/MSC23V26457SA-xxBS8 ¡ Semiconductor PIN CONFIGURATION MSC23V26457TA-xxBS8 (Unit : mm) *1 133.35 ±0.2 2.67 Max. 3.0 ±0.13 17.78 ±0.13 25.4 ±0.13 2 – R2 ±0.1 2 – φ3 ±0.1 A B 11.43 ±0.1 36.83 ±0.1 21.495 ±0.13 45.18 ±0.13 5.89 ±0.13 3.0 ±0.13 84 6.0 Min. 2 – R1 ±0.1 54.61 ±0.1 1.27 ±0.1 127.35 Typ. 1.0 ±0.1 CL 0.25 Max. 3.00 ±0.13 8 3.00 ±0.13 2.0 ±0.1 2.0 ±0.1 6.35 ±0.1 6.35 ±0.1 DETAIL A DETAIL B *1 The common size difference of the board width 19.78 mm of its height is specified as ±0.2. The value above 19.78 mm is specified as ±0.5. 632 0.23 Min. 1.27 ±0.1 ¡ Semiconductor MSC23V26457TA-xxBS8/MSC23V26457SA-xxBS8 MSC23V26457SA-xxBS8 (Unit : mm) *1 133.35 ±0.2 5.28 Max. 3.0 ±0.13 17.78 ±0.13 25.4 ±0.13 2 – R2 ±0.1 2 – φ3 ±0.1 A B 11.43 ±0.1 36.83 ±0.1 21.495 ±0.13 45.18 ±0.13 5.89 ±0.13 3.0 ±0.13 84 6.0 Min. 2 – R1 ±0.1 54.61 ±0.1 1.27 ±0.1 127.35 Typ. 1.0 ±0.1 CL 0.25 Max. 3.00 ±0.13 3.00 ±0.13 2.0 ±0.1 2.0 ±0.1 6.35 ±0.1 6.35 ±0.1 DETAIL A DETAIL B 0.23 Min. 1.27 ±0.1 *1 The common size difference of the board width 19.78 mm of its height is specified as ±0.2. The value above 19.78 mm is specified as ±0.5. 8 633 MSC23V26457TA-xxBS8/MSC23V26457SA-xxBS8 ¡ Semiconductor Front Side Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name 1 VSS 18 VCC 35 A4 52 NC 69 DQ24 2 DQ0 19 DQ14 36 A6 53 NC 70 DQ25 3 DQ1 20 DQ15 37 A8 54 VSS 71 DQ26 4 DQ2 21 NC 38 A10R 55 DQ16 72 DQ27 5 DQ3 22 NC 39 NC 56 DQ17 73 VCC 6 VCC 23 VSS 40 VCC 57 DQ18 74 DQ28 7 DQ4 24 NC 41 VCC 58 DQ19 75 DQ29 8 DQ5 25 NC 42 NC 59 VCC 76 DQ30 9 DQ6 26 VCC 43 VSS 60 DQ20 77 DQ31 10 DQ7 27 WE0 44 OE2 61 NC 78 VSS 11 DQ8 28 CAS0 45 RAS2 62 NC 79 NC 12 VSS 29 CAS1 46 CAS2 63 NC 80 NC 13 DQ9 30 RAS0 47 CAS3 64 VSS 81 NC 14 DQ10 31 OE0 48 WE2 65 DQ21 82 SDA 15 DQ11 32 VSS 49 VCC 66 DQ22 83 SCL 16 DQ12 33 A0 50 NC 67 DQ23 84 VCC 17 DQ13 34 A2 51 NC 68 VSS Back Side Pin No. Pin Name 85 8 Pin No. Pin Name VSS 102 86 DQ32 87 DQ33 Pin No. Pin Name VCC 119 103 DQ46 104 DQ47 Pin No. Pin Name Pin No. Pin Name NC 153 DQ56 137 NC 154 DQ57 138 VSS 155 DQ58 A5 136 120 A7 121 A9 88 DQ34 105 NC 122 NC 139 DQ48 156 DQ59 89 DQ35 106 NC 123 NC 140 DQ49 157 VCC 90 VCC 107 VSS 124 VCC 141 DQ50 158 DQ60 91 DQ36 108 NC 125 NC 142 DQ51 159 DQ61 92 DQ37 109 NC 126 NC 143 VCC 160 DQ62 93 DQ38 110 VCC 127 VSS 144 DQ52 161 DQ63 94 DQ39 111 NC 128 NC 145 NC 162 VSS 95 DQ40 112 CAS4 129 NC 146 NC 163 NC 96 VSS 113 CAS5 130 CAS6 147 NC 164 NC 97 DQ41 114 NC 131 CAS7 148 VSS 165 SA0 98 DQ42 115 NC 132 NC 149 DQ53 166 SA1 99 DQ43 116 VSS 133 VCC 150 DQ54 167 SA2 100 DQ44 117 A1 134 NC 151 DQ55 168 VCC 101 DQ45 118 A3 135 NC 152 VSS 634 ¡ Semiconductor MSC23V26457TA-xxBS8/MSC23V26457SA-xxBS8 Serial PD Matrix Byte Number Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 1 1 0 1 Number of Bytes used (13 Bytes) 1 0 0 0 0 1 0 0 0 Total SPD Memory size (256 Bytes) 2 0 0 0 0 0 0 1 0 Memory type (EDO) 3 0 0 0 0 1 0 1 1 Number of Rows (11) 4 0 0 0 0 1 0 1 0 Number of Columns (10) 5 0 0 0 0 0 0 0 1 Number of Banks (1) 6 0 1 0 0 0 0 0 0 Module Data Width (64) 7 0 0 0 0 0 0 0 0 Module Data Width Continued (0) 8 0 0 0 0 0 0 1 0 Supply Voltage (3.3 V, LVTTL) Remark 9 (-60) 0 0 1 1 1 1 0 0 RAS Access Time (60 ns) 9 (-70) 0 1 0 0 0 1 1 0 RAS Access Time (70 ns) 10 (-60) 0 0 0 0 1 1 1 1 CAS Access Time (15 ns) 10 (-70) 0 0 0 1 0 1 0 0 CAS Access Time (20 ns) 11 0 0 0 0 0 0 0 0 Non parity 12 0 0 0 0 0 0 0 0 Normal Refresh 8 635 MSC23V26457TA-xxBS8/MSC23V26457SA-xxBS8 ¡ Semiconductor BLOCK DIAGRAM A0 - A9 A10R RAS0 RAS2 WE0 OE0 A0 - A9 A10R RAS CAS CAS0 WE OE VCC A0 - A9 A10R RAS CAS CAS1 WE OE VCC A0 - A9 A10R RAS CAS CAS2 WE OE VCC A0 - A9 A10R RAS CAS CAS3 WE OE 8 VCC DQ DQ DQ DQ DQ DQ DQ DQ DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 WE2 OE2 WE DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 A0 - A9 A10R RAS CAS5 VSS CAS WE OE A0 - A9 A10R RAS CAS6 CAS WE OE A0 - A9 A10R RAS CAS7 CAS WE OE VCC DQ DQ DQ DQ DQ DQ DQ DQ DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ DQ DQ DQ DQ DQ DQ DQ DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 VSS VCC DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 VSS VCC DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ DQ DQ DQ DQ DQ DQ DQ VSS VCC VSS DQ DQ DQ DQ DQ DQ DQ DQ CAS OE VSS DQ DQ DQ DQ DQ DQ DQ DQ A10R RAS CAS4 VSS DQ DQ DQ DQ DQ DQ DQ DQ A0 - A9 DQ DQ DQ DQ DQ DQ DQ DQ DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 VSS VCC C1 C8 VSS SCL SDA SA0 SCL SDA A0 SA1 A1 SA2 A2 Serial PD 636 ¡ Semiconductor MSC23V26457TA-xxBS8/MSC23V26457SA-xxBS8 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings Parameter Symbol Rating Unit Voltage on Any Pin Relative to VSS VIN, VOUT –0.5 to 4.6 V Voltage VCC Supply Relative to VSS VCC –0.5 to 4.6 V Short Circuit Output Current IOS 50 mA Power Dissipation PD 8 W Operating Temperature Topr 0 to 70 °C Storage Temperature Tstg –40 to 125 °C Note: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Recommended Operating Conditions (Ta = 0°C to 70°C) Parameter Power Supply Voltage Symbol Min. Typ. Max. Unit VCC 3.0 3.3 3.6 V VSS 0 0 0 V Input High Voltage VIH 2.0 — VCC + 0.3 V Input Low Voltage VIL –0.3 — 0.8 V Capacitance (Ta = 25°C, f = 1 MHz) Parameter Symbol Typ. Max. Unit Input Capacitance (A0 - A9, A10R) CIN1 — 49 pF CIN2 — 35 pF Input Capacitance (CAS0 - CAS7) CIN3 — 13 pF I/O Capacitance (DQ0 - DQ63) CDQ — 13 pF Input Capacitance (RAS0, RAS2, WE0, WE2, OE0, OE2) 8 Note : Capacitance measured with Boonton Meter. 637 MSC23V26457TA-xxBS8/MSC23V26457SA-xxBS8 ¡ Semiconductor DC Characteristics (VCC = 3.3 V ±0.3 V, Ta = 0°C to 70°C) Parameter Symbol Input Leakage Current ILI Condition -60 -70 Unit Note Min. Max. Min. Max. –80 80 –80 80 µA –10 10 –10 10 µA 0 V £ VI £ VCC + 0.3 V; All other pins not under test = 0 V DOUT disable Output Leakage Current ILO Output High Voltage VOH IOH = –2.0 mA 2.4 VCC 2.4 VCC V Output Low Voltage VOL IOL = 2.0 mA 0 0.4 0 0.4 V — 1200 — 1040 — 16 — 16 mA 1 — 8 — 8 mA 1 — 1200 — 1040 mA 1, 2 — 1200 — 1040 mA 1, 2 — 1200 — 1040 mA 1, 3 Average Power Supply Current ICC1 (Operating) Power Supply Current (Standby) ICC2 tRC = Min. RAS, CAS ≥ VCC –0.2 V ICC3 CAS = VIH, tRC = Min. RAS cycling, Average Power ICC6 CAS before RAS, (CAS before RAS Refresh) tRC = Min. Average Power RAS = VIL, Supply Current (Fast Page Mode) ICC7 CAS cycling, tHPC = Min. Notes: 1. ICC Max. is specified as ICC for output open condition. 2. Address can be changed once or less while RAS=VIL. 3. Address can be changed once or less while CAS=VIH. 8 638 mA 1, 2 RAS cycling, (RAS-only Refresh) Supply Current RAS, CAS cycling, RAS, CAS = VIH Average Power Supply Current 0 V £ VO £ 3.6 V ¡ Semiconductor MSC23V26457TA-xxBS8/MSC23V26457SA-xxBS8 AC Characteristics (1/2) (VCC = 3.3 V ±0.3 V, Ta = 0°C to 70°C) Parameter Symbol -70 -60 Min. Max. Min. Max. Note 1,2,3,12,13 Unit Note tRC 110 — 130 — ns Read Modify Write Cycle Time tRWC 150 — 180 — ns Fast Page Mode Cycle Time tHPC Random Read or Write Cycle Time 25 — 30 — ns Fast Page Mode Read Modify Write Cycle Time tPRWC 80 — 95 — ns Access Time from RAS tRAC — 60 — 70 ns 4, 5, 6 Access Time from CAS tCAC — 15 — 20 ns 4, 5 Access Time from Column Address tAA — 30 — 35 ns 4, 6 Access Time from CAS Precharge tCPA — 35 — 40 ns 4 Access Time from OE Output Low Impedance Time from CAS tOEA tCLZ — 0 15 — — 0 20 — ns ns 4 4 Output Hold Time from CAS Low tDOH 5 — 5 — ns CAS to Data Output Buffer Turn-off Delay Time tCEZ 0 15 0 15 ns 7, 8 RAS to Data Output Buffer Turn-off Delay Time tREZ 0 15 0 15 ns 7, 8 OE to Data Output Buffer Turn-off Delay Time tOEZ 0 15 0 15 ns 7 WE to Data Output Buffer Turn-off Delay Time tWEZ 0 15 0 15 ns 7 3 Transition Time tT 3 50 3 50 ns Refresh Period tREF — 32 — 32 ms RAS Precharge Time tRP 40 — 50 — ns RAS Pulse Width tRAS 60 10k 70 10k ns RAS Pulse Width (Fast Page Mode) tRASP 60 100k 70 100k ns RAS Hold Time tRSH 15 — 20 — ns RAS Hold Time referenced to OE tROH 15 — 20 — ns CAS Precharge Time tCP 10 — 10 — ns CAS Pulse Width tCAS 15 10k 20 10k ns RAS Low to CAS High Delay Time tCSH 40 — 45 — ns CAS High to RAS Low Delay Time tCRP 5 — 5 — ns RAS Hold Time from CAS Precharge tRHCP 35 — 40 — ns CAS, OE Hold Time (Output Disable) tCHO 5 — 10 — ns RAS to CAS Delay Time tRCD 20 45 20 50 ns 5 RAS to Column Address Delay Time tRAD 15 30 15 35 ns 6 RAS to Second CAS Delay Time tRSCD 60 — 70 — ns Row Address Set-up Time tASR 0 — 0 — ns Row Address Hold Time tRAH 10 — 10 — ns Column Address Set-up Time tASC 0 — 0 — ns Column Address Hold Time tCAH 15 — 15 — ns Column Address Hold Time from RAS tAR 40 — 45 — ns Column Address to RAS Lead Time tRAL 30 — 35 — ns 8 639 MSC23V26457TA-xxBS8/MSC23V26457SA-xxBS8 ¡ Semiconductor AC Characteristics (2/2) (VCC = 3.3 V ±0.3 V, Ta = 0°C to 70°C) Parameter 8 -70 -60 Symbol Min. Max. Min. Max. Note 1,2,3,12,13 Unit Note Read Command Set-up Time tRCS 0 — 0 — ns Read Command Hold Time tRCH 0 — 0 — ns Read Command Hold Time referenced to RAS tRRH 0 — 0 — ns 9 Write Command Set-up Time tWCS 0 — 0 — ns 10 Write Command Hold Time tWCH 10 — 15 — ns Write Command Hold Time from RAS tWCR 40 — 45 — ns Write Command Pulse Width tWP 10 — 15 — ns Write Command Pulse Width (Output Disable) tWPE 5 — 10 — ns WE Low to OE Low Delay Time tOEH 15 — 20 — ns OE Precharge Time tOEP 10 — 10 — ns OE Low to CAS High Delay Time tOCH 10 — 10 — ns Write Command to RAS Lead Time tRWL 15 — 20 — ns Write Command to CAS Lead Time tCWL 15 — 20 — ns 9 Data-in Set-up Time tDS 0 — 0 — ns 11 Data-in Hold Time tDH 15 — 15 — ns 11 Data-in Hold Time from RAS tDHR 40 — 45 — ns OE to Data-in Delay Time tOED 15 — 15 — ns CAS to WE Delay Time tCWD 35 — 45 — ns 10 Column Address to WE Delay Time tAWD 50 — 60 — ns 10 RAS to WE Delay Time tRWD 80 — 95 — ns 10 CAS Precharge to WE Delay Time tCPWD 55 — 65 — ns 10 CAS Active Delay Time from RAS Precharge tRPC 5 — 5 — ns RAS to CAS Set-up Time (CAS before RAS) tCSR 5 — 5 — ns RAS to CAS Hold Time (CAS before RAS) tCHR 10 — 15 — ns WE to RAS Precharge Time (CAS before RAS) tWRP 10 — 10 — ns WE Hold Time from RAS (CAS before RAS) tWRH 10 — 10 — ns RAS to WE Set-up Time (Test Mode) tWTS 10 — 10 — ns RAS to WE Hold Time (Test Mode) tWTH 10 — 10 — ns 640 ¡ Semiconductor Notes: MSC23V26457TA-xxBS8/MSC23V26457SA-xxBS8 1. A start-up delay of 200 µs is required after power-up, followed by a minimum of eight initialization cycles (RAS-only refresh or CAS before RAS refresh) before proper device operation is achieved. 2. The AC characteristics assume tT = 5 ns. 3. VIH (Min.) and VIL (Max.) are reference levels for measuring input timing signals. Transition times (tT) are measured between VIH and VIL. 4. This parameter is measured with a load circuit equivalent to 2 TTL loads and 100 pF. 5. Operation within the tRCD (Max.) limit ensures that tRAC (Max.) can be met. tRCD (Max.) is specified as a reference point only. If tRCD is greater than the specified tRCD (Max.) limit, access time is controlled by tCAC. 6. Operation within the tRAD (Max.) limit ensures that tRAC (Max.) can be met. tRAD (Max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (Max.) limit, access time is controlled by tAA. 7. tCEZ (Max.), tREZ (Max.), tWEZ (Max.) and tOEZ (Max.) define the time at which the output achieves the open circuit condition and are not referenced to output voltage levels. 8. tCEZ and tREZ must be satisfied for open circuit condition. 9. tRCH or tRRH must be satisfied for a read cycle. 10. tWCS, tCWD, tRWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS ≥ tWCS (Min.) the cycle is an early write cycle and the data output pin will remain in a high impedance state throughout the entire cycle. If tCWD ≥ tCWD (Min.), tRWD ≥ tRWD (Min.), tAWD ≥ tAWD (Min.) and tCPWD ≥ tCPWD (Min.), the cycle is a read modify write cycle and the data output pin will contain data read from the selected cell. If neither conditions is satisfied, the data output logic state (at access time) is undefined. 11. These parameters are referenced to CAS leading edge in an early write cycle and to WE leading edge in an OE control write cycle or a read modify write cycle. 12. The test mode is initiated by performing a WE and CAS before RAS refresh cycle. This mode is latched and remains in effect until the exit cycle is generated. In the test mode CA9 is not used and each DQ pin now accesses 2 bit locations. In a read cycle, if the 2 data bits are equal, the DQ pin will indicate a high level. If the 2 data bits are not equal, the DQ pin will indicate a low level. The test mode is cleared and the memory device returned to its normal operating state by performing a RAS-only refresh cycle or a CAS before RAS refresh cycle. 13. In a test mode read cycle, the access time parameters are delayed by 5 ns. The test mode parameters are obtained by adding 5 ns to the normal read cycle values. See ADDENDUM K for AC Timing Waveforms 641 8