NB6L239 2.5V / 3.3V Any Differential Clock IN to Differential LVPECL OUT ÷1/2/4/8, ÷2/4/8/16 Clock Divider http://onsemi.com Description The NB6L239 is a high−speed, low skew clock divider with two divider circuits, each having selectable clock divide ratios; B1/2/4/8 and B2/4/8/16. Both divider circuits drive a pair of differential LVPECL outputs. (More device information on page 8). The NB6L239 is a member of the ECLinPS MAX™ Family of the high performance clock products. Features • • • • • • • • • • • • • • Maximum Clock Input Frequency, 3.0 GHz CLOCK Inputs Compatible with LVDS/LVPECL/CML/HSTL EN, MR, and SEL Inputs Compatible with LVTTL/LVCMOS Rise/Fall Time 65 ps Typical < 10 ps Typical Output−to−Output Skew Example: 622.08 MHz Input Generates 38.88 MHz to 622.08 MHz Outputs Internal 50 W Termination Provided Random Clock Jitter < 1 ps RMS QA B1 Edge Aligned to QBBn Edge Operating Range: VCC = 2.375 V to 3.465 V with VEE = 0 V Master Reset for Synchronization of Multiple Chips VBBAC Reference Output Synchronous Output Enable/Disable Pb−Free Packages are Available © Semiconductor Components Industries, LLC, 2006 December, 2006 − Rev. 5 1 MARKING DIAGRAM* 16 1 1 QFN−16 MN SUFFIX CASE 485G A L Y W G NB6L 239 ALYWG G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 12 of this data sheet. Publication Order Number: NB6L239/D NB6L239 SELA0 SELA1 B1 B2 A B4 B8 CLK VT CLK 50 W QA 50 W B2 VBBAC B B4 B8 B16 EN SELB0 SELB1 QA + MR Figure 1. Simplified Logic Diagram MR 16 VT 1 CLK 2 SELA0 SELA1 VCC 15 14 13 12 QA 11 QA NB6L239 CLK 3 10 QB VBBAC 4 9 QB 5 EN 6 7 8 SELB0 SELB1 VEE Exposed Pad (EP) Figure 2. Pinout: QFN−16 (Top View) http://onsemi.com 2 QB QB NB6L239 Table 1. PIN DESCRIPTION Pin Name 1 VT I/O Description 2 CLK LVPECL, CML, LVDS, HSTL Input Noninverted Differential CLOCK Input. 3 CLK LVPECL, CML, LVDS, HSTL Input Inverted Differential CLOCK Input. 4 VBBAC 5 EN* LVCMOS/LVTTL Input Synchronous Output Enable 6 SELB0* LVCMOS/LVTTL Input Clock Divide Select Pin 7 SELB1* LVCMOS/LVTTL Input Clock Divide Select Pin 8 VEE Power Supply Negative Supply Voltage 9 QB LVPECL Output Inverted Differential Output. Typically terminated with 50 W resistor to VCC − 2.0 V. 10 QB LVPECL Output Noninverted Differential Output. Typically terminated with 50 W resistor to VCC − 2.0 V. 11 QA LVPECL Output Inverted Differential Output. Typically terminated with 50 W resistor to VCC − 2.0 V. 12 QA LVPECL Output Noninverted Differential Output. Typically terminated with 50 W resistor to VCC − 2.0 V. 13 VCC Power Supply Positive Supply Voltage. 14 SELA1* LVCMOS/LVTTL Input Clock Divide Select Pin 15 SELA0* LVCMOS/LVTTL Input Clock Divide Select Pin 16 MR** LVCMOS/LVTTL Input Master Reset Asynchronous, Default Open High, Asserted LOW EP Power Supply (OPT) Internal 100 W Center−Tapped Termination Pin for CLK and CLK. Output Voltage Reference for Capacitor Coupled Inputs, Only. The Exposed Pad on the QFN−16 package bottom is thermally connected to the die for improved heat transfer out of package. The pad is not electrically connected to the die, but is recommended to be electrically and thermally connected to VEE on the PC board. *Pins will default LOW when left OPEN. **Pins will default HIGH when left OPEN. http://onsemi.com 3 NB6L239 + SELA0 VCC SELA1 A B4 CLK VT B1 B2 50 W R B8 QA QA 50 W CLK R B2 B4 B B8 QB QB B16 EN SELB0 SELB1 VEE + MR VBBAC Figure 3. Logic Diagram Table 2. FUNCTION TABLE CLK EN* MR** X L H X H H L FUNCTION Divide Hold Q Reset Q Table 3. CLOCK DIVIDE SELECT, QA OUTPUTS SELA1* SELA0* L L H H L H L H QA Outputs Divide by 1 Divide by 2 Divide by 4 Divide by 8 Table 4. CLOCK DIVIDE SELECT, QB OUTPUTS SELB1* SELB0* L L H H L H L H QB Outputs Divide by 2 Divide by 4 Divide by 8 Divide by 16 = Low−to−High Transition = High−to−Low Transition X = Don’t Care *Pins will default LOW when left OPEN. **Pins will default HIGH when left OPEN. http://onsemi.com 4 NB6L239 Table 5. ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor Internal Input Pullup Resistor ESD Protection 75 kW 75 kW Human Body Model Machine Model Charged Device Model Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) QFN−16 Flammability Rating Oxygen Index: 28 to 34 > 1500 V > 150 V > 1000 V Pb Pkg Pb−Free Pkg Level 1 Level 1 UL 94 V−0 @ 0.125 in Transistor Count 367 Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional Moisture Sensitivity information, refer to Application Note AND8003/D. MAXIMUM RATINGS Symbol Parameter Condition 1 VCC Positive Mode Power Supply VEE = 0 V VI Input Voltage VEE = 0 V Iout Output Current Continuous Surge IBB VBBAC Sink/Source Current TA Tstg qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm 500 lfpm qJC Thermal Resistance (Junction−to−Case) Standard Board Tsol Wave Solder Condition 2 VEE v VI v VCC Rating Unit 3.6 V 3.6 V 50 100 mA mA ± 0.5 mA Operating Temperature Range −40 to +85 °C Storage Temperature Range −65 to +150 °C 41.6 35.2 °C/W °C/W 4.0 °C/W 265 265 °C Pb Pb−Free Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. http://onsemi.com 5 NB6L239 Table 6. DC CHARACTERISTICS, CLOCK INPUTS, LVPECL OUTPUTS (VCC = 2.375 V to 3.465 V, VEE = 0 V) −405C Symbol 85°C Min Typ Max Min Typ Max Min Typ Max Unit 30 40 50 30 40 50 30 40 50 mA Output HIGH Voltage (Notes 2, 3) VCC = 3.3 V VCC = 2.5 V VCC−1150 VCC−1060 VCC−950 VCC−1100 VCC−1015 VCC − 900 VCC−1050 VCC −980 VCC − 850 mV 2150 1350 2240 1440 2350 1550 2200 1400 2285 1485 2400 1600 2250 1450 2320 1520 2450 1650 Output LOW Voltage (Notes 2, 3) VCC = 3.3 V VCC = 2.5 V VCC−1935 VCC−1775 VCC−1630 VCC−1875 VCC−1735 VCC−1580 VCC−1810 VCC−1675 VCC−1530 1365 565 1525 725 1670 870 1430 630 1565 765 1720 920 1490 690 1625 825 1770 970 Characteristic IEE Power Supply Current VOH VOL 255C mV DIFFERENTIAL INPUT DRIVEN SINGLE−ENDED (Figures 7, 10) Vth Input Threshold Reference Voltage (Note 4) 100 VCC − 100 100 VCC − 100 100 VCC − 100 mV VIH Single−ended Input HIGH Voltage Vth + 100 VCC Vth + 100 VCC Vth + 100 VCC mV VIL Single−ended Input LOW Voltage VEE Vth − 100 VEE Vth − 100 VEE Vth − 100 mV VBBAC Output Voltage Reference @ 100 mA (Note 7) VCC = 3.3 V VCC = 2.5 V VCC−1460 VCC−1330 VCC−1200 VCC−1460 VCC−1340 VCC−1200 VCC−1460 VCC−1350 VCC−1200 mV 1840 1040 1970 1170 2100 1300 1840 1040 1960 1160 2100 1300 1840 1040 1950 1150 2100 1300 DIFFERENTIAL INPUT DRIVEN DIFFERENTIALLY (Figures 8, 9, 11) (Note 6) VIHD Differential Input HIGH Voltage 100 VCC 100 VCC 100 VCC mV VILD Differential Input LOW Voltage VEE VCC – 100 VEE VCC – 100 VEE VCC – 100 mV VCMR Input Common Mode Range (Differential Cross−point Voltage) (Note 5) 50 VCC – 50 50 VCC – 50 50 VCC – 50 mV VID Differential Input Voltage (VIHD(CLK) − VILD(CLK)) and (VIHD(CLK)−VILD(CLK)) 100 VCC − VEE 100 VCC − VEE 100 VCC − VEE mV RTIN Internal Input Termination Resistor 45 55 45 55 45 55 W 50 50 50 NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 2. Input and output parameters vary 1:1 with VCC. 3. Outputs loaded with 50 W to VCC – 2.0 V for proper operation. 4. Vth is applied to the complementary input when operating in single−ended mode. 5. VCMRMIN varies 1:1 with VEE, VCMRMAX varies 1:1 with VCC. 6. Input and output voltage swing is a single−ended measurement operating in differential mode. 7. VBBAC used to rebias capacitor−coupled inputs only (see Figures 16 and 17). http://onsemi.com 6 NB6L239 Table 7. DC CHARACTERISTICS, LVTTL/LVCMOS INPUTS (VCC = 2.375 V to 3.465 V, VEE = 0 V, TA = −40°C to +85°C) Symbol Max Unit VIH Input HIGH Voltage (LVCMOS/LVTTL) Characteristic Min 2.0 Typ VCC V VIL Input LOW Voltage (LVCMOS/LVTTL) VEE 0.8 V IIH Input HIGH Current −150 150 mA IIL Input LOW Current −150 150 mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. Table 8. AC CHARACTERISTICS VCC = 2.375 V to 3.465 V; VEE = 0 V (Note 8) −40°C Symbol Min Characteristic Typ finMAX Maximum Input CLOCK Frequency 3.0 VOUTPP Output Voltage Amplitude (Notes 10, 11) QA(B2, 4, 8), QB(Bn) fin v 3.0 GHz QA(B1), QB(Bn) fin v 2.5 GHz QA(B1), QB(Bn) 2.5 GHz < fin v 3.0 GHz 450 450 300 650 650 650 tPLH, tPHL Propagation Delay to Output Differential @ 50 MHz 370 330 470 370 tRR Reset Recovery 0 ts Setup Time @ 50 MHz EN, CLK SELA/B, CLK th Hold Time @ 50 MHz CLK, EN CLK, SELA/B tskew Within−Device Skew @ 50 MHz Device−to−Device Skew Duty Cycle Skew tPW Minimum Pulse Width tJITTER RMS Random Clock Jitter (See Figure 20. Fmax/JITTER) VINPP Input Voltage Swing (Differential Configuration) (Note 10) 100 tr tf Output Rise/Fall Times @ 50 MHz (20% − 80%) 30 CLK, Qn MR, Qn Max Min Typ Max Min Typ Max 3.0 Unit GHz mV 650 630 650 370 330 470 380 −90 0 0 0 −60 −300 150 700 65 200 570 430 5 25 25 450 450 200 650 610 650 400 330 500 400 −90 0 −90 ps 0 0 −60 −300 0 0 −60 −300 ps 150 700 65 200 150 700 65 200 ps 30 80 40 550 5 30 30 570 430 30 90 45 550 100 120 30 35 90 45 65 VCC −VEE 100 120 30 ps ps ps <1 VCC −VEE 60 6 30 30 600 480 550 <1 Qn, Qn 85°C 3.0 450 450 250 (Note 9) (Note 9) (Note 9) MR 25°C 70 <1 ps VCC −VEE mV 120 ps NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 8. Measured using a 750 mV, 50% duty cycle clock source. All loading with 50 W to VCC − 2.0 V. 9. Skew is measured between outputs under identical transitions and conditions. Duty cycle skew is defined only for differential operation when the delays are measured from the cross point of the inputs to the cross point of the outputs. 10. Input and output voltage swing is a single−ended measurement operating in differential mode. 11. Output Voltage Amplitude (VOHCLK − VOLCLK) at input CLOCK frequency, fin. The output frequency, fout, is the input CLOCK frequency divided by n, fout = fin B n. Input CLOCK frequency is v3.0 GHz. http://onsemi.com 7 NB6L239 Application Information The NB6L239 is a high−speed, low skew clock divider single−ended input CLOCK signals. For the with two divider circuits, each having selectable clock capacitor−coupled CLK and/or CLK inputs, VBBAC should divide ratios; B1/2/4/8 and B2/4/8/16. Both divider be connected to the VT pin and bypassed to ground with a circuits drive a pair of differential LVPECL outputs. The 0.01 mF capacitor. Inputs CLK and CLK must be signal internal dividers are synchronous to each other. Therefore, driven or auto oscillation may result. the common output edges are precisely aligned. The common enable (EN) is synchronous so that the The NB6L239 clock inputs can be driven by a variety of internal divider flip−flops will only be enabled/disabled differential signal level technologies including LVDS, when the internal clock is in the LOW state. This avoids any LVPECL, HSTL, or CML. The differential clock input chance of generating a runt pulse on the internal clock when buffer employs a pair of internal 50 W termination resistors the device is enabled/disabled, as can happen with an asynchronous control. The internal enable flip−flop is in a 100 W center−tapped configuration and accessible via clocked on the falling edge of the input clock. Therefore, all the VT pin. This feature provides transmission line associated specification limits are referenced to the negative termination on−chip, at the receiver end, eliminating edge of the clock input. external components. The VBBAC reference output can be used to rebias capacitor−coupled differential or MR CLK Q (÷1) Q (÷2) Q (÷4) Q (÷8) Q (÷16) Figure 4. Timing Diagram CLK tRR tRR MR Q (÷n) Figure 5. Master Reset Timing Diagram NOTE: On the rising edge of MR, Q goes HIGH after the first rising edge of CLK. Internal Clock Disabled Internal Clock Enabled CLK Q (÷n) EN Figure 6. Output Enable Timing Diagrams The EN signal will “freeze” the internal divider flip−flops on the first falling edge of CLK after its assertion. The internal divider flip−flops will maintain their state during the freeze. When EN is deasserted (LOW), and after the next falling edge of CLK, then the internal divider flip−flops will “unfreeze” and continue to their next state count with proper phase relationships. http://onsemi.com 8 NB6L239 CLK CLK VIH Vth VIL CLK CLK Vth Figure 7. Differential Input Driven Single−Ended Figure 8. Differential Inputs Driven Differentially VID = |VIHD(CLK) − VILD(CLK)| CLK VIHD CLK VILD Figure 9. Differential Inputs Driven Differentially VCC Vthmax VCC VCMmax VIHmax CLK VILmax VIHDmax VILDmax VCMR Vth VIHmin Vthmin VEE CLK VCMmin VILmin VEE Figure 10. Vth Diagram VIHDmin VILDmin Figure 11. VCMR Diagram http://onsemi.com 9 NB6L239 VCC VCC Zo = 50 W LVPECL Driver VT = VCC − 2.0 V VCC NB6L239 CLK Zo = 50 W 50 W LVDS Driver VEE 50 W VEE Figure 13. LVDS Interface VCC VCC NB6L239 CLK VCC Zo = 50 W 50 W CML Driver 50 W VEE 50 W VEE Figure 15. Standard 50 W Load HSTL Interface VCC VCC NB6L239 CLK VCC Zo = 50 W 50 W Differential Driver VEE NB6L239 CLK 50 W Single−Ended Driver VT = VBBAC* 50 W Zo = 50 W CLK VEE Figure 14. Standard 50 W Load CML Interface Zo = 50 W VT =VEE Zo = 50 W CLK VEE VCC NB6L239 CLK 50 W HSTL Driver VT = VCC Zo = 50 W CLK VEE Figure 12. LVPECL Interface Zo = 50 W VT = OPEN Zo = 50 W CLK VEE VCC NB6L239 CLK 50 W 50 W Zo = 50 W VCC CLK VT = VBBAC* 50 W CLK VEE VEE Figure 16. Capacitor−Coupled Differential Interface (VT Connected to VBBAC) VEE Figure 17. Capacitor−Coupled Single−Ended Interface (VT Connected to VBBAC) *VBBAC bypassed to ground with a 0.01 mF capacitor. http://onsemi.com 10 VOUTPP, OUTPUT VOLTAGE AMPLITUDE (mV) (TYPICAL) NB6L239 800 700 600 500 400 300 200 100 0 0 1 2 3 fout, CLOCK OUTPUT FREQUENCY (GHz) Figure 18. Output Voltage Amplitude (VOUTPP) versus Clock Output Frequency at Ambient Temperature (Typical) (fout QA/QB) = fin B n; fin v 3.0 GHz). CLK VINPP = VIH(CLK) − VIL(CLK) CLK Q VOUTPP = VOH(Q) − VOL(Q) Q tPHL tPLH Figure 19. AC Reference Measurement NB6L239 Q Zo = 50 W D Receiver Device Driver Device Q Zo = 50 W D 50 W 50 W VTT VTT = VCC − 2.0 V Figure 20. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D − Termination of ECL Logic Devices.) http://onsemi.com 11 NB6L239 ORDERING INFORMATION Package Shipping † NB6L239MN QFN−16, 3 x 3 mm 123 Units / Rail NB6L239MNG QFN−16, 3 x 3 mm (Pb−Free) 123 Units / Rail NB6L239MNR2 QFN−16, 3 x 3 mm 3000 / Tape & Reel NB6L239MNR2G QFN−16, 3 x 3 mm (Pb−Free) 3000 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Resource Reference of Application Notes AN1405/D − ECL Clock Distribution Techniques AN1406/D − Designing with PECL (ECL at +5.0 V) AN1503/D − ECLinPS I/O SPiCE Modeling Kit AN1504/D − Metastability and the ECLinPS Family AN1568/D − Interfacing Between LVDS and ECL AN1672/D − The ECL Translator Guide AND8001/D − Odd Number Counters Design AND8002/D − Marking and Date Codes AND8020/D − Termination of ECL Logic Devices AND8066/D − Interfacing with ECLinPS AND8090/D − AC Characteristics of ECL Devices http://onsemi.com 12 NB6L239 PACKAGE DIMENSIONS 16 PIN QFN CASE 485G−01 ISSUE C D PIN 1 LOCATION NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. 5. Lmax CONDITION CAN NOT VIOLATE 0.2 MM MINIMUM SPACING BETWEEN LEAD TIP AND FLAG A B ÇÇÇ ÇÇÇ ÇÇÇ E DIM A A1 A3 b D D2 E E2 e K L 0.15 C TOP VIEW 0.15 C (A3) 0.10 C A 16 X 0.08 C SIDE VIEW SEATING PLANE A1 SOLDERING FOOTPRINT* C 0.575 0.022 D2 16X e L 5 NOTE 5 K 12 1 16 16X 1.50 0.059 3.25 0.128 e 13 b 0.10 C A B 0.05 C EXPOSED PAD 9 E2 16X 3.25 0.128 0.30 0.012 EXPOSED PAD 8 4 MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.18 0.30 3.00 BSC 1.65 1.85 3.00 BSC 1.65 1.85 0.50 BSC 0.18 TYP 0.30 0.50 0.50 0.02 BOTTOM VIEW NOTE 3 0.30 0.012 SCALE 10:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ECLinPS and ECLinPS MAX are trademarks of Semiconductor Components Industries, LLC (SCILLC). ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). 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This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: [email protected] N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5773−3850 http://onsemi.com 13 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative NB6L239/D