FAIRCHILD NDC652

March 1996
NDC652P
P-Channel Logic Level Enhancement Mode Field Effect Transistor
General Description
Features
These P-Channel logic level enhancement mode power
field effect transistors are produced using Fairchild's
proprietary, high cell density, DMOS technology. This
very high density process is especially tailored to
minimize on-state resistance. These devices are
particularly suited for low voltage applications such as
notebook computer power management and other
battery powered circuits where fast high-side switching,
and low in-line power loss are needed in a very small
outline surface mount package.
-2.4A, -30V. RDS(ON) = 0.18Ω @ VGS = -4.5V
RDS(ON) = 0.11Ω @ VGS = -10V.
Proprietary SuperSOTTM-6 package design using copper
lead frame for superior thermal and electrical capabilities.
High density cell design for extremely low RDS(ON).
Exceptional on-resistance and maximum DC current
capability.
____________________________________________________________________________________________
Absolute Maximum Ratings
4
3
5
2
6
1
T A = 25°C unless otherwise noted
Symbol Parameter
NDC652P
Units
-30
V
VDSS
Drain-Source Voltage
VGSS
Gate-Source Voltage - Continuous
-20
V
ID
Drain Current - Continuous
-2.4
A
- Pulsed
PD
Maximum Power Dissipation
-10
(Note 1a)
(Note 1b)
(Note 1c)
TJ,TSTG
Operating and Storage Temperature Range
1.6
W
1
0.8
-55 to 150
°C
(Note 1a)
78
°C/W
(Note 1)
30
°C/W
THERMAL CHARACTERISTICS
RθJA
Thermal Resistance, Junction-to-Ambient
RθJC
Thermal Resistance, Junction-to-Case
© 1997 Fairchild Semiconductor Corporation
NDC652P Rev. D1
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted)
Symbol
Parameter
Conditions
Min
-30
Typ
Max
Units
1
µA
OFF CHARACTERISTICS
BVDSS
Drain-Source Breakdown Voltage
VGS = 0 V, ID = -250 µA
IDSS
Zero Gate Voltage Drain Current
VDS = -24 V, VGS = 0 V
V
TJ = 55oC
10
µA
IGSSF
Gate - Body Leakage, Forward
VGS = 20 V, VDS = 0 V
100
nA
IGSSR
Gate - Body Leakage, Reverse
VGS = -20 V, VDS= 0 V
-100
nA
V
ON CHARACTERISTICS (Note 2)
VGS(th)
Gate Threshold Voltage
VDS = VGS, ID = -250 µA
TJ = 125oC
RDS(ON)
Static Drain-Source On-Resistance
-1
-1.5
-3
-0.7
-1.2
-2.2
0.16
0.18
0.22
0.36
0.09
0.11
VGS = -4.5 V, ID = -2.4 A
TJ = 125oC
VGS = -10 V, ID = -3.1 A
ID(on)
On-State Drain Current
VGS = -4.5 V, VDS = -5 V
gFS
Forward Transconductance
VDS = -10 V, ID = -2.4 A
-5
Ω
A
3
S
DYNAMIC CHARACTERISTICS
Ciss
Input Capacitance
Coss
Output Capacitance
Crss
Reverse Transfer Capacitance
VDS = -15 V, VGS = 0 V,
f = 1.0 MHz
290
pF
180
pF
60
pF
SWITCHING CHARACTERISTICS (Note 2)
tD(on)
Turn - On Delay Time
tr
Turn - On Rise Time
tD(off)
Turn - Off Delay Time
tf
Turn - Off Fall Time
Qg
Total Gate Charge
Qgs
Gate-Source Charge
Qgd
Gate-Drain Charge
VDD = -15 V, ID = -1 A,
VGEN = -4.5 V, RGEN = 6 Ω
VDS = -15 V,
ID = -2.4 A, VGS = -10 V
13
20
ns
26
35
ns
22
30
ns
19
30
ns
10.5
20
nC
1.5
nC
3.3
nC
NDC652P Rev. D1
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
-1.3
A
-1.2
V
DRAIN-SOURCE DIODE CHARACTERISTICS
IS
Continuous Source Diode Current
VSD
Drain-Source Diode Forward Voltage
-0.8
VGS = 0 V, IS = -1.3 A (Note 2)
Notes:
1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RθJC is guaranteed by
design while RθCA is determined by the user's board design.
P D (t ) =
T J−TA
R θJ A(t )
=
T J−TA
R θJ C+RθCA(t )
= I 2D (t ) × RDS(ON )
TJ
Typical RθJA using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment:
a. 78oC/W when mounted on a 1 in2 pad of 2oz cpper.
b. 125oC/W when mounted on a 0.01 in2 pad of 2oz cpper.
c. 156oC/W when mounted on a 0.003 in2 pad of 2oz cpper.
1a
1b
1c
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.
NDC652P Rev. D1
Typical Electrical Characteristics
-10
-7.0 -6.0 -5.5
-5.0
-8
-4.5
R DS(ON), NORMALIZED
I D , DRAIN-SOURCE CURRENT (A)
= -10V
-4.0
-6
-4
-3.5
-3.0
-2
DRAIN-SOURCE ON-RESISTANCE
2.5
V GS
V GS = -3.0V
-3.5
2
-4.0
1.5
-4.5
-5.0
1
-5.5
-6.0
-7.0
-10
-2.5
0
0
-0.5
V
-1
-1.5
-2
-2.5
, DRAIN-SOURCE VOLTAGE (V)
DS
0.5
-3
0
-2
Figure 1. On-Region Characteristics
-10
2.5
I D = -2.4A
1.4
R DS(on), NORMALIZED
V GS = -4.5V
1.2
1
0.8
0.6
-50
-25
0
25
50
75
100
125
DRAIN-SOURCE ON-RESISTANCE
R DS(ON), NORMALIZED
DRAIN-SOURCE ON-RESISTANCE
-8
Figure 2. On-Resistance Variation
with Drain Current and Gate Voltage
1.6
V GS = -4.5 V
2
T J = 125°C
1.5
25°C
-55°C
1
0.5
150
0
-2
T J , JUNCTION TEMPERATURE (°C)
-4
-6
I D , DRAIN CURRENT (A)
-8
-10
Figure 4. On-Resistance Variation
with Drain Current and Temperature
Figure 3. On-Resistance Variation
with Temperature
-10
T J = -55°C
V th, NORMALIZED
GATE-SOURCE THRESHOLD VOLTAGE
1.2
V DS = - 10V
125°C
-8
I D , DRAIN CURRENT (A)
-4
-6
ID , DRAIN CURRENT (A)
25°C
-6
-4
-2
0
-1
-2
-3
-4
-5
V GS , GATE TO SOURCE VOLTAGE (V)
Figure 5. Transfer Characteristics
-6
V DS = V
1.1
I
D
GS
= -250µA
1
0.9
0.8
0.7
0.6
-50
-25
0
25
50
75
100
T J , JUNCTION TEMPERATURE (°C)
125
150
Figure 6. Gate Threshold Variation
with Temperature
NDC652P Rev. D1
Typical Electrical Characteristics (continued)
10
I D = -250µA
5
1.08
-I S , REVERSE DRAIN CURRENT (A)
BV DSS , NORMALIZED
DRAIN-SOURCE BREAKDOWN VOLTAGE
1.1
1.06
1.04
1.02
1
0.98
0.96
0.94
-50
-25
0
25
50
75
100
T J , JUNCTION TEMPERATURE (°C)
125
VG S = 0V
T J = 125°C
25°C
1
-55°C
0.1
0.01
0.001
0.2
150
0.4
0.6
0.8
1
-V SD , BODY DIODE FORWARD VOLTAGE (V)
Figure 8. Body Diode Forward Voltage Variation with
Source Current and Temperature
Figure 7. Breakdown Voltage Variation
with Temperature
1000
10
V DS = -5V
-V GS , GATE-SOURCE VOLTAGE (V)
I D = -2.4A
CAPACITANCE (pF)
500
C iss
C oss
200
100
f = 1 MHz
C rss
V GS = 0 V
50
0.1
0.2
-V
0.5
1
2
5
10
, DRAIN TO SOURCE VOLTAGE (V)
30
-15V
8
-10V
6
4
2
0
0
2
4
8
10
12
Figure 10. Gate Charge Characteristics
t on
-VDD
t d(on)
t off
tr
RL
V IN
6
Q g , GATE CHARGE (nC)
DS
Figure 9. Capacitance Characteristics
t d(off)
tf
90%
90%
V OUT
D
VGS
1.2
VOUT
R GEN
10%
10%
DUT
G
90%
S
V IN
50%
50%
10%
PULSE WIDTH
Figure 11. Switching Test Circuit
INVERTED
Figure 12. Switching Waveforms
NDC652P Rev. D1
Typical Electrical and ThermalCharacteristics (continued)
2
STEADY-STATE POWER DISSIPATION (W)
V DS = -10V
TJ = -55°C
6
25°C
4
125°C
2
g
FS
, TRANSCONDUCTANCE (SIEMENS)
8
0
0
-2
-4
-6
-8
1a
1.5
1
1b
1c
0.5
4.5"x5" FR-4 Board
o
TA = 2 5 C
Still Air
0
0
-10
0.2
0.4
0.6
0.8
2oz COPPER MOUNTING PAD AREA (in 2 )
I D , DRAIN CURRENT (A)
Figure 14. SOT-6 Maximum Steady-State Power
Dissipation versus Copper Mounting Pad Area.
Figure 13. Transconductance Variation with Drain
Current and Temperature
3
30
10
2.5
1a
-I D, DRAIN CURRENT (A)
-I D , STEADY-STATE DRAIN CURRENT (A)
1
2
1b
1c
1.5
4.5"x5" FR-4 Board
3
RD
VG S = - 4 . 5 V
1
0
0.2
0.4
0.6
0.8
2oz COPPER MOUNTING PAD AREA (in 2 )
1
Figure 15. Maximum Steady-State Drain Current
versus Copper Mounting Pad Area.
IT
10
10
0u
s
1m
s
10
ms
0m
s
1s
0.3
V
0.1
GS
DC
= -4.5V
SINGLE PULSE
R θJ A = See Note 1c
0.03
Still Air
O
IM
1
o
TA = 2 5 C
S(
L
N)
T A = 25°C
0.01
0.1
0.2
0.5
1
2
5
10
-VDS , DRAIN-SOURCE VOLTAGE (V)
30
50
Figure 16. Maximum Safe Operating Area
r(t), NORMALIZED EFFECTIVE
TRANSIENT THERMAL RESISTANCE
1
0.5
0.2
0.1
0.05
D = 0.5
R θJA (t) = r(t) * R θJA
R JA = See Note 1c
θ
0.2
0.1
P(pk)
0.05
t1
0.02
0.02
0.01
0.01
t2
TJ - T
=P *R
(t)
θJA
Duty Cycle, D = t 1 / t 2
A
Single Pulse
0.005
0.00001
0.0001
0.001
0.01
0.1
t 1 , TIME (sec)
1
10
100
300
Figure 17. Transient Thermal Response Curve.
Note:
Thermal characterization performed using the conditions described in note 1c. Transient thermal response will change
depending on the circuit board design.
NDC652P Rev. D1
SuperSOTTM-6 Tape and Reel Data and Package Dimensions
SSOT-6 Packaging
Configuration: Figur e 1.0
Packaging Description:
Customize Label
SSOT-6 parts are shipped in tape. The carrier tape is
made from a dissipative (carbon filled) polycarbonate
resin. The cover tape is a multilayer film (Heat Activated
Adhesive in nature) primarily composed of polyester film,
adhesive layer, sealant, and anti-static sprayed agent.
These reeled parts in standard option are shipped with
3,000 units per 7" or 177cm diameter reel. The reels are
dark blue in color and is made of polystyrene plastic (antistatic coated). Other option comes in 10,000 units per 13"
or 330cm diameter reel. This and some other options are
described in the Packaging Information table.
Anti static Cover Tape
These full reels are individually barcode labeled and
placed inside a pizza box (illustrated in figure 1.0) made of
recyclable corrugated brown paper with a Fairchild logo
printing. One pizza box contains three reels maximum.
And these pizza boxes are placed inside a barcode
labeled shipping box which comes in different sizes
depending on the number of parts shipped.
F63TNR
Label
Embossed
Carrier Tape
631
631
631
631
631
SSOT-6 Packaging Information
Packaging Option
Standard
(no f l ow c ode )
Pin 1
D87Z
SSOT-6 Unit Orientation
Packaging type
TNR
TNR
Qty per Reel/Tube/Bag
3,000
10,000
Reel Size
7" Dia
13"
184x187x47
343x343x64
Max qty per Box
9,000
30,000
Weight per unit (gm)
0.0158
0.0158
Weight per Reel (kg)
0.1440
0.4700
Box Dimension (mm)
343mm x 342mm x 64mm
Intermediate box fo r D87Z Option
F63TNR Label
Note/Comments
F63TNR
Label
F63TNR Label sa mpl e
184mm x 187mm x 47mm
Pizza Box fo r Standar d Opti on
F63TNR
Label
LOT: CBVK741B019
QTY: 3000
FSID: FDC633N
SPEC:
D/C1: D9842
D/C2:
SSOT-6 Tape Leader and Trailer
Configuration: Figur e 2.0
QTY1:
QTY2:
SPEC REV:
CPN:
N/F: F
(F63TNR)3
Carrier Tape
Cover Tape
1998 Fairchild Semiconductor Corporation
Comp onent s
Traile r Tape
300mm mi nimum or
75 empty poc kets
Lead er Tape
500mm mi nimum or
125 emp ty poc kets
August 1999, Rev. C
SuperSOTTM-6 Tape and Reel Data and Package Dimensions, continued
SSOT-6 Embossed Carrier Tape
Configuration: Figure 3.0
P0
D0
T
E1
F
K0
Wc
W
E2
B0
Tc
A0
D1
P1
User Direction of Feed
Dimensions are in millimeter
Pkg type
A0
B0
SSOT-6
(8mm)
3.23
+/-0.10
3.18
+/-0.10
W
8.0
+/-0.3
D0
D1
E1
E2
1.55
+/-0.05
1.125
+/-0.125
1.75
+/-0.10
F
6.25
min
3.50
+/-0.05
P1
P0
4.0
+/-0.1
4.0
+/-0.1
K0
T
1.37
+/-0.10
0.255
+/-0.150
Notes: A0, B0, and K0 dimensions are determined with respect to the EIA/Jedec RS-481
rotational and lateral movement requirements (see sketches A, B, and C).
Wc
0.06
+/-0.02
0.5mm
maximum
20 deg maximum
Typical
component
cavity
center line
B0
5.2
+/-0.3
Tc
0.5mm
maximum
20 deg maximum component rotation
Typical
component
center line
Sketch A (Side or Front Sectional View)
A0
Component Rotation
Sketch C (Top View)
Component lateral movement
Sketch B (Top View)
SSOT-6 Reel Configuration: Figure 4.0
Component Rotation
W1 Measured at Hub
Dim A
Max
Dim A
max
See detail AA
Dim N
7" Diameter Option
B Min
Dim C
See detail AA
W3
13" Diameter Option
Dim D
min
W2 max Measured at Hub
DETAIL AA
Dimensions are in inches and millimeters
Tape Size
Reel
Option
Dim A
Dim B
0.059
1.5
512 +0.020/-0.008
13 +0.5/-0.2
0.795
20.2
2.165
55
0.331 +0.059/-0.000
8.4 +1.5/0
0.567
14.4
0.311 – 0.429
7.9 – 10.9
0.059
1.5
512 +0.020/-0.008
13 +0.5/-0.2
0.795
20.2
4.00
100
0.331 +0.059/-0.000
8.4 +1.5/0
0.567
14.4
0.311 – 0.429
7.9 – 10.9
8mm
7" Dia
7.00
177.8
8mm
13" Dia
13.00
330
Dim C
Dim D
Dim N
Dim W1
Dim W2
Dim W3 (LSL-USL)
July 1999, Rev. C
SuperSOTTM-6 Tape and Reel Data and Package Dimensions, continued
SuperSOT -6 (FS PKG Code 31, 33)
1:1
Scale 1:1 on letter size paper
Dimensions shown below are in:
inches [millimeters]
Part Weight per unit (gram): 0.0158
1998 Fairchild Semiconductor Corporation
September 1998, Rev. A
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PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
Advance Information
Formative or
In Design
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
Preliminary
First Production
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
No Identification Needed
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This datasheet contains final specifications. Fairchild
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that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
Rev. D