SMD Type Product specification NDS356P General Description Features -1.1 A, -20V. RDS(ON) = 0.3Ω @ VGS = -4.5V. These P-Channel logic level enhancement mode power field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. These devices are particularly suited for low voltage applications such as notebook computer power management, portable electronics, and other battery powered circuits where fast high-side switching, and low in-line power loss are needed in a very small outline surface mount package. Proprietary package design using copper lead frame for superior thermal and electrical capabilities. High density cell design for extremely low RDS(ON). Exceptional on-resistance and maximum DC current capability. Compact industry standard SOT-23 surface mount package. _______________________________________________________________________________ D S G Absolute Maximum Ratings T A = 25°C unless otherwise noted Symbol Parameter NDS356P Units VDSS Drain-Source Voltage -20 V VGSS Gate-Source Voltage - Continuous ± 12 V ID Maximum Drain Current ±1.1 A - Continuous (Note 1a) - Pulsed PD TJ,TSTG Maximum Power Dissipation ±10 (Note 1a) 0.5 (Note 1b) 0.46 Operating and Storage Temperature Range W -55 to 150 °C 250 °C/W 75 °C/W THERMAL CHARACTERISTICS RθJA Thermal Resistance, Junction-to-Ambient RθJC Thermal Resistance, Junction-to-Case (Note 1a) http://www.twtysemi.com (Note 1) [email protected] 4008-318-123 1 of 3 SMD Type Product specification NDS356P Electrical Characteristics (TA = 25°C unless otherwise noted) Symbol Parameter Conditions Min -20 Typ Max Units OFF CHARACTERISTICS BVDSS Drain-Source Breakdown Voltage VGS = 0 V, ID = -250 µA IDSS Zero Gate Voltage Drain Current VDS = -16 V, VGS = 0 V V TJ =125°C -5 µA -20 µA IGSSF Gate - Body Leakage, Forward VGS = 12 V, VDS = 0 V 100 nA IGSSR Gate - Body Leakage, Reverse VGS = -12 V, VDS = 0 V -100 nA V ON CHARACTERISTICS (Note 2) VGS(th) Gate Threshold Voltage VDS = VGS, ID = -250 µA TJ =125°C RDS(ON) Static Drain-Source On-Resistance -0.8 -1.6 -2.5 -0.5 -1.3 -2.2 0.3 VGS = -4.5 V, ID = -1.1 A Ω 0.4 TJ =125°C 0.21 VGS = -10 V, ID = -1.3 A ID(ON) On-State Drain Current VGS = -4.5 V, VDS = -5 V -3 gFS Forward Transconductance VDS = -5 V, ID = -1.1 A 1.8 A S VDS = -10 V, VGS = 0 V, f = 1.0 MHz 180 pF 255 pF 60 pF DYNAMIC CHARACTERISTICS Ciss Input Capacitance Coss Output Capacitance Crss Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Note 2) td(on) Turn - On Delay Time tr Turn - On Rise Time td(off) tf 7 15 ns 17 30 ns Turn - Off Delay Time 56 90 ns Turn - Off Fall Time 41 80 ns Qg Total Gate Charge Qgs Gate-Source Charge Qgd Gate-Drain Charge http://www.twtysemi.com VDD = -10 V, ID = -1 A, VGS = -10 V, RGEN = 50 Ω VDS = -10 V, ID = -1.1 A, VGS = -5 V [email protected] 3.5 4008-318-123 5 nC 1.5 nC 2 nC 2 of 3 SMD Type Product specification NDS356P Electrical Characteristics (TA = 25°C unless otherwise noted) Symbol Parameter Conditions Min Typ Max Units -0.6 A -4 A -1.2 V DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS IS Maximum Continuous Drain-Source Diode Forward Current ISM Maximum Pulsed Drain-Source Diode Forward Current VSD Drain-Source Diode Forward Voltage VGS = 0 V, IS = -1.1 A (Note 2) -0.85 Notes: 1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RθJC is guaranteed by design while RθCA is determined by the user's board design. PD(t ) = T J−TA R θJ A(t ) = T J−TA R θJ C+RθCA(t ) = I 2D (t ) × RDS (ON ) TJ Typical RθJA using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment: a. 250oC/W when mounted on a 0.02 in2 pad of 2oz cpper. b. 270oC/W when mounted on a 0.001 in2 pad of 2oz cpper. 1a 1b Scale 1 : 1 on letter size paper 2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%. http://www.twtysemi.com [email protected] 4008-318-123 3 of 3