ONSEMI 2N7002ET1G

2N7002E
Small Signal MOSFET
60 V, 310 mA, Single, N−Channel, SOT−23
Features
•
•
•
•
Low RDS(on)
Small Footprint Surface Mount Package
Trench Technology
This is a Pb−Free Device
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V(BR)DSS
RDS(on) MAX
ID MAX
(Note 1)
60 V
3.0 W @ 4.5 V
310 mA
Applications
•
•
•
•
2.5 W @ 10 V
Low Side Load Switch
Level Shift Circuits
DC−DC Converter
Portable Applications i.e. DSC, PDA, Cell Phone, etc.
Simplified Schematic
N−Channel
3
MAXIMUM RATINGS (TJ = 25°C unless otherwise stated)
Symbol
Value
Unit
Drain−to−Source Voltage
VDSS
60
V
Gate−to−Source Voltage
VGS
±20
V
Rating
Drain Current (Note 1)
Steady State
t<5s
TA = 25°C
TA = 85°C
ID
TA = 25°C
TA = 85°C
1
mA
260
190
2
(Top View)
310
220
Power Dissipation (Note 1)
Steady State
t<5s
PD
mW
Pulsed Drain Current (tp = 10 ms)
IDM
1.2
A
Operating Junction and Storage
Temperature Range
TJ, TSTG
−55 to
+150
°C
Source Current (Body Diode)
IS
300
mA
Lead Temperature for Soldering Purposes
(1/8″ from case for 10 s)
TL
260
°C
300
420
3
Characteristic
3
2
SOT−23
CASE 318
STYLE 21
Max
Unit
Junction−to−Ambient − Steady State
(Note 1)
RqJA
417
°C/W
Junction−to−Ambient − t ≤ 5 s (Note 1)
RqJA
300
1. Surface−mounted on FR4 board using 1 in sq pad size (Cu area = 1.127 in
sq [1 oz] including traces)
April, 2007 − Rev. 1
703
W
703 W
1
2
Gate
Source
= Device Code
= Work Week
ORDERING INFORMATION
Symbol
© Semiconductor Components Industries, LLC, 2007
Drain
1
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
THERMAL CHARACTERISTICS
MARKING DIAGRAM
& PIN ASSIGNMENT
1
Device
2N7002ET1G
Package
Shipping †
SOT−23
(Pb−Free)
3000/Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
Publication Order Number:
2N7002E/D
2N7002E
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified)
Symbol
Test Condition
Min
Drain−to−Source Breakdown Voltage
V(BR)DSS
VGS = 0 V, ID = 250 mA
60
Drain−to−Source Breakdown Voltage
Temperature Coefficient
V(BR)DSS/TJ
Parameter
Typ
Max
Units
OFF CHARACTERISTICS
Zero Gate Voltage Drain Current
Gate−to−Source Leakage Current
IDSS
V
75
VGS = 0 V,
VDS = 60 V
mV/°C
TJ = 25°C
1
TJ = 125°C
500
IGSS
VDS = 0 V, VGS = ±20 V
VGS(TH)
VGS = VDS, ID = 250 mA
mA
±100
nA
2.5
V
ON CHARACTERISTICS (Note 2)
Gate Threshold Voltage
Negative Threshold Temperature
Coefficient
VGS(TH)/TJ
Drain−to−Source On Resistance
RDS(on)
Forward Transconductance
gFS
1.0
4.4
mV/°C
VGS = 10 V, ID = 240 mA
0.86
2.5
VGS = 4.5 V, ID = 50 mA
1.1
3.0
VDS = 5 V, ID = 200 mA
80
S
26.7
pF
W
CHARGES AND CAPACITANCES
Input Capacitance
CISS
Output Capacitance
COSS
Reverse Transfer Capacitance
CRSS
VGS = 0 V, f = 1 MHz,
VDS = 25 V
4.6
2.9
Total Gate Charge
QG(TOT)
0.81
Threshold Gate Charge
QG(TH)
0.31
Gate−to−Source Charge
QGS
Gate−to−Drain Charge
QGD
VGS = 5 V, VDS = 10 V;
ID = 240 mA
nC
0.48
0.08
SWITCHING CHARACTERISTICS, VGS = V (Note 3)
Turn−On Delay Time
td(ON)
Rise Time
Turn−Off Delay Time
tr
td(OFF)
Fall Time
ns
1.7
VGS = 10 V, VDD = 30 V,
ID = 200 mA, RG = 10 W
tf
1.2
4.8
3.6
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
VSD
VGS = 0 V,
IS = 200 mA
2. Pulse Test: pulse width ≤ 300 ms, duty cycle ≤ 2%
3. Switching characteristics are independent of operating junction temperatures
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2
TJ = 25°C
0.79
TJ = 85°C
0.7
1.2
V
2N7002E
TYPICAL CHARACTERISTICS
4.0 V
3.5 V
0.8
3.0 V
0.4
2.5 V
2.0 V
0
2
4
6
0
TJ = −55°C
2
4
6
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
TJ = 125°C
2.0
TJ = 85°C
1.6
TJ = 25°C
1.2
TJ = −55°C
0.8
0.4
0.2
0.4
0.6
0.8
1.0
1.2
2.4
VGS = 10 V
2.0
TJ = 125°C
1.6
TJ = 85°C
1.2
TJ = 25°C
0.8
TJ = −55°C
0.4
0
0
0.2
0.4
0.6
0.8
1.0
1.2
ID, DRAIN CURRENT (A)
ID, DRAIN CURRENT (A)
Figure 3. On−Resistance vs. Drain Current and
Temperature
Figure 4. On−Resistance vs. Drain Current and
Temperature
1.6
2.2
ID = 250 mA
1.2
ID = 75 mA
0.8
0.4
TJ = 125°C
VGS, GATE−TO−SOURCE VOLTAGE (V)
VGS = 4.5 V
0
TJ = 25°C
0.4
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
2.4
0
0.8
0
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
ID, DRAIN CURRENT (A)
1.2
0
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
4.5 V
9.0 V
8.0 V
7.0 V
6.0 V
1.6
1.2
5.0 V
VGS = 10 V
RDS(on), DRAIN−TO−SOURCE
RESISTANCE (NORMALIZED)
ID, DRAIN CURRENT (A)
2.0
2
4
6
8
ID = 0.2 A
1.8
VGS = 10 V
1.4
1.0
0.6
−50
10
VGS = 4.5 V
−25
0
25
50
75
100
125
VGS, GATE−TO−SOURCE VOLTAGE (V)
TJ, JUNCTION TEMPERATURE (°C)
Figure 5. On−Resistance vs. Gate−to−Source
Voltage
Figure 6. On−Resistance Variation with
Temperature
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3
150
2N7002E
TYPICAL CHARACTERISTICS
30
VGS, GATE−TO−SOURCE VOLTAGE (V)
TJ = 25°C
VGS = 0 V
Ciss
20
Coss
10
0
Crss
0
4
8
12
16
20
5
TJ = 25°C
ID = 0.25 A
4
3
2
1
0
0
0.2
0.4
0.6
0.8
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (V)
Qg, TOTAL GATE CHARGE (nC)
Figure 7. Capacitance Variation
Figure 8. Gate−to−Source and
Drain−to−Source Voltage vs. Total Charge
10
VGS = 0 V
IS, SOURCE CURRENT (A)
C, CAPACITANCE (pF)
40
1
TJ = 85°C
TJ = 25°C
0.1
0.01
0.2
0.4
0.6
0.8
1.0
VSD, SOURCE−TO−DRAIN VOLTAGE (V)
Figure 9. Diode Forward Voltage vs. Current
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4
1.2
1
2N7002E
PACKAGE DIMENSIONS
SOT−23 (TO−236)
CASE 318−08
ISSUE AH
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. MAXIMUM LEAD THICKNESS INCLUDES
LEAD FINISH THICKNESS. MINIMUM
LEAD THICKNESS IS THE MINIMUM
THICKNESS OF BASE MATERIAL.
4. 318−03 AND −07 OBSOLETE, NEW
STANDARD 318−08.
A
L
3
1
V
B S
2
G
DIM
A
B
C
D
G
H
J
K
L
S
V
C
D
H
J
K
INCHES
MIN
MAX
0.1102 0.1197
0.0472 0.0551
0.0350 0.0440
0.0150 0.0200
0.0701 0.0807
0.0005 0.0040
0.0034 0.0070
0.0140 0.0285
0.0350 0.0401
0.0830 0.1039
0.0177 0.0236
MILLIMETERS
MIN
MAX
2.80
3.04
1.20
1.40
0.89
1.11
0.37
0.50
1.78
2.04
0.013 0.100
0.085 0.177
0.35
0.69
0.89
1.02
2.10
2.64
0.45
0.60
STYLE 21:
PIN 1. GATE
2. SOURCE
3. DRAIN
SOLDERING FOOTPRINT*
0.95
0.037
0.95
0.037
2.0
0.079
0.9
0.035
0.8
0.031
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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5
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2N7002E/D