ONSEMI NTP13N10

NTP13N10
Preferred Device
Power MOSFET
13 A, 100 V, N−Channel
Enhancement−Mode TO−220
Features
• Source−to−Drain Diode Recovery Time Comparable to a Discrete
•
•
•
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Fast Recovery Diode
Avalanche Energy Specified
IDSS and RDS(on) Specified at Elevated Temperature
Pb−Free Package is Available
VDSS
RDS(ON) TYP
ID MAX
100 V
165 mΩ @ 10 V
13 A
Typical Applications
N−Channel
• PWM Motor Controls
• Power Supplies
• Converters
D
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
G
Symbol
Value
Unit
Drain−to−Source Voltage
VDSS
100
Vdc
Drain−to−Source Voltage (RGS = 1.0 MΩ)
VDGR
100
Vdc
Rating
Gate−to−Source Voltage
− Continuous
− Non−Repetitive (tpv10 ms)
Drain Current
− Continuous @ TA 25°C
− Continuous @ TA 100°C
− Pulsed (Note 1)
Total Power Dissipation @ TA = 25°C
Derate above 25°C
Operating and Storage Temperature Range
Single Drain−to−Source Avalanche Energy −
Starting TJ = 25°C
(VDD = 50 Vdc, VGS = 10 Vdc,
IL(pk) = 13 A, L = 1.0 mH, RG = 25 Ω)
Thermal Resistance
− Junction−to−Case
Maximum Lead Temperature for Soldering
Purposes, 1/8″ from case for 10 seconds
VGS
VGSM
"20
"30
ID
ID
13
8.0
39
PD
64.7
0.43
W
W/°C
TJ, Tstg
−55 to
+175
°C
Adc
IDM
EAS
mJ
4
Drain
4
TO−220AB
CASE 221A
STYLE 5
1
2
13N10
AYWW
1
Gate
3
RθJC
2.32
TL
260
°C/W
°C
1
3
Source
2
Drain
85
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
August, 2006 − Rev. 6
MARKING DIAGRAM
& PIN ASSIGNMENT
Vdc
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Pulse Test: Pulse Width = 10 ms, Duty Cycle = 2%.
© Semiconductor Components Industries, LLC, 2006
S
13N10
A
Y
WW
= Device Code
= Assembly Location
= Year
= Work Week
ORDERING INFORMATION
Package
Shipping†
NTP13N10
TO−220AB
50 Units/Rail
NTP13N10G
TO−220AB
(Pb−Free)
50 Units/Rail
Device
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Preferred devices are recommended choices for future use
and best overall value.
Publication Order Number:
NTP13N10/D
NTP13N10
ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted)
Characteristic
Symbol
Min
Typ
Max
Unit
100
−
−
147
−
−
−
−
−
−
5.0
50
−
−
± 100
2.0
−
3.2
−7.6
4.0
−
−
−
0.130
0.250
0.165
0.400
−
1.82
2.34
gFS
−
6.0
−
mhos
Ciss
−
390
550
pF
Coss
−
115
160
Crss
−
35
70
td(on)
−
11
20
tr
−
40
80
td(off)
−
20
40
OFF CHARACTERISTICS
V(BR)DSS
Drain−to−Source Breakdown Voltage
(VGS = 0 Vdc, ID = 250 mAdc)
Temperature Coefficient (Positive)
Zero Gate Voltage Collector Current
(VGS = 0 Vdc, VDS = 100 Vdc, TJ = 25°C)
(VGS = 0 Vdc, VDS = 100 Vdc, TJ = 125°C)
IDSS
Gate−Body Leakage Current (VGS = ± 20 Vdc, VDS = 0)
IGSS
Vdc
mV/°C
mAdc
nAdc
ON CHARACTERISTICS
Gate Threshold Voltage
VDS = VGS, ID = 250 mAdc)
Temperature Coefficient (Negative)
VGS(th)
Static Drain−to−Source On−State Resistance
(VGS = 10 Vdc, ID = 6.5 Adc)
(VGS = 10 Vdc, ID = 6.5 Adc, TJ = 125°C)
RDS(on)
Drain−to−Source On−Voltage
(VGS = 10 Vdc, ID = 13 Adc)
VDS(on)
Forward Transconductance (VDS = 15 Vdc, ID = 6.5 Adc)
Vdc
mV/°C
Ω
Vdc
DYNAMIC CHARACTERISTICS
Input Capacitance
(VDS = 25 Vdc, VGS = 0 Vdc,
f = 1.0 MHz)
Output Capacitance
Reverse Transfer Capacitance
SWITCHING CHARACTERISTICS (Notes 2 & 3)
Turn−On Delay Time
Rise Time
(VDD = 80 Vdc, ID = 13 Adc,
VGS = 10 Vdc, RG = 9.1 Ω)
Turn−Off Delay Time
Fall Time
Gate Charge
(VDS = 80 Vdc, ID = 13 Adc,
VGS = 10 Vdc)
ns
tf
−
36
70
Qtot
−
14
20
Qgs
−
3.0
−
Qgd
−
7.0
−
VSD
−
−
0.98
0.88
1.3
−
Vdc
trr
−
85
−
ns
ta
−
60
−
tb
−
28
−
QRR
−
0.3
−
nC
BODY−DRAIN DIODE RATINGS (Note 2)
Forward On−Voltage
(IS = 13 Adc, VGS = 0 Vdc)
(IS = 13 Adc, VGS = 0 Vdc, TJ = 125°C)
Reverse Recovery Time
(IS = 13 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/ms)
Reverse Recovery Stored Charge
2. Pulse Test: Pulse Width = 300 ms max, Duty Cycle = 2%.
3. Switching characteristics are independent of operating junction temperature.
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2
mC
26
24
22
20
18
16
14
12
10
8
6
4
2
0
VGS = 10 V
TJ = 25°C
9V
8V
7V
ID, DRAIN CURRENT (AMPS)
ID, DRAIN CURRENT (AMPS)
NTP13N10
6.5 V
7.5 V
6V
5.5 V
5V
4.5 V
8
9
1
2
3
4
5
6
7
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
0
10
26
24
22
20
18
16
14
12
10
8
6
4
2
0
VDS ≥ 10 V
TJ = 25°C
TJ = 100°C
0
VGS = 10 V
0.4
0.2
TJ = 25°C
0.175
0.3
TJ = 100°C
0.2
TJ = 25°C
0
2
4
VGS = 10 V
0.15
VGS = 15 V
0.125
TJ = −55°C
0.1
0
6 8 10 12 14 16 18 20 22 24
ID, DRAIN CURRENT (AMPS)
26
0.1
0
2
4
6 8 10 12 14 16 18 20 22 24 26
ID, DRAIN CURRENT (AMPS)
Figure 4. On−Resistance versus Drain Current
and Gate Voltage
3
10,000
VGS = 0 V
ID = 6.5 A
VGS = 10 V
IDSS, LEAKAGE (nA)
RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED)
Figure 3. On−Resistance versus Drain Current
and Temperature
2.5
10
Figure 2. Transfer Characteristics
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
Figure 1. On−Region Characteristics
0.5
TJ = −55°C
1
2
3
4
5
6
7
8
9
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
2
1.5
1
TJ = 150°C
1000
100
0.5
TJ = 100°C
0
−50 −25
0
25
50
75 100 125 150
TJ, JUNCTION TEMPERATURE (°C)
10
175
20
Figure 5. On−Resistance Variation with
Temperature
30
60
70
80
90 100
40
50
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 6. Drain−to−Source Leakage Current
versus Voltage
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3
NTP13N10
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (Δt)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The published capacitance data is difficult to use for
calculating rise and fall because drain−gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (IG(AV)) can be made from a
rudimentary analysis of the drive circuit so that
t = Q/IG(AV)
The capacitance (Ciss) is read from the capacitance curve at
a voltage corresponding to the off−state condition when
calculating td(on) and is read at a voltage corresponding to the
on−state when calculating td(off).
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load. Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.
During the rise and fall time interval when switching a
resistive load, VGS remains virtually constant at a level
known as the plateau voltage, VSGP. Therefore, rise and fall
times may be approximated by the following:
tr = Q2 x RG/(VGG − VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turn−on and turn−off delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG − VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
C, CAPACITANCE (pF)
1000
VDS = 0 V
VGS = 0 V
TJ = 25°C
Ciss
800
600
Crss
Ciss
400
200
Coss
0
10
Crss
5
0
VGS
5
10
15
20
25
VDS
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE
(VOLTS)
Figure 7. Capacitance Variation
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4
100
90
QT
16
80
VDS
14
70
60
12
10
50
VGS
8
6
40
Q2
Q1
30
4
ID = 13 A
TJ = 25°C
2
0
0
2
4
6
8
10
QG, TOTAL GATE CHARGE (nC)
12
20
10
0
14
1000
VDD = 80 V
ID = 13 A
VGS = 10 V
100
t, TIME (ns)
20
18
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
NTP13N10
tr
tf
td(off)
10
1
td(on)
1
Figure 8. Gate−To−Source and Drain−To−Source
Voltage versus Total Charge
10
RG, GATE RESISTANCE (Ω)
100
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
DRAIN−TO−SOURCE DIODE CHARACTERISTICS
IS, SOURCE CURRENT (AMPS)
12
VGS = 0 V
TJ = 25°C
10
8
6
4
2
0
0.4
0.5
0.6
0.7
0.8
0.9
1
VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
Figure 10. Diode Forward Voltage versus Current
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain−to−source voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
junction temperature and a case temperature (TC) of 25°C.
Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the procedures
discussed
in
AN569,
“Transient
Thermal
Resistance−General Data and Its Use.”
Switching between the off−state and the on−state may
traverse any load line provided neither rated peak current
(IDM) nor rated voltage (VDSS) is exceeded and the
transition time (tr,tf) do not exceed 10 μs. In addition the total
power averaged over a complete switching cycle must not
exceed (TJ(MAX) − TC)/(RθJC).
A Power MOSFET designated E−FET can be safely used
in switching circuits with unclamped inductive loads. For
reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and adjusted for operating conditions
differing from those specified. Although industry practice is
to rate in terms of energy, avalanche energy capability is not
a constant. The energy rating decreases non−linearly with an
increase of peak current in avalanche and peak junction
temperature.
Although many E−FETs can withstand the stress of
drain−to−source avalanche at currents up to rated pulsed
current (IDM), the energy rating is specified at rated
continuous current (ID), in accordance with industry custom.
The energy rating must be derated for temperature as shown
in the accompanying graph (Figure 12). Maximum energy at
currents below rated continuous ID can safely be assumed to
equal the values indicated.
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5
NTP13N10
ID, DRAIN CURRENT (AMPS)
100
VGS = 20 V
SINGLE PULSE
TC = 25°C
10
10 μs
100 μs
1 ms
1
10 ms
dc
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
0.1
0.1
10
1
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
100
EAS, SINGLE PULSE DRAIN−TO−SOURCE
AVALANCHE ENERGY (mJ)
SAFE OPERATING AREA
100
ID = 13 A
80
60
40
20
0
25
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
r(t), EFFECTIVE TRANSIENT THERMAL
RESISTANCE (NORMALIZED)
50
75
100
125
150
175
TJ, STARTING JUNCTION TEMPERATURE (°C)
Figure 12. Maximum Avalanche Energy versus
Starting Junction Temperature
1
D = 0.5
0.2
P(pk)
0.1
0.05
t1
0.01
t2
DUTY CYCLE, D = t1/t2
SINGLE PULSE
0.1
0.0001
0.01
0.001
RθJC(t) = r(t) RθJC
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) − TC = P(pk) RθJC(t)
0.1
1
t, TIME (s)
Figure 13. Thermal Response
di/dt
IS
trr
ta
tb
TIME
0.25 IS
tp
IS
Figure 14. Diode Reverse Recovery Waveform
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6
10
NTP13N10
PACKAGE DIMENSIONS
TO−220 THREE−LEAD
TO−220AB
CASE 221A−09
ISSUE AA
SEATING
PLANE
−T−
B
F
T
C
S
4
DIM
A
B
C
D
F
G
H
J
K
L
N
Q
R
S
T
U
V
Z
A
Q
1 2 3
U
H
K
Z
L
R
V
J
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION Z DEFINES A ZONE WHERE ALL
BODY AND LEAD IRREGULARITIES ARE
ALLOWED.
G
D
N
INCHES
MIN
MAX
0.570
0.620
0.380
0.405
0.160
0.190
0.025
0.035
0.142
0.147
0.095
0.105
0.110
0.155
0.018
0.025
0.500
0.562
0.045
0.060
0.190
0.210
0.100
0.120
0.080
0.110
0.045
0.055
0.235
0.255
0.000
0.050
0.045
−−−
−−−
0.080
STYLE 5:
PIN 1.
2.
3.
4.
MILLIMETERS
MIN
MAX
14.48
15.75
9.66
10.28
4.07
4.82
0.64
0.88
3.61
3.73
2.42
2.66
2.80
3.93
0.46
0.64
12.70
14.27
1.15
1.52
4.83
5.33
2.54
3.04
2.04
2.79
1.15
1.39
5.97
6.47
0.00
1.27
1.15
−−−
−−−
2.04
GATE
DRAIN
SOURCE
DRAIN
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
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NTP13N10/D