PACE1754 SINGLE CHIP, 40MHz CMOS PROCESSOR INTERFACE CIRCUIT (PIC) FEATURES The PACE1754 (PIC) is a support chip for the PACE1750A/AE Processor. It eliminates the SSI/ MSI Logic and external system functions required in typical 1750A implementations. Provides a significant savings in part-count and power dissipation enhancing reliability and overall system speed performance. Provides an optimal interface when used with the PACE1753 MMU/COMBO in a full 1750A implementation. Provides the following additional important system functions: — Programmable READY for memory and I/O — Automatic READY during self-test and internal I/O instructions — 100KHz timer clock output provided — Programmable system watchdog—ranges from 1 µs to 1 minute — Programmable Bus time-out function — Memory Parity generation/detection — Error detection of unimplemented memory and/or I/O space addressing — First failing memory address register for diagnostics — High drive three-state address latches — Built-in system test program—automatically tests the PACE1750A/AE CPU, PACE1753 MMU/COMBO, PACE1754 PIC and system address lines as well as memory and I/O strobes — System configuration decoding and buffering — Interrupt acknowledge decoder and strobe — Start up ROM support per MIL-STD-1750A — Memory or I/O READ/WRITE three-state strobes with external three-state control for DMA applications 20, 30 and 40 MHz operation over full Military Temperature Range Single 5V ± 10% Power Supply Power Dissipation over Military Temperature Range < 0.25 watts at 20 MHz < 0.30 watts at 30 MHz < 0.35 watts at 40 MHz Available in: — 64-Pin DIP or Gull Wing (50 Mil Pin centers) — 68-Pin Pin Grid Array (PGA) (100 Mil centers) — 68-Lead Quad Pack PACE1754 PROCESSOR INTERFACE CIRCUIT DESCRIPTION The PACE1754 Processor Interface Circuit (PIC) is a single chip implementation of many special system functions that are often required when using the PACE1750A/AE, single chip, 40MHz CMOS Microprocessor. The PIC allows a system designer to design a higher performance, more effecient microprocessor system which uses less power and takes up less board space than was previously possible. In addition to providing significant savings in part count and power dissipation the PIC uses only a 5V ±10%, single supply and operates at 20, 30 and 40 MHz over the fully Military Temperature Range. The PIC provides many important system functions. These functions are governed by respective bit positions in a programmable Control Register which is incorporated in the PIC. The individual bits of the control register are set to select the various features and are set to a specified default value upon Reset. Document # MICRO-5 REV C Revised November 2005 PACE1754 ABSOLUTE MAXIMUM RATINGS1 Supply Voltage Range 0.5V to +7.0V Input Voltage Range 0.5V to VCC + 0.5V Storage Temperature Range –65°C to +150°C Input Current Range –30mA to +5mA Current applied to any output3 150mA Maximum Power Dissipation2 Lead Temperature Range (soldering 10 seconds) RECOMMENDED OPERATING CONDITIONS Case Temperature GND VCC –55°C to +125°C 0 4.5V to +5.5V 1.5W 300°C ):4 Thermal resistance (θJC Cases X and T Cases Y and U Case Z 8°C/W 5°C/W 6°C/W Notes: 1. Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. 2. Must withstand the added power dissipation due to short circuit test e.g., IOS. 3. Duration 1 second or less. 4. Device Type Definitions from 5962-88642 SMD: Case X: Dual In-Line Case T: Dual In-Line with Gull-Wing Leads Case Y: Leaded Chip Carrier with Gull-Wing Leads Case U: Leaded Chip Carrier with Unformed Leads Case Z: Pin Grid Array Document # MICRO-5 REV C Page 2 of 20 PACE1754 DC ELECTRICAL SPECIFICATIONS (Over recommended operating conditions) Symbol Parameter Min Max Unit Conditions1 VIH Input HIGH Voltage 2.0 VCC + 0.5 V VIL Input LOW Voltage –0.5 0.8 V VCD Input Clamp Diode Voltage –1.2 V VCC = 4.5V, IIN = –18mA VOH Output HIGH Voltage 2.4 V VCC = 4.5V, IOH = –8.0mA VCC – 0.2 V VIN = 0.8V, 2.0V IOH = –300µA VOL VOL IIH Output LOW Voltage, 0.5 V VCC = 4.5V, IOL = 8.0mA except A0 – A15 0.2 V VIN = 0.8V, 2.0V IOL = 300µA Output LOW Voltage, 0.5 V VCC = 4.5V, IOL = 20.0mA A0 – A15 0.2 V VIN = 0.8V, 2.0V IOL = 300µA 10 µA VIN = VCC, VCC = 5.5V Input HIGH Current, except IB0 – IB15, parity/IB16, SING ERR, A0/EXT AD0, A1/EXT AD1, STRBA IIH Input HIGH Current, IB0 – IB15, parity/IB16, A0/EXT AD0, A1/EXT AD1 50 µA IIH Input HIGH Current, STRBA, SING ERR 500 µA –10 µA IIL Input LOW Current, except IB0 – IB15, parity/IB16, SING ERR, A0/EXT AD0, A1/EXT AD1, STRBD, TEST ON VIN = VCC, VCC = 5.5V VIN = VCC, VCC = 5.5V VIN = GND, VCC = 5.5V IIL Input LOW Current, IB0 – IB15, parity/IB16, SING ERR, A0/EXT AD0, A1/EXT AD1 –50 µA IIL Input LOW Current, STRBD, TEST ON –500 µA VIN = GND, VCC = 5.5V IOZH Output Three-State Current 50 µA VOUT = 2.4V, VCC = 5.5V IOZL Output Three-State Current –50 µA VOUT = 0.5V, VCC = 5.5V ICCQC Quiescent Power Supply Current (CMOS Input Levels) 10 mA VIN < 0.2V or > VCC – 0.2V f = 0MHz, Outputs Open, VCC = 5.5V ICCQT Quiescent Power Supply Current (TTL Input Levels) 50 mA VIN = 3.4V, f = 0MHz, All Inputs, Outputs Open, VCC = 5.5V ICCD VIN = GND, VCC = 5.5V Dynamic Power f = 20MHz 40 mA VIN = 0V to VCC, Supply Current f = 30MHz 50 mA tr = tf = 2.5 ns typ., f = 40MHz 60 mA Outputs Open, VCC = 5.5V mA VOUT = GND, VCC = 5.5V Current2 IOS Output Short Circuit –25 CIN Input Capacitance 10 pF Inputs Only COUT Output/Bi-directional Capacitance 15 pF Outputs Only (Including I/O Buffers) Notes: 1. 4.5V ≤ VCC ≤ 5.5V, –55°C ≤ TC ≤ +125°C. Unless otherwise specified, testing shall be conducted at worst-case conditions. 2. Duration of the short should not exceed one second; only one output may be shorted at a time. Document # MICRO-5 REV C Page 3 of 20 PACE1754 AC ELECTRICAL CHARACTERISTICS1, 2 (VCC = 5V ± 10% Over Recommended Operating Conditions) 20 MHz Symbol Parameter Min Max 30MHz Min Max 40 MHz Min Max Unit tEX RDY (RDYD)V Time from External Ready to Ready Data Valid 16 14 12 ns tC (RDYD)V Time from Clock Read to Ready Data Valid 28 22 16 ns tSTRBAH (A)V Time from Strobe Address HIGH to Address Bus Valid 29 21 19 ns tIBAV (A)V Time from Information Bus Address to Address Bus Valid 31 22 20 ns tFC (R)L Time from Falling Clock to Read LOW 24 18 12 ns tSTRBDH (R)H Time from Strobe Data HIGH to Read HIGH 24 18 12 ns tSTRBDL (W)L Time from Strobe Data LOW to Write LOW 26 20 15 ns tSTRBDH (W)H Time from Strobe Data HIGH to Write HIGH 26 20 15 ns tIBDIN (ME PA ER)L Time from Information Bus Data into Memory Parity Error LOW 22 17 12 ns tIBAIN (EX AD ER) Time from Information Bus Address into External Address Error 30 25 20 ns tSTRBDL – (STRT ROM)V Time from Strobe Data LOW to Start-up ROM Valid 26 20 15 ns tFC (IB OUT)V Time from Falling Clock to Information Bus Valid 30 25 25 ns tC (TIMER CLK) Time from Rising Edge of Clock to Timer Clock 30 25 20 ns tIB INV (IB16) Time from Information Bus Data to Parity Valid 25 20 18 ns tEXT AD (CLKB3) Extended Address Setup Time tEX RDY1 (RDYD)V Time from External Ready Data to Ready Data Valid 28 24 21 ns tFC (SCR EN) Time from Falling Clock to SCR Enable; Case Types T and X only 30 24 24 ns tSTRBDH (SCR EN) Time from STRBD HIGH to SCR Enable; Case Types T and X only 30 24 24 ns 10 10 10 ns Notes: 1. 4.5V ≤ VCC ≤ 5.5V, –55°C ≤ TC ≤ +125°C. Unless otherwise specified, testing shall be conducted at worst-case conditions. 2. All measurements of delay times on active signals are related to the 1.5V levels. Document # MICRO-5 REV C Page 4 of 20 PACE1754 TERMINAL CONNECTIONS Case Outlines: Dual-In-Line (Case X) and Dual-In-Line with Gull-Wing Leads (Case T) Terminal Number Terminal Symbol Terminal Number Terminal Symbol Terminal Number Terminal Symbol 1 GND 23 IB13 45 A3 2 SCR EN 24 IB14 46 GND 3 TEST ON 25 IB15 47 A2 4 VCC 26 IB16 48 A1/EXT AD1 5 RESET 27 ME PA ER/RAM DIS 49 A0/EXT AD0 6 TEST END 28 EX AD ER/SING ERR 50 TC 7 TIMER CLK 29 INTA 51 CPU CLK 8 EX RDY 1 30 STRT ROM 52 STRBA 9 IB0 31 VCC 53 STRBD 10 IB1 32 GND 54 STRB EN 11 IB2 33 A15 55 EX RDY 12 IB3 34 A14 56 RDYD 13 IB4 35 A13 57 R/W 14 IB5 36 A12 58 GND 15 IB6 37 A11 59 M/IO 16 IB7 38 A10 60 MEMW 17 IB8 39 A9 61 MEMR 18 IB9 40 A8 62 IOW 19 GND 41 A7 63 IOR 20 IB10 42 A6 64 VCC 21 IB11 43 A5 22 IB12 44 A4 Document # MICRO-5 REV C Page 5 of 20 PACE1754 TERMINAL CONNECTIONS Case Outlines: Leaded Chip Carrier with unformed leads (Case U) and Leaded Chip Carrier with GullWing Leads (Case Y) Terminal Number Terminal Symbol 1 GND 2 Terminal Symbol Terminal Number 24 IB12 47 A3 SC0 25 IB13 48 GND 3 SC1 26 IB14 49 A2 4 TEST ON 27 IB15 50 A1/EXT AD1 5 RESET 28 PARITY/IB16 51 A0/EXT AD0 6 TEST END 29 ME PA ER/RAM DIS 52 SC4 7 TIMER CLK 30 EX AD ER/SING ERR 53 SC3 8 SC2 31 INTA 54 TC 9 VCC 32 STRT ROM 55 CPU CLK 10 IB0 33 VCC 56 STRBA 11 IB1 34 GND 57 STRBD 12 IB2 35 A15 58 STRB EN 13 IB3 36 A14 59 EX RDY 14 IB4 37 A13 60 RDYD 15 IB5 38 A12 61 R/W 16 IB6 39 A11 62 GND 17 IB7 40 A10 63 M/IO 18 EX RDY 1 41 A9 64 MEMW 19 IB8 42 A8 65 MEMR 20 IB9 43 A7 66 IOW 21 GND 44 A6 67 IOR 22 IB10 45 A5 68 VCC 23 IB11 46 A4 Document # MICRO-5 REV C Terminal Number Terminal Symbol Page 6 of 20 PACE1754 TERMINAL CONNECTIONS Case Outline: Pin Grid Array (Case Z) Terminal Number Terminal Symbol Terminal Number Terminal Symbol Terminal Number Terminal Symbol B1 VCC L5 SC1 D11 A3 B2 IB14 K5 SC0 D10 A4 C1 IB13 L6 VCC C11 A5 C2 IB12 K6 IOR C10 A6 D1 IB11 L7 IOW B11 A7 D2 IB10 K7 MEMR A10 GND E1 IB9 L8 MEMW B10 A8 E2 IB8 K8 M/IO A9 A9 F1 EX RDY 1 L9 GND B9 A10 F2 IB7 K9 R/W A8 A11 G1 IB6 L10 RDYD B8 A12 G2 IB5 K11 EX RDY A7 A13 H1 IB4 K10 STRB EN B7 A14 H2 IB3 J11 STRBD A6 A15 J1 IB2 J10 STRBA B6 GND J2 IB1 H11 CPU CLK A5 VCC K1 IB0 H10 TC B5 STRT ROM L2 GND G11 SC3 A4 INTA K2 SC2 G10 SC4 B4 EX AD ER L3 TIMER CLK F11 A0/EXT AD0 A3 ME PA ER K3 TEST END F10 A1/EXT AD1 B3 PARITY/IB16 L4 RESET E11 A2 A2 IB15 K4 TEST ON E10 GND Document # MICRO-5 REV C Page 7 of 20 PACE1754 STRT ROM Timer Clk IB Bus Output (0:15) EX AD ER Extended Addresses (0:1) Note: All time measurements on active signals relate to 1.5V levels. Document # MICRO-5 REV C Page 8 of 20 PACE1754 RDYD Timing TEST END Timing1 Notes: 1. The last two instructions executed during system test are: XIO RA, 1F44, 0 and JC 7, 0000 hex, 0. After execution of the IOW bus cycle, the XIO proceeds by filling the instruction pipe with two memory read bus cycles where the opcode 7070 hex and 0000 hex are entered to the processor. As from the end of STRBD in the second cycle, TEST END is asserted. At this point, the execution of IC starts by first issuing two fetch cycles from the "old PC" (from addresses XXXX & XXXX+1). The data will be taken from system memory (because TEST END is asserted) but both the address and data are irrelevent. Following that, IC will start filling the pipe from address 0000 hex and 0001 hex, now from the system memory to start user's program execution. 2. All time measurements on active signals relate to 1.5V levels. Document # MICRO-5 REV C Page 9 of 20 PACE1754 Address Bus and Strobes Note: All time measurements on active signals relate to 1.5V levels. Document # MICRO-5 REV C Page 10 of 20 PACE1754 TEST CIRCUITS Standard Output (Non Three-State) Three-State Note: All time measurements on active signals relate to 1.5V levels. Parameter VO VMEA TPLZ ≥ 3V 0.5V TPHZ 0V VCC – 0.5V TPXL VCC/2 1.5V TPXH VCC/2 1.5V Document # MICRO-5 REV C Page 11 of 20 PACE1754 PIN FUNCTIONS Symbol Name Description CPU CLK CPU Clock A single-phase input clock signal (0-40MHz, 40% to 60% duty cycle.) STRBA Strobe Address An active HIGH input which latches the contents of IB(0:15) into the address latches. STRBD Strobe Data An active LOW input which is used for writing or reading data to or from the device and also to produce the external memory and I/O strobes. TIMER CLK Timer Clock A 100KHz output (fixed frequency) based on the programmed operating frequency of the CPU clock. MEMW Memory Write Strobe An active LOW output produced in memory write cycles. MEMR Memory Read Strobe An active LOW output produced in memory read cycles. IOW I/O Write Strobe An active LOW output produced in output write cycles. IOR I/O Read Strobe An active LOW output produced in input read cycles. INTA Interrupt Acknowledge Strobe An active LOW output produced after any interrupt, corresponding to an output write to address 1000 (hex). SCR EN System Configuration An active LOW output (in 64 pin only) produced any time an input read from address 8410 (hex), read system configuration is executed. STRB EN Strobe Enable An active LOW input, enabling the active state of the address outputs and the MEMR, MEMQ, IOR, and IOW outputs. When at a logic "1" (if enabled by bits EST, EAD of the control register) it will correspondingly enable the three-state state of the above signals. IB0 - IB15 Information Bus (0:15) A bi-directional time multiplexed bus. It is an input during the address phase of any bus cycle and also during the data phase when writing. It is an output during the data phase when reading from the device. IB16 Information Bus (16) A bi-directional line. It is an output during write cycles and an input during read cycles. It is used to implement the parity function at the system level. A(0:1)/ EX AD(0:1), A(2:15) Address Bus (0:15) An active HIGH output bus. Contains the address of the current bus cycle as latched by the end of STRBA. In system configurations including the MMU function, the only active lines during memory are A(4:15). In this case, A(2:3) are high impedance (don't care) and A(0:1) turn into inputs called Extended Addresses, EXT ADR (0:1). In this case, these two lines supplied by the MMU, will be used to operate the programmable ready generation during bus cycles. M/IO Memory I/O An input qualifier indicating the nature of the current bus cycle. Document # MICRO-5 REV C Page 12 of 20 PACE1754 PIN FUNCTIONS (Continued) Symbol Name Description R/W Read or Write An input qualifier indicating the nature of the current bus cycle, either Read (1) or Write (0). RESET External Reset An active LOW input used to initialize the device's hardware. TEST ON System Test Enable An active LOW input used to enable the execution of the System Test built into the device, immediately after completion of the P1754 initialization and before fetching any instruction from the user program. TEST END System Test End An active HIGH output indicating whether the system test in the device has been completed. Whenever the system test is disabled by the TEST ON signal, the TEST END output will be at a logical "1" immediately after RESET is removed. STRT ROM Start Up ROM An output following the execution of the ESUR and DSUR, I/O commands as defined in MIL-STD-1750A. It will be at the logical "1" level after executing ESUR and at the logical "0" level after executing DSUR. Initially, it defaults to a logical "1". RDYD Ready Data An active HIGH output to be connected to the P1750A/AE CPU input to control the bus cycle termination. EX RDY External Ready Data An active HIGH input which at logical "0" overrides the internal RDYD generation and forces it to a logical "0". EX RDY1 External Ready Data An active LOW input which at logical "1" overrides the internal RDYD generation and forces it to a logical "0". ME PA ER/ RAM DIS Memory Parity Error An active LOW output indicating a parity error when reading from memory. It becomes an active HIGH output called RAM DISABLE for handshaking with the P1753 MMU when the device is programmed to support EDAC. EX AD ER/ SING ERR Illegal Address Error An active LOW output indicating an illegal address error when referencing memory or I/O. It becomes an active HIGH output called SINGLE ERROR for handshaking with the P1753 MMU when the device is programmed to support EDAC. TC Terminal Count An active HIGH output indicating a Bus time out or a watchdog trigger. SC0–SC4 System Configuration Inputs (for case outlines U, Y, and Z only) which are buffered onto IB0–IB4 when executing an I/O read from I/O address 8410 (hex), system configuration. GND Ground 0 volts system ground. VCC Power Supply 5 volts ± 10% power supply. Case U: Leaded Chip Carrier with Unformed Leads Case Y: Leaded Chip Carrier with Gull-Wing Leads Case Z: Pin Grid Array Document # MICRO-5 REV C Page 13 of 20 PACE1754 Standardized Military Drawing PIN Vendor CAGE Number Vendor similar PIN 5962-8864201UX 3DTT2 P1754-20QLMB 5962-8864201YX 3DTT2 P1754-20QGMB 5962-8864201ZX 3DTT2 P1754-20PGMB 5962-8864202UX 3DTT2 P1754-30QLMB 5962-8864202YX 3DTT2 P1754-30QGMB 5962-8864202ZX 3DTT2 P1754-30PGMB 5962-8864203UX 3DTT2 P1754-40QLMB 5962-8864203YX 3DTT2 P1754-40QGMB 5962-8864203ZX 3DTT2 P1754-40PGMB 5962-8864204TX 3DTT2 P1754-20GMB 5962-8864204XX 3DTT2 P1754-20CMB 5962-8864205TX 3DTT2 P1754-30GMB 5962-8864205XX 3DTT2 P1754-30CMB 5962-8864206TX 3DTT2 P1754-40GMB 5962-8864206XX 3DTT2 P1754-40CMB ORDERING INFORMATION Document # MICRO-5 REV C Page 14 of 20 PACE1754 CASE OUTLINE X: 64 Lead Top Brazed DIP Package, Straight Lead Version (Ordering Code C) Inches .002 .005 .008 .010 .015 .016 .018 .025 .040 .050 .185 .265 .470 .530 .590 .620 .645 1.550 1.563 mm 0.05 0.12 0.20 0.25 0.38 0.40 0.45 0.63 1.01 1.27 4.70 6.73 11.93 13.46 14.98 15.74 16.38 39.37 39.70 NOTES: 1) Dimensions are in inches. 2) Metric equivalents are given for general information only. 3) Unless otherwise specified, tolerances are .02 (0.5 mm) for two place decimals and .005 (0.13 mm) for three place decimals. Document # MICRO-5 REV C Page 15 of 20 PACE1754 CASE OUTLINE T: 64 Lead Top Brazed DIP Package, Gullwing Lead Version (Ordering Code G) Inches .001 .003 .005 .008 .010 .015 .016 .022 .030 .040 .050 .150 .470 .530 .590 .620 .868 1.663 mm 0.03 0.08 0.12 0.20 0.25 0.38 0.41 0.55 0.76 1.01 1.27 3.81 11.93 13.46 14.98 15.74 22.04 42.24 NOTES: 1) Dimensions are in inches. 2) Metric equivalents are given for general information only. 3) Unless otherwise specified, tolerances are .02 (0.5 mm) for two place decimals and .005 (0.13 mm) for three place decimals. 4) Case T is derived from Case X by forming the leads to the shown gullwing configuration. Document # MICRO-5 REV C Page 16 of 20 PACE1754 CASE OUTLINE U: 68 Lead Quad Pack with Straight Leads (Ordering Code QL) Inches .002 .004 .006 .010 .012 .020 .050 .100 .116 .250 .560 .570 .800 .955 1.090 mm 0.05 0.10 0.15 0.25 0.30 0.51 1.27 2.54 2.95 6.40 14.22 14.48 20.32 24.25 27.69 NOTES: 1) 2) 3) 4) 5) Dimensions are in inches. Metric equivalents are given for general information only. Unless otherwise specified, tolerances are .02 (0.5 mm) for two place decimals and .005 (0.13 mm) for three place decimals. Pin 1 indicator can be either rectangle, dot, or triangle at specified location or referenced to the uniquely beveled corner. Corners indicated as notched may be either notched or square. Document # MICRO-5 REV C Page 17 of 20 PACE1754 CASE OUTLINE Y: 68 Lead Quad Pack with Gullwing Leads (Ordering Code QG) Inches .004 .005 .008 .010 .012 .015 .016 .020 .024 .040 .050 .100 .115 .570 .800 .955 1.010 1.090 mm 0.10 0.12 0.20 0.25 0.30 0.38 0.41 0.50 0.60 1.02 1.27 2.54 2.92 14.48 20.32 24.25 25.65 27.68 NOTES: 1) 2) 3) 4) 5) 6) Dimensions are in inches. Metric equivalents are given for general information only. Unless otherwise specified, tolerances are .02 (0.5 mm) for two place decimals and .005 (0.13 mm) for three place decimals. Pin 1 indicator can either be rectangle, dot, or triangle at specified location or referenced to the uniquely beveled corner. Corners indicated as notched my be either notched or square (with radius). Case Y is derived from Case U by forming the leads to the shown gullwing configuration. Document # MICRO-5 REV C Page 18 of 20 PACE1754 CASE OUTLINE Z: 68-Pin Pin Grid Array (PGA) (Ordering Code PG) Inches .016 .020 .040 .050 .059 .060 .098 .100 .120 .150 .170 1.010 1.089 1.160 mm 0.41 0.50 1.01 1.27 1.49 1.52 2.49 2.54 3.04 3.81 4.32 25.65 27.66 29.46 NOTES: 1) Dimensions are in inches. 2) Metric equivalents are given for general information only. 3) Unless otherwise specified, tolerances are .02 (0.5 mm) for two place decimals and .005 (0.13 mm) for three place decimals. 4) Corners except pin number 1 (ref.) can be either rounded or square. 5) All pins must be on the .100" grid. Document # MICRO-5 REV C Page 19 of 20 PACE1754 REVISIONS DOCUMENT NUMBER: DOCUMENT TITLE: MICRO-5 PACE1754 PIC BULK CMOS REV. ISSUE DATE ORIG. OF CHANGE ORIG May-89 RKK New Data Sheet A Jul-04 JDB Added Pyramid logo B Aug-05 JDB Re-created electronic version C 11/15/05 JDB Removed Commercial Temperature Range Document # MICRO-5 REV C DESCRIPTION OF CHANGE Page 20 of 20