P4C1298/P4C1298L ULTRA HIGH SPEED 64K x 4 STATIC CMOS RAM FEATURES Data Retention with 2.0V Supply Full CMOS, 6T Cell High Speed (Equal Access and Cycle Times) – 15/20/25/35 ns (Commercial/Industrial) – 15/20/25/35/45 ns (Military) Three-State Outputs TTL/CMOS Compatible Outputs Low Power Fully TTL Compatible Inputs Single 5V±10% Power Supply Standard Pinout (JEDEC Approved) – 28-Pin 300 mil DIP, SOJ – 28-Pin 350x550 mil LCC Output Enable & Chip Enable control functions DESCRIPTION The P4C1298/L are a 262,144-bit ultra high speed static RAM organized as 64K x 4. The CMOS memory requires no clock or refreshing and has equal access and cycle times. Inputs and outputs are fully TTL-compatible. The RAM operates from a single 5V±10% tolerance power supply. With battery backup, data integrity is maintained for supply voltages down to 2.0V. Current drain is typically 10 µA from a 2.0V supply. Access times as fast as 15 nanoseconds are available, permitting greatly enhanced system speeds. CMOS is utilized to reduce power consumption. FUNCTIONAL BLOCK DIAGRAM PIN CONFIGURATION The P4C1298 is available in a 28-pin 300 mil DIP or SOJ, as well as a 28-pin 350x500 mil LCC package, providing excellent board level densities. DIP (P5, C5) LCC (L5) SOJ (J5) Document # SRAM135 REV OR Revised April 2007 1 P4C1298/L MAXIMUM RATINGS(1) Symbol Parameter Value Unit VCC Power Supply Pin with Respect to GND –0.5 to +7 V VTERM Terminal Voltage with Respect to GND (up to 7.0V) –0.5 to VCC +0.5 V TA Operating Temperature –55 to +125 °C RECOMMENDED OPERATING TEMPERATURE AND SUPPLY VOLTAGE Grade(2) Ambient Temperature Military Industrial Commercial Symbol Parameter Value Unit TBIAS Temperature Under Bias –55 to +125 °C TSTG Storage Temperature –65 to +150 °C PT Power Dissipation 1.0 W IOUT DC Output Current 50 mA CAPACITANCES(4) VCC = 5.0V, TA = 25°C, f = 1.0MHz GND VCC -55°C to +125°C 0V 5.0V ± 10% CIN Input Capacitance –40°C to +85°C 0V 5.0V ± 10% COUT Output Capacitance 0°C to +70°C 0V 5.0V ± 10% Symbol Parameter Conditions Typ. Unit VIN = 0V 5 pF VOUT = 0V 7 pF DC ELECTRICAL CHARACTERISTICS Over recommended operating temperature and supply voltage(2) Symbol Parameter P4C1298 Min Max Test Conditions P4C1298L Min Max Unit VIH Input High Voltage 2.2 VCC +0.5 2.2 VCC +0.5 V VIL Input Low Voltage –0.5(3) 0.8 –0.5(3) 0.8 V VCC +0.5 V 0.2 V VHC CMOS Input High Voltage VCC –0.2 VCC +0.5 VCC –0.2 VLC CMOS Input Low Voltage V CD Input Clamp Diode Voltage VCC = Min., IIN = 18 mA –1.2 –1.2 V VOL Output Low Voltage (TTL Load) IOL = +8 mA, VCC = Min. 0.4 0.4 V VOH Output High Voltage (TTL Load) IOH = –4 mA, VCC = Min. (3) –0.5 2.4 VCC = Max. ILI Input Leakage Current ILO Output Leakage Current ISB Standby Power Supply Current (TTL Input Levels) CE ≥ VIH VCC = Max ., f = Max., Outputs Open ISB1 Standby Power Supply Current (CMOS Input Levels) CE ≥ VHC VCC = Max., f = 0, Outputs Open VIN ≤ VLC or VIN ≥ VHC Document # SRAM135 REV OR –0.5 2.4 V –5 +5 –10 +10 µA –5 +5 –10 +10 µA Mil ___ 40 ___ 20 mA Ind/Comm ___ 20 ___ N/A mA Mil ___ 10 ___ 10 mA Ind/Comm ___ 10 ___ N/A mA VIN = GND to VCC VCC = Max., CE = VIH VOUT = GND to VCC Notes: 1. Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to MAXIMUM rating conditions for extended periods may affect reliability. 0.2 (3) 2. Extended temperature operation guaranteed with 400 linear feet per minute of air flow. 3. Transient inputs with VIL and IIL not more negative than –3.0V and –100mA, respectively, are permissible for pulse widths up to 20 ns. 4. This parameter is sampled and not 100% tested. Page 2 of 11 P4C1298/L POWER DISSIPATION CHARACTERISTICS VS. SPEED Symbol ICC Parameter Dynamic Operating Current* Temperature Range –15 –20 –25 –35 Unit Commercial Industrial 160 125 115 110 mA 160 135 120 115 mA Military 160 150 120 120 mA *VCC = 5.5V. Tested with outputs open. f = Max. Switching inputs are 0V and 3V. CE = VIL DATA RETENTION CHARACTERISTICS (P4C1298L ONLY) Symbol Parameter VDR VCC for Data Retention ICCDR Data Retention Current tCDR Chip Deselect to Data Retention Time tR† Operation Recovery Time Test Conditions Min Typ.* VCC = 2.0V 3.0V Max VCC = 2.0V 3.0V V 2.0 CE ≥ VCC –0.2V, VIN ≥ VCC –0.2V or VIN ≤ 0.2V Unit 10 15 1000 2000 µA 0 ns tRC§ ns *TA = +25°C § tRC = Read Cycle Time † This parameter is guaranteed but not tested. DATA RETENTION WAVEFORM Document # SRAM135 REV OR Page 3 of 11 P4C1298/L AC CHARACTERISTICS—READ CYCLE (VCC = 5V ± 10%, All Temperature Ranges)(2) Sym. -15 Parameter -25 -20 Min Max Min Max Min 15 20 25 -35 Max Min -45 Max Min Unit Max tRC Read Cycle Time tAA Address Access Time 15 20 25 35 45 ns tAC Chip Enable Access Time 15 20 25 35 45 tOH Output Hold from Address Change 3 3 3 3 3 ns ns tLZ Chip Enable to Output in Low Z 3 3 3 3 3 ns tHZ Chip Disable to Output in High Z 8 10 15 15 20 ns tOE Output Enable Low to Data Valid 8 10 15 25 30 ns tOLZ Output Enable Low to Low Z t OHZ Output Enable High to High Z tPU Chip Enable to Power Up Time t PD Chip Disable to Power Down Time 0 0 9 0 0 9 0 15 35 0 15 0 20 ns 0 20 20 0 0 25 ns 45 35 ns ns 45 ns OE CONTROLLED)(5) TIMING WAVEFORM OF READ CYCLE NO. 1 (OE TIMING WAVEFORM OF READ CYCLE NO. 2 (ADDRESS CONTROLLED)(5,6) Document # SRAM135 REV OR Page 4 of 11 P4C1298/L CE CONTROLLED)(5,6) TIMING WAVEFORM OF READ CYCLE NO. 3 (CE Notes: 5. CE is LOW and WE is HIGH for READ cycle. 6. WE is HIGH, and address must be valid prior to or coincident with CE transition LOW. Document # SRAM135 REV OR 7. Transition is measured ±200mV from steady state voltage prior to change with specified loading in Figure 1. This parameter is sampled and not 100% tested. 8. Read Cycle Time is measured from the last valid address to the first transitioning address. Page 5 of 11 P4C1298/L AC CHARACTERISTICS - WRITE CYCLE (VCC = 5V ± 10%, All Temperature Ranges)(2) -15 Sym Parameter Min -20 Max Min -25 Max Min -35 Max Min -45 Max Min tWC Write Cycle Time 15 20 25 35 45 tCW Chip Enable Time to End of Write 10 15 20 25 30 t AW Address Valid to End of Write 10 15 20 25 30 t AS Address Set-up Time 0 0 0 0 0 t WP Write Pulse Width 10 15 20 25 30 t AH Address Hold Time from End of Write 0 0 0 0 0 tDW Data Valid to End of Write 9 10 15 20 20 t DH Data Hold Time 0 0 0 0 0 t WZ Write Enable to Output in High Z tOW Output Active from End of Write 7 0 10 0 15 0 20 0 Max 20 0 WE CONTROLLED) (9) TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE Notes: 9. CE and WE must be LOW for WRITE cycle. 10. OE is LOW for this WRITE cycle. 11. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high impedance state. Document # SRAM135 REV OR 12. Write Cycle Time is measured from the last valid address to the first transition address. 13. Transition is measured ±200mV from steady state voltage prior to change with specified loading in Figure 1. This parameter is sampled and not 100% tested. Page 6 of 11 P4C1298/L CE CONTROLLED)(9,10) TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CE AC TEST CONDITIONS Input Pulse Levels TRUTH TABLE GND to 3.0V Mode CE WE Output Power Standby Input Rise and Fall Times 3ns Standby H X High Z Input Timing Reference Level 1.5V Read L H DOUT Active Output Timing Reference Level 1.5V Write L L DIN Active Output Load See Figures 1 and 2 Figure 1. Output Load Figure 2. Thevenin Equivalent * including scope and test fixture. Note: Because of the ultra-high speed of the P4C1298, care must be taken when testing this device; an inadequate setup can cause a normal functioning part to be rejected as faulty. Long high-inductance leads that cause supply bounce must be avoided by bringing the VCC and ground planes directly up to the contactor fingers. A 0.01 µF high Document # SRAM135 REV OR frequency capacitor is also required between VCC and ground. To avoid signal reflections, proper termination must be used; for example, a 50Ω test environment should be terminated into a 50Ω load with 1.73V (Thevenin Voltage) at the comparator input, and a 116Ω resistor must be used in series with DOUT to match 166Ω (Thevenin Resistance). Page 7 of 11 P4C1298/L ORDERING INFORMATION SELECTION GUIDE The P4C1298 is available in the following temperature, speed and package options. Temperature Range Speed Package 15 20 25 35 Commercial Plastic SOJ, 300 mil -15J3C -20J3C -25J3C -35J3C Industrial Plastic SOJ, 300 mil -15J3I -20J3I -25J3I -35J3I Military Temperature Ceramic DIP, 300 mil -15CM -20CM -25CM -35CM 28-Pin Ceramic LCC -15L28M -20L28M -25L28M -25L28M Military Processeed* Ceramic DIP, 300 mil -15CMB -20CMB -25CMB -35CMB 28-Pin Ceramic LCC -15L28MB -20L28MB -25L28MB -25L28MB Document # SRAM135 REV OR 1513 10 Page 8 of 11 P4C1298/L Pkg # # Pins Symbol A A1 b C D e E E1 E2 Q Pkg # # Pins Symbol A A1 b b2 C D E1 E e eB L α J5 SOJ SMALL OUTLINE IC PACKAGE 28 (300 mil) Min Max 0.120 0.148 0.078 0.014 0.020 0.007 0.011 0.700 0.730 0.050 BSC 0.335 BSC 0.292 0.300 0.267 BSC 0.025 - P5 PLASTIC DUAL IN-LINE PACKAGE 28 (300 mil) Min Max 0.210 0.014 0.023 0.045 0.070 0.008 0.014 1.345 1.400 0.270 0.300 0.300 0.380 0.100 BSC 0.430 0.115 0.150 0° 15° Document # SRAM135 REV OR Page 9 of 11 P4C1298/L Pkg # # Pins Symbol A A1 B1 D D1 D2 D3 E E1 E2 E3 e h j L L1 L2 ND NE Pkg # # Pins Symbol A b b2 C D E eA e L Q S1 S2 L5 RECTANGULAR LEADLESS CHIP CARRIER 28 Min Max 0.060 0.075 0.050 0.065 0.022 0.028 0.342 0.358 0.200 BSC 0.100 BSC 0.358 0.540 0.560 0.400 BSC 0.200 BSC 0.558 0.050 BSC 0.040 REF 0.020 REF 0.045 0.055 0.045 0.055 0.075 0.095 5 9 C5 SIDEBRAZED DUAL IN-LINE PACKAGE 28 (300 mil) Min Max 0.225 0.014 0.026 0.045 0.065 0.008 0.018 1.485 0.240 0.310 0.300 BSC 0.100 BSC 0.125 0.200 0.015 0.070 0.005 0.005 - Document # SRAM135 REV OR Page 10 of 11 P4C1298/L REVISIONS DOCUMENT NUMBER: DOCUMENT TITLE: SRAM135 P4C1298/P4C1298L ULTRA HIGH SPEED 64K x 4 STATIC CMOS RAM REV. ISSUE DATE ORIG. OF CHANGE OR Apr-07 JDB Document # SRAM135 REV OR DESCRIPTION OF CHANGE New Data Sheet Page 11 of 11