P4C148/P4C149 P4C148, P4C149 ULTRA HIGH SPEED 1K x 4 STATIC CMOS RAMS FEATURES Full CMOS, 6T Cell Two Options – P4C148 Low Power Standby Mode – P4C149 Fast Chip Select Control High Speed (Equal Access and Cycle Times) – 10/12/15/20/25 ns (Commercial) – 15/20/25/35 ns (P4C148 Military) Common Input/Output Ports Three-State Outputs Low Power Operation – 715 mW Active –10 (Commecial) – 550 mW Active –25 (Commercial) – 110 mW Standby (TTL Input) P4C148 – 55 mW Standby (CMOS Input) P4C148 Fully TTL Compatible Inputs and Outputs Standard Pinout (JEDEC Approved) – 18 Pin 300 mil DIP Single 5V ± 10% Power Supply DESCRIPTION The P4C148 and P4C149 are 4,096-bit ultra high-speed static RAMs organized as 1K x 4. Both devices have common input/output ports. The P4C148 enters the standby mode when the chip enable (CE) goes HIGH; with CMOS input levels, power consumption is extremely low in this mode. The P4C149 features a fast chip select capability using CS. The CMOS memories require no clocks or refreshing, and have equal access and cycle times. Inputs are fully TTL-compatible. The RAMs operate from a single 5V ± 10% tolerance power supply. Access times as fast as 10 nanoseconds are available, permitting greatly enhanced system operating speeds. FUNCTIONAL BLOCK DIAGRAM PIN CONFIGURATIONS A A A A A A I/O 1 I/O 2 I/O 3 I/O 4 CMOS is used to reduce power consumption when active; for the P4C148, consumption is further reduced in the standby mode. The P4C148 and P4C149 are available in 18-pin 300 mil DIP packages providing excellent board level densities. 4,096-BIT MEMORY ARRAY ROW SELECT INPUT DATA CONTROL COLUMN I/O POWER DOWN COLUMN SELECT A A 1 18 2 17 V CC A9 A2 A3 3 16 A8 4 15 A7 A4 A5 5 14 6 13 I/O4 I/O3 A6 7 12 CE, CS GND 8 11 I/O2 I/O1 9 10 WE P4C148 DIP (P1, D1) P4C149 DIP (P1) TOP VIEW CE/CS A A0 A1 A P4C148 ONLY WE Means Quality, Service and Speed 1Q97 19 P4C148/P4C149 MAXIMUM RATINGS(1) Symbol Parameter Value Unit VCC Power Supply Pin with Respect to GND – 0.5 to +7 V VTERM Terminal Voltage with Respect to GND (up to 7.0V) – 0.5 to VCC +0.5 V TA Operating Temperature – 55 to +125 °C Symbol Parameter Value Unit TBIAS Temperature Under Bias – 55 to +125 °C TSTG Storage Temperature – 65 to +150 °C PT Power Dissipation 1.0 W IOUT DC Output Current 50 mA CAPACITANCES(4) RECOMMENDED OPERATING CONDITIONS (VCC = 5.0V, TA = 25°C, f = 1.0MHz) Symbol Parameter Conditions Typ. Unit Grade(2) Ambient Temp Gnd VCC Commercial 0˚C to 70˚C 0V 5.0V ± 10% CIN Input Capacitance VIN = 0V 5 pF -55˚C to +125˚C 0V 5.0V ± 10% COUT Output Capacitance VOUT= 0V 7 pF Military DC ELECTRICAL CHARACTERISTICS Over recommended operating temperature and supply voltage (2) Sym. P4C148 Test Conditions Parameter Min. Max. VOH Output High Voltage (TTL Load) IOH = –4 mA, VCC = Min. VOL Output Low Voltage (TTL Load) IOL = +8 mA, VCC = Min VIH Input High Voltage 2.2 VCC+0.5 VIL Input Low Voltage –0.5(3) ILI Input Leakage Current VCC = Max., VIN = GND to VCC Mil. Comm’l ILO Output Leakage Current VCC = Max., CE, CS = VIH, VOUT = GND to VCC Mil. Comm’l ISB Standby Power Supply CE≥VIH, VCC = Max., Current (TTL Input Levels) f=Max., Outputs Open ISB1 Standby Power Supply Current (CMOS Input Levels) CE≥VHC, VCC = Max., f= 0, Outputs Open VIN≤0.2V or VIN≥VCC -0.2V 2.4 P4C149 Min. Unit Max. 2.4 V 0.4 0.4 V 2.2 VCC+0.5 V 0.8 –0.5(3) 0.8 V –10 –5 +10 +5 –10 –5 +10 +5 µA –10 –5 +10 +5 –10 –5 +10 +5 µA Mil. Comm’l 30 23 N/A N/A mA Mil. Comm’l 15 10 N/A N/A mA N/A = Not Applicable POWER DISSIPATION CHARACTERISTICS VS. SPEED Symbol Parameter Temperature Range -10 -12 -15 -20 -25 -35 ICC Dynamic Operating Current Commercial Military 130 N/A 130 N/A 120 145 115 135 100 125 N/A 120 20 Unit mA mA P4C148/P4C149 AC CHARACTERISTICS—READ CYCLE (VCC = 5V ± 10%, All Temperature Ranges)(2) Sym. -10 Parameter tAC† Chip Enable Access Time (P4C148) * tAC Chip Select Access Time (P4C149) tOH Output Hold from Address Change tLZ* Chip Enable to Output in Low Z tHZ* Chip Disable to Output in High Z tRCS Read Command Setup Time tRCH Read Command Hold Time tPU† Chip Enable to Power Up Time t -15 -20 -25 -35 Min Max Min Max Min Max Min Max Min Max Min Max 12 15 20 10 35 25 12 35 15 20 10 25 tRC Read Cycle Time tAA Address Access Time † PD -12 ns ns 10 12 15 20 25 35 ns 8 10 12 14 15 20 ns 3 3 2 2 4 3 3 2 2 5 0 0 0 Chip Disable to Power Down Time Unit 2 0 0 0 0 12 0 0 0 0 0 0 15 20 3 ns 2 ns ns 10 8 6 0 0 10 3 14 0 0 0 25 ns ns ns 35 ns TIMING WAVEFORM OF READ CYCLE NO. 1(5) (8) t RC ADDRESS t AA t OH PREVIOUS DATA VALID DATA OUT DATA VALID TIMING WAVEFORM OF READ CYCLE NO. 2(6) t RC CE (7) t HZ t AC (7) t LZ DATA VALID DATA OUT t RCS HIGH IMPEDANCE t RCH WE I V CC SUPPLY CURRENT (P4C148 ONLY) I CC t PU t PD SB Notes: 1. Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to MAXIMUM rating conditions for extended periods may affect reliability. 2. Extended temperature operation guaranteed with 400 linear feet per minute of air flow. 3. Transient inputs with VIL and IIL not more negative than –3.0V and –100mA, respectively, are permissible for pulse widths up to 20 ns. 4. This parameter is sampled and not 100% tested. 5. CE is LOW and WE is HIGH for READ cycle. 6. WE is HIGH, and address must be valid prior to or coincident with CE transition LOW. 7. Transition is measured ±200mV from steady state voltage prior to change with specified loading in Figure 1. This parameter is sampled and not 100% tested. 8. Read Cycle Time is measured from the last valid address to the first transitioning address. 21 P4C148/P4C149 AC CHARACTERISTICS—WRITE CYCLE (VCC = 5V ± 10%, All Temperature Ranges)(2) Sym. -10 -25 -12 -15 -20 -35 Unit Min Max Min Max Min Max Min Max Min Max Min Max Parameter tWC Write Cycle Time 10 12 15 20 25 35 ns tCW Chip Enable Time to End of Write 8 10 12 16 20 25 ns tAW Address Valid to End of Write 8 10 12 16 20 25 ns tAS Address Set-up Time 0 0 0 0 0 0 ns tWP Write Pulse Width 8 10 12 16 20 25 ns tAH Address Hold Time from End of Write 0 0 0 0 0 0 ns tDW Data Valid to End of Write 5 6 7 9 12 16 ns tDH Data Hold Time 0 0 0 0 0 0 ns tWZ Write Enable to Output in High Z tOW Output Active from End of Write 6 5 0 7 0 7 0 0 12 8 0 0 ns ns WE CONTROLLED)(9) TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE t WC (11) ADDRESS t CW CE t AW t WR t AH t WP WE t AS t DW DATA IN t DH DATA VALID t OW(10, 12) (12) t WZ DATA OUT DATA UNDEFINED HIGH IMPEDANCE CE CS CONTROLLED)(9) TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CE CE/CS t WC (11) ADDRESS t AS t CW CE t AH t WR t AW t WP WE t DW DATA IN t DH DATA VALID DATA OUT HIGH IMPEDANCE Notes: 9. CE and WE must be LOW for WRITE cycle. 10. If CE goes HIGH simultaneously with WE high, the output remains in a high impedance state. 11. Write Cycle Time is measured from the last valid address to the first transition address. 12. Transition is measured ±200mV from steady state voltage prior to change with specified loading in Figure 1. This parameter is sampled and not 100% tested. 22 P4C148/P4C149 AC TEST CONDITIONS Input Pulse Levels TRUTH TABLE Mode GND to 3.0V CE WE Output Power Standby Input Rise and Fall Times 3ns Standby H X High Z Input Timing Reference Level 1.5V Read L H DOUT Active Output Timing Reference Level 1.5V Write L L High Z Active Output Load See Figures 1 and 2 RTH = 166.5Ω +5 DOUT 480Ω V TH = 1.73 V DOUT 30pF (5pF* for tHZ, tLZ , tOHZ, tOLZ, tWZ and tOW ) 255Ω 30pF (5pF* for tHZ, tLZ, tOHZ, tOLZ, tWZ and tOW ) Figure 1. Output Load Figure 2. Thevenin Equivalent * including scope and test fixture. Note: Due to the ultra-high speed of the P4C147, care must be taken when testing this device; an inadequate setup can cause a normal functioning part to be rejected as faulty. Long high-inductance leads that cause supply bounce must be avoided by bringing the VCC and ground planes directly up to the contactor fingers. A 0.01 µF high frequency capacitor is also required between VCC and ground. To avoid signal reflections, proper termination must be used; for example, a 50Ω test environment should be terminated into a 50Ω load with 1.73V (Thevenin Voltage) at the comparator input, and a 116Ω resistor must be used in series with DOUT to match 166Ω (Thevenin Resistance). 23 P4C148/P4C149 PACKAGE SUFFIX Package Suffix TEMPERATURE RANGE SUFFIX Temperature Description Range Suffix Description P Plastic DIP, 300 mil wide standard D CERDIP, 300 mil wide C Commercial Temperature Range, 0˚C to +70˚C. Military Temperature Range, –55˚C to +125˚C. Mil. Temp. with MIL-STD-883 Class B Compliance. M MB ORDERING INFORMATION P4C148 P4C149 Device Type xx x x Speed Package Processing C 0˚C to +70˚C M –55°C to +125°C MB Mil. Temp. with MIL-STD-883 Class B Compliance P Plastic DIP (300 mil) D CERDIP (300 mil) 10, 12, 15, 20, 25, 35 1K x 4 SRAM The P4C148 is also available per SMD 5962-87513 SELECTION GUIDE The P4C148/P4C149 are available in the following temperature, speed and package options. Speed (ns) Temperature Range Package Commercial Plastic DIP Military Temp. (P4C148 only) Military Processed* (P4C148 only) 10 12 15 20 25 35 –10PC –12PC –15PC –20PC –25PC N/A CERDIP (300 mil) N/A N/A –15DM –20DM –25DM –35DM CERDIP (300 mil) N/A N/A –15DMB –20DMB –25DMB –35DMB * Military temperature range with MIL-STD-883, Class B processing. N/A = Not Available 24