PYRAMID P4C163

P4C163/P4C163L
ULTRA HIGH SPEED 8K x 9
STATIC CMOS RAMS
FEATURES
Data Retention with 2.0V Supply, 10 µA Typical
Current (P4C163L Military)
Common I/O
Fully TTL Compatible Inputs and Outputs
Standard Pinout (JEDEC Approved)
– 28-Pin 300 mil DIP, SOJ
– 28-Pin 350 x 550 mil LCC
– 28-Pin CERPACK
Full CMOS, 6T Cell
High Speed (Equal Access and Cycle Times)
– 25/35ns (Commercial)
– 25/35/45ns (Military)
Low Power Operation (Commercial/Military)
Output Enable and Dual Chip Enable Control
Functions
Single 5V±10% Power Supply
DESCRIPTION
The P4C163 and P4C163L are 73,728-bit ultra high-speed
static RAMs organized as 8K x 9. The CMOS memories require no clocks or refreshing and have equal access and
cycle times. Inputs are fully TTL-compatible. The RAMs
operate from a single 5V±10% tolerance power supply.
With battery backup, data integrity is maintained for supply
voltages down to 2.0V. Current drain is 10 µA from a 2.0V
supply.
Access times as fast as 25 nanoseconds are available, permitting greatly enhanced system operating speeds. CMOS
is used to reduce power consumption in both active and
standby modes.
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATIONS
The P4C163 and P4C163L are available in 28-pin 300 mil
DIP and SOJ, 28-pin 350 x 550 mil LCC, and 28-pin
CERPACK packages providing excellent board level densities.
DIP (P5, C5), SOJ (J5)
CERPACK (F4) SIMILAR
LCC (L5)
Document # SRAM120 REV C
1
Revised August 2006
P4C163/163L
MAXIMUM RATINGS(1)
Symbol
Parameter
Value
Unit
VCC
Power Supply Pin with
Respect to GND
–0.5 to +7
V
VTERM
Terminal Voltage with
Respect to GND
(up to 7.0V)
–0.5 to
VCC +0.5
V
TA
Operating Temperature
–55 to +125
°C
Symbol
Parameter
Value
Unit
TBIAS
Temperature Under
Bias
–55 to +125
°C
TSTG
Storage Temperature
–65 to +150
°C
PT
Power Dissipation
1.0
W
IOUT
DC Output Current
50
mA
RECOMMENDED OPERATING TEMPERATURE AND SUPPLY VOLTAGE
Grade(2)
Ambient
Temperature
GND
VCC
Military
–55 to +125°C
0V
5.0V ± 10%
Grade(2)
Ambient
Temperature
GND
VCC
Commercial
0°C to +70°C
0V
5.0V ± 10%
DC ELECTRICAL CHARACTERISTICS
Over recommended operating temperature and supply voltage(2)
Symbol
Parameter
P4C163
Test Conditions
P4C163L
Min
Max
Min
Max
Unit
VIH
Input High Voltage
2.2
VCC+0.5
2.2
VCC+0.5
V
VIL
Input Low Voltage
–0.5(3)
0.8
–0.5(3)
0.8
V
VHC
CMOS Input High Voltage
VLC
CMOS Input Low Voltage
VCD
Input Clamp Diode Voltage
VCC = Min., IIN = –18 mA
VOL
Output Low Voltage
(TTL Load)
VOLC
VCC–0.2 VCC+0.5
–0.5
0.2
VCC–0.2 VCC+0.5
–0.5
V
0.2
V
–1.2
–1.2
V
IOL = +8 mA, VCC = Min.
0.4
0.4
V
Output Low Voltage
(CMOS Load)
IOLC = +100 µA, VCC = Min.
0.2
0.2
V
VOH
Output High Voltage
(TTL Load)
IOH = –4 mA, VCC = Min.
VOHC
Output High Voltage
(CMOS Load)
IOHC = –100 µA, VCC = Min.
ILI
Input Leakage Current
VCC = Max.
VIN = GND to VCC
Mil.
Com’l.
–10
–5
+10
+5
–5
N/A
+5
N/A
µA
ILO
Output Leakage Current
VCC = Max., CE = VIH,
VOUT= GND to VCC
Mil.
Com’l.
–10
–5
+10
+5
–5
N/A
+5
N/A
µA
(3)
(3)
2.4
2.4
V
VCC–0.2
VCC–0.2
V
CAPACITANCES(4)
(VCC = 5.0V, TA = 25°C, f = 1.0MHz)
Symbol
CIN
Parameter
Input Capacitance
Conditions Typ. Unit
VIN = 0V
5
pF
Notes:
1. Stresses greater than those listed under MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification
is not implied. Exposure to MAXIMUM rating conditions for extended
periods may affect reliability.
Document # SRAM120 REV C
Symbol
COUT
Parameter
Output Capacitance
Conditions Typ. Unit
VOUT = 0V
7
pF
2. Extended temperature operation guaranteed with 400 linear feet per
minute of air flow.
3. Transient inputs with VIL and IIL not more negative than –3.0V and
–100mA, respectively, are permissible for pulse widths up to 20 ns.
4. This parameter is sampled and not 100% tested.
Page 2 of 12
P4C163/163L
POWER DISSIPATION CHARACTERISTICS
Over recommended operating temperature and supply voltage(2)
Symbol
Parameter
P4C163
Test Conditions
P4C163L
Min
Max
Min
Max
Unit
ICC
Dynamic Operating
Current – 25
VCC = Max., f = Max.,
Outputs Open
Mil.
Com’l.
—
—
145
125
—
—
145
N/A
mA
ICC
Dynamic Operating
Current – 35, 45
VCC = Max., f = Max.,
Outputs Open
Mil.
Com’l.
—
—
120
95
—
—
120
N/A
mA
ISB
Standby Power Supply
CE1 ≥ VIH or
Current (TTL Input Levels) CE2 ≤ VIL, VCC = Max.,
f = Max., Outputs Open
Mil.
Com’l.
—
—
40
35
—
—
40
N/A
mA
ISB1
Standby Power Supply
Current
(CMOS Input Levels)
Mil.
Com’l.
—
—
20
18
—
—
1
N/A
mA
CE1 ≥ VHC or
CE2 ≤ VLC, VCC = Max.,
f = 0, Outputs Open,
VIN ≤ VLC or VIN ≥ VHC
n/a = Not Applicable
DATA RETENTION CHARACTERISTICS (P4C163L, Military Temperature Only)
Symbol
Parameter
VDR
VCC for Data Retention
ICCDR
Data Retention Current
tCDR
Chip Deselect to
Data Retention Time
tR†
Operation Recovery Time
Test Condition
Min
Typ.*
VCC=
2.0V
3.0V
Max
VCC=
2.0V
3.0V
2.0
CE1 ≥ VCC – 0.2V or
CE2 ≤ 0.2V, VIN ≥ VCC – 0.2V
or VIN ≤ 0.2V
Unit
V
10
15
200
300
µA
0
ns
tRC§
ns
*TA = +25°C
§
tRC = Read Cycle Time
†
This parameter is guaranteed but not tested.
DATA RETENTION WAVEFORM
Document # SRAM120 REV C
Page 3 of 12
P4C163/163L
AC ELECTRICAL CHARACTERISTICS—READ CYCLE
(VCC = 5V ± 10%, All Temperature Ranges)(2)
Symbol
Parameter
-25
-35
-45
Min Max Min Max Min Max
25
35
tRC
Read Cycle Time
tAA
Address Access Time
25
35
45
ns
tAC
Chip Enable
Access Time
25
35
45
ns
tOH
Output Hold from
Address Change
3
3
3
ns
tLZ
Chip Enable to
Output in Low Z
3
3
3
ns
tHZ
Chip Disable to
Output in High Z
10
15
20
ns
tOE
Output Enable
Low to Data Valid
13
18
20
ns
tOLZ
Output Enable
Low to Low Z
tOHZ
Output Enable
High to High Z
tPU
Chip Enable to
Power Up Time
tPD
Chip Disable to
Power Down Time
3
45
Unit
3
12
0
3
15
0
20
ns
ns
20
0
20
ns
ns
25
ns
OE CONTROLLED)(5)
READ CYCLE NO. 1 (OE
Notes:
5. WE is HIGH for READ cycle.
6. CE1 is LOW, CE2 is HIGH and OE is LOW for READ cycle.
7. ADDRESS must be valid prior to, or coincident with CE1 transition
LOW and CE2 transition HIGH.
Document # SRAM120 REV C
8. Transition is measured ± 200mV from steady state voltage prior to
change, with loading as specified in Figure 1. This parameter is
sampled and not 100% tested.
Page 4 of 12
P4C163/163L
READ CYCLE NO. 2 (ADDRESS CONTROLLED)(5,6)
CE1, CE2 CONTROLLED)(5,7,10)
READ CYCLE NO. 3 (CE
Notes:
9. READ Cycle Time is measured from the last valid address to the first
transitioning address.
Document # SRAM120 REV C
10. Transitions caused by a chip enable control have similar delays
irrespective of whether CE1 or CE2 causes them.
Page 5 of 12
P4C163/163L
AC CHARACTERISTICS—WRITE CYCLE
(VCC = 5V ± 10%, All Temperature Ranges)(2)
-25
Symbol
Parameter
-35
-45
Min Max Min Max Min Max
Unit
tWC
Write Cycle Time
25
35
45
ns
tCW
Chip Enable
Time to End of Write
18
25
33
ns
tAW
Address Valid to
End of Write
18
25
33
ns
tAS
Address Set-up Time
0
0
0
ns
tWP
Write Pulse Width
18
20
25
ns
tAH
Address Hold Time
0
0
0
ns
tDW
Data Valid to End
of Write
13
15
20
ns
tDH
Data Hold Time
0
0
0
ns
tWZ
Write Enable to
Output in High Z
tOW
Output Active
from End of Write
10
3
14
5
18
5
ns
ns
WE CONTROLLED)(11)
WRITE CYCLE NO. 1 (WE
Notes:
11. CE1 and WE must be LOW, and CE2 HIGH for WRITE cycle.
12. OE is LOW for this WRITE cycle to show tWZ and tOW.
13. If CE1 goes HIGH, or CE2 goes LOW, simultaneously with WE
HIGH, the output remains in a low impedance state.
14. Write Cycle Time is measured from the last valid address to the first
transitioning address.
Document # SRAM120 REV C
Page 6 of 12
P4C163/163L
CE CONTROLLED)(11)
TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CE
AC TEST CONDITIONS
Input Pulse Levels
TRUTH TABLE
GND to 3.0V
Mode
CE1
CE2
OE
WE
I/O
Power
Input Rise and Fall Times
3ns
Standby
H
X
X
X
High Z
Standby
Input Timing Reference Level
1.5V
Standby
X
L
X
X
High Z
Standby
Output Timing Reference Level
1.5V
DOUT
Disabled
L
H
H
H
High Z
Active
Read
L
H
L
H
DOUT
Active
Write
L
H
X
L
DIN
Active
Output Load
See Figures 1 and 2
1527 10
Figure 1. Output Load
Figure 2. Thevenin Equivalent
* including scope and test fixture.
Note:
Because of the ultra-high speed of the P4C163/L, care must be taken
when testing this device; an inadequate setup can cause a normal
functioning part to be rejected as faulty. Long high-inductance leads that
cause supply bounce must be avoided by bringing the VCC and ground
planes directly up to the contactor fingers. A 0.01 µF high frequency
Document # SRAM120 REV C
capacitor is also required between VCC and ground. To avoid signal
reflections, proper termination must be used; for example, a 50Ω test
environment should be terminated into a 50Ω load with 1.73V (Thevenin
Voltage) at the comparator input, and a 116Ω resistor must be used in
series with DOUT to match 166Ω (Thevenin Resistance).
Page 7 of 12
P4C163/163L
ORDERING INFORMATION
SELECTION GUIDE
The P4C163/L is available in the following temperature, speed and package options. The P4C163L is
only available over the military temperature range.
Temperature
Range
Commercial
Miliitary
Temperature
Military
Processed*
Package
Speed
25
35
45
Plastic DIP
-25PC
-35PC
N/A
Plastic SOJ
Side Brazed DIP
-25JC
-35JC
N/A
-25CM
-35CM
-45CM
LCC
-25LM
-35LM
-45LM
CERPACK
Side Brazed DIP
-25FM
-35FM
-45FM
LCC
-25CMB
-25LMB
-35CMB
-35LMB
-45CMB
-45LMB
CERPACK
-25FMB
-35FMB
-45FMB
* Military temperature range with MIL-STD-883, Class B processing.
N/A = Not available
Document # SRAM120 REV C
Page 8 of 12
P4C163/163L
Pkg #
# Pins
Symbol
A
b
b2
C
D
E
eA
e
L
Q
S1
S2
Pkg #
# Pins
Symbol
A
b
c
D
E
e
k
L
Q
S
S1
C5
SIDE BRAZED DUAL IN-LINE PACKAGE
28 (300 mil)
Min
Max
0.225
0.014
0.026
0.045
0.065
0.008
0.018
1.485
0.240
0.310
0.300 BSC
0.100 BSC
0.125
0.200
0.015
0.070
0.005
0.005
-
F4
CERPACK CERAMIC FLAT PACKAGE
28
Min
Max
0.060
0.090
0.015
0.022
0.004
0.009
0.730
0.330
0.380
0.050 BSC
0.005
0.018
0.250
0.370
0.026
0.045
0.085
0.005
-
Document # SRAM120 REV C
Page 9 of 12
P4C163/163L
Pkg #
# Pins
Symbol
A
A1
b
C
D
e
E
E1
E2
Q
Pkg #
# Pins
Symbol
A
A1
B1
D
D1
D2
D3
E
E1
E2
E3
e
h
j
L
L1
L2
ND
NE
J5
SOJ SMALL OUTLINE IC PACKAGE
28 (300 mil)
Min
Max
0.120
0.148
0.078
0.014
0.020
0.007
0.011
0.700
0.730
0.050 BSC
0.335 BSC
0.292
0.300
0.267 BSC
0.025
-
L5
RECTANGULAR LEADLESS CHIP CARRIER
28
Min
Max
0.060
0.075
0.050
0.065
0.022
0.028
0.342
0.358
0.200 BSC
0.100 BSC
0.358
0.540
0.560
0.400 BSC
0.200 BSC
0.558
0.050 BSC
0.040 REF
0.020 REF
0.045
0.055
0.045
0.055
0.075
0.095
5
9
Document # SRAM120 REV C
Page 10 of 12
P4C163/163L
Pkg #
# Pins
Symbol
A
A1
b
b2
C
D
E1
E
e
eB
L
α
P5
PLASTIC DUAL IN-LINE PACKAGE
28 (300 mil)
Min
Max
0.210
0.014
0.023
0.045
0.070
0.008
0.014
1.345
1.400
0.270
0.300
0.300
0.380
0.100 BSC
0.430
0.115
0.150
0°
15°
Document # SRAM120 REV C
Page 11 of 12
P4C163/163L
REVISIONS
DOCUMENT NUMBER:
DOCUMENT TITLE:
SRAM120
P4C164 / P4C163L ULTRA HIGH SPEED 8K x 9 STATIC CMOS RAMS
REV.
ISSUE
DATE
ORIG. OF
CHANGE
OR
1997
DAB
New Data Sheet
A
Oct-05
JDB
Change logo to Pyramid
B
Jul-06
JDB
Added Lead-Free Designation
C
Aug-06
JDB
Updated SOJ package information
Document # SRAM120 REV C
DESCRIPTION OF CHANGE
Page 12 of 12