FINAL COM’L: H-25 PALCE29MA16H-25 24-Pin EE CMOS Programmable Array Logic DISTINCTIVE CHARACTERISTICS ■ High-performance semicustom logic ■ ■ ■ ■ ■ Register/Latch Preload permits full logic replacement; Electrically Erasable (EE) technology allows reprogrammability 16 bidirectional user-programmable I/O logic macrocells for Combinatorial/Registered/ Latched operation Output Enable controlled by a pin or product terms Varied product term distribution for increased design flexibility Programmable clock selection with common pin clock/latch enable (LE) or individual product term clock/LE with LOW/HIGH clock/ LE polarity verification ■ High speed (tPD = 25 ns, fMAX = 33 MHz and fMAX internal = 50 MHz) ■ Full-function AC and DC testing at the factory for high programming and functional yields and high reliability ■ 24-pin 300 mil SKINNYDIP and 28-pin plastic leaded chip carrier packages ■ Extensive third-party software and programmer support through FusionPLD partners GENERAL DESCRIPTION The PALCE29MA16 is a high-speed, EE CMOS Programmable Array Logic (PAL) device designed for general logic replacement in TTL or CMOS digital systems. It offers high speed, low power consumption, high programming yield, fast programming, and excellent reliability. PAL devices combine the flexibility of custom logic with the off-the-shelf availability of standard products, providing major advantages over other BLOCK DIAGRAM 4 4 I/OF4 I/O Logic Macrocell I/O Logic Macrocell I/O Logic Macrocell I/O Logic Macrocell 4 4 4 4 I/O Logic Macrocell I/OF5 8 4 12 4 V I/O Logic Macrocell I/O 4 V I/O Logic Macrocell I/O 5 V I/O Logic Macrocell I/O6 V I/O7 V I/OF6 V I/OF7 V V CLK/LE 4 4 12 8 4 4 12 8 4 4 Programmable AND Array 58x178 I/O Logic Macrocell I/O Logic Macrocell 4 I/O Logic Macrocell 4 4 I/O Logic Macrocell V I/O Logic Macrocell 4 V 4 V 12 4 V I/O Logic Macrocell V 4 V V 4 I/O Logic Macrocell 8 4 V 4 I/O Logic Macrocell 4 I 0 -I 3 I/OE I/OF0 I/OF 1 I/O0 I/O 1 I/O 2 I/O3 I/OF 2 I/OF3 08811G-1 Publication# 08811 Rev. G Issue Date: June 1993 Amendment /0 2-349 AMD GENERAL DESCRIPTION (continued) semicustom solutions such as gate arrays and standard cells, including reduced development time and low upfront development cost. The PALCE29MA16 uses the familiar sum-of-products (AND-OR) structure, allowing users to customize logic functions by programming the device for specific applications. It provides up to 29 array inputs and 16 outputs. It incorporates AMD’s unique input/output logic macrocell which provides flexible input/output structure and polarity, flexible feedback selection, multiple Output Enable choices, and a programmable clocking scheme. The macrocells can be individually programmed as combinatorial, registered, or latched with active-HIGH or active-LOW polarity. The flexibility of the logic macrocells permits the system designer to tailor the device to particular application requirements. Increased logic power has been built into the PALCE29MA16 by providing a varied number of logic product terms per output. Of the 16 outputs, 8 outputs have 4 product terms each, 4 outputs have 8 product terms each, and the other 4 outputs have 12 product terms each. This varied product-term distribution allows complex functions to be implemented in a single PAL device. Each output can be dynamically controlled by a common Output Enable pin or Output Enable product term. Each output can also be permanently enabled or disabled. System operation has been enhanced by the addition of common asynchronous-Preset and Reset product terms and a power-up Reset feature. The PALCE29MA16 also incorporates Preload and Observability functions which permit full logic verification of the design. The PALCE29MA16 is offered in the space-saving 300-mil SKINNYDIP package as well as the plastic leaded chip carrier package. CONNECTION DIAGRAMS Top View SKINNYDIP 23 I3 I/OF0 3 22 I/OF7 I/OF1 4 21 I/OF6 I/O0 5 20 I/O7 I/O1 6 19 I/O6 I/O3 7 8 18 17 I/O1 NC I/O2 I/O5 I/O4 I/OF2 9 16 I/OF5 I/OF3 10 15 I/OF4 I/OE 11 14 I2 GND 12 13 I1 Note: Pin 1 is marked for orientation. I/OF1 I/O0 I/O3 I/OF2 5 25 24 6 7 23 22 8 21 20 19 9 10 11 I/OF6 I/O7 I/O6 NC I/O5 I/O4 I/OF5 12 13 14 15 16 17 18 08811G-2 PIN DESIGNATIONS CLK/LE = Clock or Latch Enable GND = Ground I = Input I/O = Input/Output I/OF = Input/Output with Dual Feedback VCC = Supply Voltage NC = No Connection 2-350 3 2 1 28 27 26 I/OF3 I/OE I/O2 4 I/OF7 2 I3 I0 NC VCC VCC CLK/LE 24 PALCE29MA16H-25 GND NC I1 I2 I/OF4 1 I/OF0 I0 CLK/LE PLCC 08811G-3 AMD ORDERING INFORMATION Commercial Products AMD programmable logic products for commercial applications are available with several ordering options. The order number (Valid Combination) is formed by a combination of these elements: PAL CE 29 MA 16 H -25 P C /4 FAMILY TYPE PAL = Programmable Array Logic OPTIONAL PROCESSING Blank = Standard Processing TECHNOLOGY CE = CMOS Electrically Erasable PROGRAMMING REVISION /4 = First Revision (Requires current programming Algorithm) NUMBER OF ARRAY INPUTS OUTPUT TYPE MA = Advanced Asynchronous Macrocell TEMPERATURE RANGE C = Commercial (0°C to +75°C) NUMBER OF FLIP-FLOPS POWER H = Half Power (100 mA) PACKAGE TYPE P = 24-Pin Plastic SKINNYDIP (PD3024) J = 28-Pin Plastic Leaded Chip Carrier (PL 028) SPEED -25 = 25 ns Valid Combinations Valid Combinations PALCE29MA16H-25 PC, JC /4 Valid Combinations lists configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations. PALCE29MA16H-25 (Com’l) 2-351 AMD device ranging from 4 to 12 wide, with an average of 7 logic product terms per output. An increased number of product terms per output allows more complex functions to be implemented in a single PAL device. This flexibility aids in implementing functions such as counters, exclusive-OR functions, or complex state machines, where different states require different numbers of product terms. FUNCTIONAL DESCRIPTION Inputs The PALCE29MA16 has 29 inputs to drive each product term (up to 58 inputs with both TRUE and complement versions available to the AND array) as shown in the block diagram in Figure 1. Of these 29 inputs, 4 are dedicated inputs, 16 are from eight I/O logic macrocells with two feedbacks, 8 are from other I/O logic macrocells with single feedback and one is the I/OE input. Individual asynchronous-Preset and Reset product terms are connected to all Registered or Latched I/Os. Initially the AND-array gates are disconnected from all the inputs. This condition represents a logical TRUE for the AND array. By selectively programming the EE cells, the AND array may be connected to either the TRUE input or the complement input. When both the TRUE and complement inputs are connected, a logical FALSE results at the output of the AND gate. When the asynchronous-Preset product term is asserted (HIGH) the register or latch will immediately be loaded with a HIGH, independent of the clock. When the asynchronous-Reset product term is asserted (HIGH) the register or latch will be immediately loaded with a LOW, independent of the clock. The actual output state will depend on the macrocell polarity selection. The latches must be in latched mode (not transparent mode) for the Reset, Preset, Preload, and power-up Reset modes to be meaningful. Product Terms The degree of programmability and complexity of a PAL device is determined by the number of connections that form the programmable-AND and OR gates. Each programmable-AND gate is called a product term. The PALCE29MA16 has 178 product terms; 112 of these product terms provide logic capability and others are architectural product terms. Among the control product terms, one is for Observability, and one is for Preload. The Output Enable of each macrocell can be programmed to be controlled by a common Output Enable pin or an individual product term. It may also be permanently disabled. In addition, independent product terms for each macrocell control Preset, Reset and CLK/LE. Input/Output Logic Macrocells The I/O logic macrocell allows the user the flexibility of defining the architecture of each input or output on an individual basis. It also provides the capability of using the associated pin either as an input or an output. The PALCE29MA16 has 16 macrocells, one for each I/O pin. Each I/O macrocell can be programmed for combinatorial, registered or latched operation (see Figure 2). Combinatorial output is desired when the PAL device is used to replace combinatorial glue logic. Registers and Latches are used in synchronous logic applications. Registers and Latches with product term controlled clocks can also be used in asychronous application. Each product term on the PALCE29MA16 consists of a 58-input AND gate. The outputs of these AND gates are connected to a fixed-OR plane. Product terms are allocated to OR gates in a varied distribution across the VCC Common I/OE (Pin) 0 1 1 0 Individual OE Individual Asynchronous Preset S6 1 0 1 0 P0 Preset Q D Q 1 0 P7 or P11 S3 Individual CLK/LE S4 S0 1 0 1 0 S7 I/O X S1 CLK/LE Reset V 1 1 0 0 Common CLK/LE (PIN) 1 1 0 0 1 1 0 0 S2 S5 Individual Asynchronous Reset 1 0 To AND Array RX S8 08811G-4 Figure 2a. PALCE29MA16 Macrocell (Single Feedback) 2-352 PALCE29MA16H-25 AMD a dynamic I/O controlled by the Output Enable pin or by a product term. The output polarity for each macrocell in each of the three modes of operation is user-selectable, allowing complete flexibility of the macrocell configuration. I/O Logic Macrocell Configuration Eight of the macrocells (I/OF0–I/OF7) have two independent feedback paths to the AND array (see Figure 2b). The first is a dedicated I/O pin feedback to the AND array for combinatorial input. The second path consists of a direct register/latch feedback to the array. If the pin is used as a dedicated input using the first feedback path, the register/latch feedback path is still available to the AND array. This path provides the capability of using the register/latch as a buried state register/latch. The other eight macrocells have a single feedback path to the AND array. This feedback is user-selectable as either an I/O pin or a register/latch feedback (see Figure 2a). AMD’s unique I/O macrocell offers major benefits through its versatile, programmable input/output cell structure, multiple clock choices, flexible Output Enable and feedback selection. Eight I/O macrocells with single feedback contain 9 EE cells, while the other eight macrocells contain 8 EE cells for programming the input/ output functions (see Table 1). EE cell S1 controls whether the macrocell will be combinatorial or registered/latched. S0 controls the output polarity (active-HIGH or active-LOW). S2 determines whether the storage element is a register or a latch. S3 allows the use of the macrocell as an input register/latch or as an output register/latch. It selects the direction of the data path through the register/latch. If connected to the usual AND-OR array output, the register/latch is an output connected to the I/O pin. If connected to the I/O pin, the register/latch becomes an input register/latch to the AND array using the feedback data path. Each macrocell can provide true input/output capability. The user can select each macrocell register/latch to be driven by either the signal generated by the AND-OR array or the corresponding I/O pin. When the I/O pin is selected as the input, the feedback path provides the register/latch input to the array. When used as an input, each macrocell is also user-programmable for registered, latched, or combinatorial input. Programmable EE cells S4 and S5 allow the user to select one of the four CLK/LE signals for each macrocell. S6 and S7 are used to control Output Enable as pin controlled, product-term controlled, permanently enabled or permanently disabled. S8 controls a feedback multiplexer for the macrocells with a single feedback path only. The PALCE29MA16 has a dedicated CLK/LE pin and one individual CLK/LE product term or macrocell. All macrocells have a programmable switch to choose between the CLK/LE pin and the CLK/LE product term as the clock or latch enable signal. These signals are clock signals for macrocells configured as registers and latch enable signals for macrocells configured as latches. The polarity of these CLK/LE signals is also individually programmable. Thus different registers or latches can be driven by different clocks and clock phases. Using the programmable EE cells S0–S8 various input and output configurations can be selected. Some of the possible configuration options are shown in Figure 3. In the erased state (charged, disconnected), an architectural cell is said to have a value of “1”; in the programmed state (discharged, connected to GND), an architectural cell is said to have a value of “0.” The Output-Enable mode of each of the macrocells can be selected by the user. The I/O pin can be configured as an output pin (permanently enabled) or as an input pin (permanently disabled). It can also be configured as VCC Common I/OE (Pin) 0 1 1 0 Individual OE Individual Asynchronous Preset S6 1 0 1 0 P0 Preset Q D Q 1 0 P3 S3 Individual CLK/LE S4 1 0 1 0 S0 S7 I/OFX S1 CLK/LE Reset V 1 1 0 0 Common CLK/LE (PIN) 1 1 0 0 1 1 0 0 S5 S2 Individual Asynchronous Reset RFX To AND Array To AND Array 08811G-5 Figure 2b. PALCE29MA16 Macrocell (Dual Feedback) PALCE29MA16H-25 2-353 AMD Table 1a. PALCE29MA16 I/O Logic Macrocell Architecture Selections S3 I/O Cell S2 Storage Element 1 Output Cell 1 Register 0 Input Cell 0 Latch S1 Output Type S0 Output Polarity 1 Combinatorial 1 Active LOW 0 Register/Latch 0 Active HIGH S8 Feedback* 1 Register/Latch 0 I/O *Applies to macrocells with single feedback only. Table 1b. PALCE29MA16 I/O Logic Macrocell Clock Polarity and Output Enable Selections S4 S5 Clock Edge/Latch Enable Level 1 1 CLK/LE pin positive-going edge, active-LOW LE* 1 0 CLK/LE pin negative-going edge, active-HIGH LE* 0 1 CLK/LE PT positive-going edge, active-LOW LE* 0 0 CLK/LE PT negative-going edge, active-HIGH LE* S6 S7 Output Buffer Control 1 1 Pin-Controlled Three-State Enable 1 0 PT-Controlled Three-State Enable 0 1 Permanently Enabled (Output only) 0 0 Permanently Disabled (Input only) Notes: 1 = Erased State (Charged or disconnected). 0 = Programmed State (Discharged or connected). *Active-LOW LE means that data is stored when the LE pin is HIGH, and the latch is transparent when the LE pin is LOW. Active-HIGH LE means the opposite. 2-354 PALCE29MA16H-25 AMD SOME POSSIBLE CONFIGURATIONS OF THE INPUT/OUTPUT LOGIC MACROCELL Q Q S0 = 1 S1 = 0 S3 = 1 S2 = 1 D Q V D V (For other useful configurations, please refer to the macrocell diagrams in Figure 2. All macrocell architecture cells are independently programmable). Q S0 = 1 S1 = 1 S3 = 1 08811G-6 Output Registered/Active Low 08811G-7 Q Q S0 = 0 S1 = 0 S3 = 1 S2 = 1 Q Q S0 = 0 S1 = 1 S3 = 1 08811G-9 08811G-8 Output Registered/Active High D V D V Output Combinatorial/Active Low Output Combinatorial/Active High D Q V Figure 3a. Dual Feedback Macrocells Q S0 = 1 S1 = 0 S3 = 1 S8 = 0 S2 = 1 S0 = 1 S1 = 1 S3 = 1 S8 = 0 08811G-11 08811G-10 Output Registered/Active Low, I/O Feedback D Output Combinatorial/Active Low, I/O Feedback Q LE Q S0 = 0 S1 = 0 S3 = 1 S8 = 0 S2 = 0 S0 = 0 S1 = 1 S3 = 1 S8 = 0 08811G-13 08811G-12 Output Latched/Active High, I/O Feedback Output Combinatorial/Active High, I/O Feedback Figure 3b. Single Feedback Macrocells PALCE29MA16H-25 2-355 AMD Q Q S0 = 1 S1 = 0 S3 = 1 S8 = 1 S2 = 1 D Q V D V SOME POSSIBLE CONFIGURATIONS OF THE INPUT/OUTPUT LOGIC MACROCELL Q S0 = 1 S1 = 1 S3 = 1 S8 = 1 S2 = 1 08811G-14 08811G-15 Output Registered/Active Low, Register Feedback D Output Combinatorial/Active Low, Latched Feedback Q S0 = 1 S1 = 0 S3 = 1 S8 = 1 S2 = 0 LE Q D Q LE Q S0 = 1 S1 = 1 S3 = 1 S8 = 1 S2 = 0 08811G-16 Output Latched/Active Low, Latched Feedback 08811G-17 Output Combinatorial/Active Low, Latched Feedback Figure 3b. Single Feedback Macrocells (Continued) D V Q S3 = 0 S8 = 1 (FOR SINGLE FEEDBACK ONLY) S2 = 1 REGISTER = 0 LATCH 08811G-18 PROGRAMMABLE-AND ARRAY Programmable-AND Array Figure 3c. All Macrocells 2-356 PALCE29MA16H-25 AMD Power-Up Reset All flip-flops power up to a logic LOW for predictable system initialization. The outputs of the PALCE29MA16 depend on whether they are selected as registered or combinatorial. If registered is selected, the output will be LOW if programmed as active LOW and HIGH if programmed as active HIGH. If combinatorial is selected, the output will be a function of the logic. Preload To simplify testing, the PALCE29MA16 is designed with preload circuitry that provides an easy method for testing logical functionality. Both product-term-controlled and supervoltage-enabled preload modes are available. The TTL-level preload product term can be useful during debugging, where supervoltages may not be available. Preload allows any arbitrary state value to be loaded into the registers/latches of the device. A typical functional-test sequence would be to verify all possible state transitions for the device being tested. This requires the ability to set the state registers into an arbitrary “present state” value and to set the device’s inputs into an arbitrary “present input” value. Once this is done, the state machine is clocked into a new state, or “next state,” which can be checked to validate the transition from the “present state.” In this way any transition can be checked. Since preload can provide the capability to go directly to any desired arbitrary state, test sequences may be greatly shortened. Also, all possible states can be tested, thus greatly reducing test time and development costs and guaranteeing proper in-system operation. Observability The output register/latch observability product term, when asserted, suppresses the combinatorial output data from appearing on the I/O pin and allows the observation of the contents of the register/latch on the output pin for each of the logic macrocells. This unique feature allows for easy debugging and tracing of the buried state machines. In addition, a capability of supervoltage observability is also provided. Security Cell A security cell is provided on each device to prevent unauthorized copying of the user’s proprietary logic design. Once programmed, the security cell disables the programming, verification, preload, and the observability modes. The only way to erase the protection cell is by erasing the entire array and architecture cells, in which case no proprietary design can be copied. (This cell should be programmed only after the rest of the device has been completely programmed and verified.) Programming and Erasing The PALCE29MA16 can be programmed on standard logic programmers. It may also be erased to reset a previously configured device back to its virgin state. Erasure is automatically performed by the programming hardware. No special erasure operation is required. Quality and Testability The PALCE29MA16 offers a very high level of built-in quality. The erasability of the device provides a direct means of verifying performance of all the AC and DC parameters. In addition, this verifies complete programmability and functionality of the device to yield the highest programming yield and post-programming functional yield in the industry. Technology The high-speed PALCE29MA16 is fabricated with AMD’s advanced electrically-erasable (EE) CMOS process. The array connections are formed with proven EE cells. Inputs and outputs are designed to be compatible with TTL devices. This technology provides strong input-clamp diodes, output slew-rate control, and a grounded substrate for clean switching. PALCE29MA16H-25 2-357 AMD LOGIC DIAGRAM SKINNY DIP (PLCC) Pinouts CLK/LE (2) 1 0 4 8 12 16 20 24 28 32 36 40 44 48 52 56 (3) 2 I0 (4) 3 I/OF0 Input/ Output Macro 23 (27) I3 OBSERVE PRODUCT TERM (5) 4 I/OF1 Input/ Output Macro Input/ Output Macro Input/ Output Macro (6) 5 I/O 0 22 (26) I/OF 7 21 (25) I/OF 6 Input/ Output Macro Input/ Output Macro 20 (24) I/O 7 (7) 6 I/O 1 Input/ Output Macro 19 (23) I/O6 Input/ Output Macro Continued on Next Page 08811G-19 2-358 PALCE29MA16H-25 AMD LOGIC DIAGRAM SKINNY DIP (PLCC) Pinouts Continued from Previous Page 0 4 8 12 16 20 24 28 32 36 40 44 48 52 56 (9) 7 I/O 2 Input/ Output Macro 18 (21) I/O 5 Input/ Output Macro (10) 8 I/O 3 Input/ Output Macro Input/ Output Macro (11) 9 I/OF2 17 (20) I/O 4 Input/ Output Macro Input/ Output Macro (12) 10 I/OF 3 16 (19) I/OF5 Input/ Output Macro PRELOAD PRODUCT TERM 15 (18) I/OF4 Input/ Output Macro (13) 11 I/OE 14 (17) I2 13 (16) I1 0 4 8 12 16 20 24 28 32 36 PALCE29MA16H-25 40 44 48 52 56 08811G-19 (concluded) 2-359 AMD ABSOLUTE MAXIMUM RATINGS OPERATING RANGES Storage Temperature . . . . . . . . . . . –65°C to +150°C Ambient Temperature with Power Applied . . . . . . . . . . . . . –55°C to +125°C Commercial (C) Devices Ambient Temperature (TA) Operating in Free Air . . . . . . . . . . . . . . 0°C to +75°C Supply Voltage with Respect to Ground . . . . . . . . . . . . . –0.5 V to +7.0 V Supply Voltage (VCC) with Respect to Ground . . . . . . . . +4.75 V to +5.25 V DC Input Voltage . . . . . . . . . . . –0.5 V to VCC + 0.5 V Operating ranges define those limits between which the functionality of the device is guaranteed. DC Output or I/O Pin Voltage . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V Latchup Current (TA = 0°C to +75°C) . . . . . . 100 mA Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ. DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified Parameter Symbol Parameter Description Test Conditions Min Max VOH Output HIGH Voltage IOH = –2 mA VIN = VIH or VIL VCC = Min VOL Output LOW Voltage IOL = 8 mA VIN = VIH or VIL 0.5 IOL = 4 mA VCC = Min 0.33 Unit 2.4 IOL = 20 µA V V 0.1 VIH Input HIGH Voltage Guaranteed Input Logical HIGH Voltage for all Inputs (Note 1) 2.0 VIL Input LOW Voltage Guaranteed Input Logical LOW Voltage for all Inputs (Note 1) 0.8 V IIH Input HIGH Leakage Current VIN = 5.5 V, VCC = Max (Note 2) 10 µA IIL Input LOW Leakage Current VIN = 0 V, VCC = Max (Note 2) –10 µA IOZH Off-State Output Leakage Current HIGH VOUT = 5.5 V, VCC = Max VIN = VIH or VIL (Note 2) 10 µA IOZL Off-State Output Leakage Current LOW VOUT = 5.5 V, VCC = Max VIN = VIH or VIL (Note 2) –10 µA ISC Output Short-Circuit Current VOUT = 0.5 V, VCC = Max (Note 3) –130 mA ICC Supply Current VIN = 0 V, Outputs Open (IOUT = 0 mA) VCC = Max 100 mA –30 V Notes: 1. These are absolute values with respect to device ground all overshoots due to system and/or tester noise are included. 2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH). 3. Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second. VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation. 2-360 PALCE29MA16H-25 (Com’l) AMD CAPACITANCE (Note 1) Parameter Symbol CIN COUT Parameter Description Test Conditions Typ Unit Input Capacitance VIN = 0 V VCC = 5.0 V, TA = 25°C, 5 pF Output Capacitance VOUT = 0 V f = 1 MHz 8 pF Note: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. SWITCHING CHARACTERISTICS Registered Operation Parameter Symbol Parameter Description Min Max Unit 25 ns Combinatorial Output tPD Input or I/O Pin to Combinatorial Output Output Register – Pin Clock tSOR Input or I/O Pin to Output Register Setup tCOR Output Register Clock to Output tHOR Data Hold Time for Output Register 15 ns 15 0 ns ns Output Register – Product Term Clock tSORP I/O Pin or Input to Output Register Setup tCORP Output Register Clock to Output tHORP Data Hold Time for Output Register 4 ns 29 ns 10 ns 2 ns Input Register – Pin Clock tSIR I/O Pin to Input Register Setup tCIR Register Feedback Clock to Combinatorial Output tHIR Data Hold time for Input Register 28 ns 6 ns Clock and Frequency tCIS Register Feedback (Pin Driven Clock) to Output Register/Latch (Pin Driven) Setup 20 ns tCISPP Register Feedback (PT Driven Clock) to Output Register/Latch (PT Driven) Setup 25 ns fMAX Maximum Frequency (Pin Driven) 1/(tSOR + tCOR) 33.3 MHz fMAXI Maximum Internal Frequency (Pin Driven) 1/tCIS 50 MHz fMAXP Maximum Frequency (PT Driven) 1/(tSORP + tCORP) 30 MHz fMAXIPP Maximum Internal Frequency (PT Driven) 1/tCISPP 40 MHz tCWH Pin Clock Width HIGH 8 ns tCWL Pin Clock Width LOW 8 ns tCWHP PT Clock Width HIGH 12 ns tCWLP PT Clock Width LOW 12 ns PALCE29MA16H-25 (Com’l) 2-361 AMD CLK V tSIR t CIS AND-OR Array t CIS V t COR Output Register Input Register I/O I/O I/O t CIR I/O t SOR t PD t PD 08811G-20 Input/Output Register Specs (Pin CLK Reference) CLK Input V t CISPP AND-OR Array t CISPP V Output Register Input Register I/O t CORP I/O I/O I/O tSORP t PD t PD 08811G-21 Input/Output Register Specs (PT CLK Reference) 2-362 PALCE29MA16H-25 AMD SWITCHING WAVEFORMS Combinatorial Input VT tPD Combinatorial Output VT 08811G-22 Combinatorial Output Combinatorial Output Combinatorial Input VT VT tSOR Clock tHOR VT tCOR Registered Output VT Output Register (Pin Clock) Output Register (Pin Clock) Combinatorial Input VT VT t HORP t SORP Combinatorial Input as Clock 08811G-23 VT t CORP Registered Output VT Output Register (PT Clock) Output Register (PT Clock) Registered Input VT VT t SIR Clock 08811G-24 t HIR VT t CIR Combinatorial Output VT Input InputRegister Register PALCE29MA16H-25 08811G-25 2-363 AMD SWITCHING WAVEFORMS t CIS Clock VT VT tCWH VT t CWL Pin Clock Width Pin Clock Width 08811G-26 t CISPP Combinatorial Input as Clock VT VT VT t CWLP t CWHP 08811G-27 PT Clock PT Clock WidthWidth 2-364 PALCE29MA16H-25 AMD SWITCHING CHARACTERISTICS Latched Operation Parameter Symbol Parameter Description Min Max Unit Combinatorial Output tPD Input or I/O Pin to Combinatorial Output 25 ns tPTD Input or I/O Pin to Output via Transparent Latch 28 ns Output Latch – Pin LE tSOL Input or I/O Pin to Output Register Setup tGOL Latch Enable to Transparent Mode Output tHOL Data Hold Time for Output Latch 0 ns tSTL Input or I/O Pin to Output Latch Setup via Transparent Input Latch 18 ns 4 ns 15 ns 15 ns Output Latch – Product Term LE tSOLP Input or I/O Pin to Output Latch Setup tGOLP Latch Enable to Transparent Mode Output tHOLP Data Hold Time for Output Latch 10 ns tSTLP Input or I/O Pin to Output Latch Setup via Transparent Input Latch 10 ns 2 ns 29 ns Input Latch – Pin LE tSIL I/O Pin to Input Latch Setup tGIL Latch Feedback, Latch Enable Transparent Mode to Combinatorial Output tHIL Data Hold Time for Input Latch 6 ns tGIS Latch Feedback (Pin Driven) to Output Register/Latch (Pin Driven) Setup 20 ns tGISPP Latch Feedback (PT Driven) to Output Register/Latch (PT Driven) Setup 25 ns tGWH Pin Enable Width HIGH 8 ns tGWL Pin Enable Width LOW 8 ns tGWHP PT Enable Width HIGH 12 ns tGWLP PT Enable Width LOW 12 ns 28 ns Latch Enable PALCE29MA16H-25 (Com’l) 2-365 AMD LE t GIS AND-OR Array t GIS t STL t GOL Output Latch Input Latch t SIL tPTD I/O t PTD I/O I/O t GIL t PTD t PD I/O t SOL t PTD t PD 08811G-28 Input/Output Latch Specs (Pin LE Reference) LE INPUT tGISPP t STLP tPTD AND-OR Array tGISPP t GOLP Output Latch Input Latch I/O I/O I/O I/O t t PTD SOLP t PTD t PD t PTD tPD 08811G-29 Input/Output Latch Specs (PT LE Reference) 2-366 PALCE29MA16H-25 AMD SWITCHING WAVEFORMS Latched Input VT LE Latched Transparent tPTD Combinatorial Input VT VT Input Latch tGIS tPD Combinatorial Output VT VT Transparent LE Output Latch Latched tPTD 08811G-31 Latched Output VT Input and Output Latch Relationship 08811G-30 Latch (Transparent Mode) Latched Input Latched Input VT VT t STLP t STL Combinatorial Input VT Combinatorial Input VT t SOL LE VT t SOLP t HOL VT VT Transparent t HOLP Combinatorial Input as LE VT VT Transparent t GOL Latched Output VT VT t PTD t PTD t GOLP Latched Output Note 1 VT VT t PTD 08811G-33 08811G-32 Output Latch (Pin LE) Latched Input Output Latch (PT LE) VT VT t SIL LE LATCHED t GIL t HIL VT LE VT VT VT Transparent TRANSPARENT VT t GWL t GWH 08811G-35 Combinatorial Output VT Pin LE Width VT t PTD 08811G-34 Input Latch (Pin LE) Latched Combinatorial Input as LE VT Transparent VT VT t GWLP tGWHP PT LE Width Note: 08811G-36 1. If the combinatorial input changes while LE is in the latched mode and LE goes into the transparent mode after tPTD ns has elasped, the corresponding latched output will change tGOL ns after LE goes into the transparent mode. If the combinatorial input changes while LE is in the latched mode and LE goes into the transparent mode before tPTD ns has elapsed, the corresponding latched output will change at the later of the following – tPTD ns after the combinatorial input changes or tGOL ns after LE goes into the latched mode. PALCE29MA16H-25 2-367 AMD SWITCHING CHARACTERISTICS Reset/Preset, Enable Parameter Symbol Parameter Description Min Max Unit 30 ns tAPO Input or I/O Pin to Output Register/Latch Reset/Preset tAW Asynchronous Reset/Preset Pulse Width 15 ns tARO Asynchronous Reset/Preset to Output Register/Latch Recovery 15 ns tARI Asynchronous Reset/Preset to Input Register/Latch Recovery 12 ns tARPO Asynchronous Reset/Preset to Output Register/Latch Recovery PT Clock/LE 4 ns tARPI Asynchronous Reset/Preset to Input Register/Latch Recovery PT Clock/LE 6 ns Output Enable Operation tPZX I/OE Pin to Output Enable 20 ns tPXZ I/OE Pin to Output Disable (Note 1) 20 ns tEA Input or I/O to Output Enable via PT 25 ns tER Input or I/O to Output Disable via PT (Note 1) 25 ns Note: 1. Output disable times do not include test load RC time constants. SWITCHING WAVEFORMS t AW Combinatorial Asynchronous Reset/Preset VT t APO Registered/ Latched Output t ARO VT Clock VT Pin 11 VT 08811G-37 Combinatorial/ Registered/ Latched Output Output Register/Latch Reset/Preset t PXZ t PZX VOH - 0.5 V VOL + 0.5 V VT 08811G-39 Pin 11 to Output Disable/Enable t AW Combinatorial Asynchronous Reset/Preset VT Combinatorial Input t ARI Clock VT 08811G-38 Combinatorial/ Registered/ Latched Output Input Register/Latch Reset/Preset 2-368 PALCE29MA16H-25 (Com’l) VT t ER t EA VOH - 0.5 V VOL + 0.5 V VT 08811G-40 Input to Output Disable/Enable AMD KEY TO SWITCHING WAVEFORMS WAVEFORM INPUTS OUTPUTS Must be Steady Will be Steady May Change from H to L Will be Changing from H to L May Change from L to H Will be Changing from L to H Don’t Care, Any Change Permitted Changing, State Unknown Does Not Apply Center Line is HighImpedance “Off” State KS000010-PAL SWITCHING TEST CIRCUIT S1 5V R1 Output R2 CL 08811G-41 Specification Switch S1 tPD, tCO, tGOL Closed tEA, tPZX Z→H: open CL H→Z: open R2 Measured Output Value 1.5 V 1.5 V 35 pF 470 Ω Z→L: closed tER, tPXZ R1 5 pF L→Z: closed 390 Ω H→Z: VOH –0.5 V L→Z: VOL +0.5 V PALCE29MA16H-25 2-369 AMD PRELOAD ■ Pulse the clock pin (pin 1). The PALCE29MA16 has the capability for product-term Preload. When the global-preload product term is true, the PALCE29MA16 will enter the preload mode. This feature aids functional testing by allowing direct setting of register states. The procedure for Preload is as follows: ■ Remove the inputs to the I/O pins. ■ Set the selected input pins to the user selected preload condition. ■ Apply the desired register value to the I/O pins. This sets Q of the register. The value seen on the I/O pin, after Preload, will depend on whether the macrocell is active high or active low. Parameter Symbol ■ Remove the Preload condition. ■ Verify VOL/VOH for all output pins as per pro- grammed pattern. Because the Preload command is a product term, any input to the array can be used to set Preload (including I/O pins and registers). Preload itself will change the values of the I/O pins and registers. This will have unpredictable results. Therefore, only dedicated input pins should be used for the Preload command. Parameter Description Min Rec. Max Unit tD Delay Time 0.5 1.0 5.0 µs tW Pulse Width 250 500 700 ns tI/O Valid Output 100 500 ns VIH Inputs Preload Mode VIL tD tIO Data to be Preloaded I/O Pins tD VOH/VIH VOL/VIL tD VIH CLK Pin 1 (2) tW VIL 08811G-42 Preload Waveform 2-370 PALCE29MA16H-25 AMD ■ Set the inputs to the, user selected, Observe OBSERVABILITY The PALCE29MA16 has the capability for product-term Observability. When the global-Observe product term is true, the PALCE29MA16 will enter the Observe mode. This feature aids functional testing by allowing direct observation of register states. When the PALCE29MA16 is in the Observe mode, the output buffer is enabled and the I/O pin value will be Q of the corresponding register. This overrides any OE inputs. The procedure for Observe is: configuration. ■ The register values will be sent to the corresponding I/O pins. ■ Remove the Observe configuration from the selected I/O pins. Because the Observe command is a product term, any input to the array can be used to set Observe (including I/O pins and registers). If I/O pins are used, the observe mode could cause a value change, which would cause the device to oscillate in and out of the Observe mode. Therefore, only dedicated input pins should be used for the Observe command. ■ Remove the inputs to all the I/O pins. Parameter Symbol Parameter Description Min Rec. Max Unit tD Delay Time 0.5 1.0 5.0 µs tI/O Valid Output 100 500 ns VIH Input Pins Observe Mode VIL tIO tD VOH I/O Pins VOL VIH CLK Pin 1 (2) VIL 08811G-43 Observability Waveform PALCE29MA16H-25 2-371 AMD POWER-UP RESET The registered devices in the AMD PAL Family have been designed with the capability to reset during system power-up. Following power-up, all registers will be reset to LOW. The output state will depend on the polarity of the output buffer. This feature provides extra flexibility to the designer and is especially valuable in simplifying state machine initialization. A timing diagram and parameter table are shown below. Due to the Parameter Symbol asynchronous operation of the power-up reset, and the wide range of ways VCC can rise to its steady state, two conditions are required to ensure a valid power-up reset. These conditions are: ■ The VCC rise must be monotonic. ■ Following reset, the clock input must not be driven from LOW to HIGH until all applicable input and feedback setup times are met. Parameter Description tPR Power-Up Reset Time Min tS Input or Feedback Setup Time tW Clock Width tR VCC Rise Time Max Unit 10 µs See Switching Characteristics µs 500 VCC 4V Power tR tPR Registered Active LOW Output tS Clock tW 08811G-44 Power-Up Reset Waveform 2-372 PALCE29MA16H-25 AMD TYPICAL THERMAL CHARACTERISTICS Measured at 25°C ambient. These parameters are not tested. Parameter Symbol Typ Parameter Description SKINNYDIP PLCC Unit θjc Thermal impedance, junction to case 17 11 °C/W θja Thermal impedance, junction to ambient 63 51 °C/W 200 lfpm air 60 43 °C/W 400 lfpm air 52 38 °C/W 600 lfpm air 43 34 °C/W 800 lfpm air 39 30 °C/W θjma Thermal impedance, junction to ambient with air flow Plastic θjc Considerations The data listed for plastic θjc are for reference only and are not recommended for use in calculating junction temperatures. The heat-flow paths in plastic-encapsulated devices are complex, making the θjc measurement relative to a specific location on the package surface. Tests indicate this measurement reference point is directly below the die-attach area on the bottom center of the package. Furthermore, θjc tests on packages are performed in a constant-temperature bath, keeping the package surface at a constant temperature. Therefore, the measurements can only be used in a similar environment. PALCE29MA16H-25 2-373