PCF85134 Universal LCD driver for low multiplex rates Rev. 01 — 17 December 2009 Product data sheet 1. General description The PCF85134 is a peripheral device which interfaces to almost any LCD1 with low multiplex rates. It generates the drive signals for any static or multiplexed LCD containing up to four backplanes and up to 60 segments. In addition, the PCF85134 can be easily cascaded for larger LCD applications. The PCF85134 is compatible with most microprocessors or microcontrollers and communicates via a two-line bidirectional I2C-bus. Communication overheads are minimized using display RAM with auto-incremented addressing, hardware subaddressing, and display memory switching (static and duplex drive modes). 2. Features n Single-chip LCD controller and driver n Selectable backplane drive configurations: static, 2, 3, or 4 backplane multiplexing n 60 segment outputs allowing to drive: u 30 7-segment alphanumeric characters u 16 14-segment alphanumeric characters u Any graphics of up to 240 elements n Cascading supported for larger applications n 60 × 4-bit display data storage RAM n Wide LCD supply range: from 2.5 V for low threshold LCDs up to 6.5 V for guest-host LCDs and high threshold twisted nematic LCDs n Internal LCD bias generation with voltage follower buffers n Selectable display bias configurations: static, 1⁄2, or 1⁄3 n Wide logic power supply range: from 1.8 V to 5.5 V n LCD and logic supplies may be separated n Low power consumption n 400 kHz I2C-bus interface n Compatible with any microprocessor or microcontroller n No external components required n Display memory bank switching in static and duplex drive mode n Auto-incremented display data loading n Versatile blink modes n Silicon gate CMOS process 1. The definition of the abbreviations and acronyms used in this data sheet can be found in Section 17. PCF85134 NXP Semiconductors Universal LCD driver for low multiplex rates 3. Ordering information Table 1. Ordering information Type number PCF85134HL/1 Package Name Description Delivery form Version LQFP80 plastic low profile quad flat package; 80 leads; body 12 × 12 × 1.4 mm tape and reel SOT315-1 4. Marking Table 2. Marking codes Type number Marking code PCF85134HL/1 PCF85134HL PCF85134_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 17 December 2009 2 of 40 PCF85134 NXP Semiconductors Universal LCD driver for low multiplex rates 5. Block diagram S0 to S59 BP0 BP1 BP2 BP3 60 VLCD BACKPLANE OUTPUTS LCD VOLTAGE SELECTOR DISPLAY SEGMENT OUTPUTS DISPLAY REGISTER OUTPUT BANK SELECT AND BLINK CONTROL DISPLAY CONTROL LCD BIAS GENERATOR VSS PCF85134 CLK SYNC CLOCK SELECT AND TIMING BLINKER TIMEBASE OSC OSCILLATOR POWER-ON RESET SCL INPUT FILTERS SDA COMMAND DECODE WRITE DATA CONTROL I2C-BUS CONTROLLER SA0 Fig 1. DISPLAY RAM DATA POINTER AND AUTO INCREMENT SUBADDRESS COUNTER VDD A0 A1 A2 013aaa204 Block diagram of PCF85134 PCF85134_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 17 December 2009 3 of 40 PCF85134 NXP Semiconductors Universal LCD driver for low multiplex rates 6. Pinning information 61 S11 62 S12 63 S13 64 S14 65 S15 66 S16 67 S17 68 S18 69 S19 70 S20 71 S21 72 S22 73 S23 74 S24 75 S25 76 S26 77 S27 78 S28 79 S29 80 S30 6.1 Pinning S31 1 60 S10 S32 2 59 S9 S33 3 58 S8 S34 4 57 S7 S35 5 56 S6 S36 6 55 S5 S37 7 54 S4 S38 8 53 S3 S39 9 52 S2 S40 10 51 S1 PCF85134 S41 11 50 S0 CLK 40 SCL 39 SDA 38 n.c. 37 n.c. 36 n.c. 35 n.c. 34 BP3 33 BP2 32 BP1 31 BP0 30 41 VDD S59 29 42 SYNC S50 20 S58 28 43 OSC S49 19 S57 27 44 A0 S48 18 S56 26 45 A1 S47 17 S55 25 46 A2 S46 16 S54 24 47 SA0 S45 15 S53 23 48 VSS S44 14 S52 22 49 VLCD S43 13 S51 21 S42 12 013aaa205 Top view. For mechanical details, see Figure 22. Fig 2. Pin configuration for SOT315-1 (PCF85134) PCF85134_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 17 December 2009 4 of 40 PCF85134 NXP Semiconductors Universal LCD driver for low multiplex rates 6.2 Pin description Table 3. Pin description Symbol Pin Description S31 to S59 1 to 29 LCD segment output 31 to 59 BP0 to BP3 30 to 33 LCD backplane output 0 to 3 n.c. 34 to 37 not connected SDA 38 I2C-bus serial data input and output SCL 39 I2C-bus serial clock input CLK 40 external clock input and internal clock output VDD 41 supply voltage SYNC 42 cascade synchronization input and output (active LOW) OSC 43 enable input for internal oscillator A0 to A2 44 to 46 subaddress counter input 0 to 2 SA0 47 I2C-bus slave address input 0 VSS 48 ground supply voltage VLCD 49 input of LCD supply voltage S0 to S30 50 to 80 LCD segment output 0 to 30 PCF85134_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 17 December 2009 5 of 40 PCF85134 NXP Semiconductors Universal LCD driver for low multiplex rates 7. Functional description The PCF85134 is a versatile peripheral device designed to interface any microprocessor or microcontroller to a wide variety of LCDs. It can directly drive any static or multiplexed LCD containing up to four backplanes and up to 60 segments. The display configurations possible with the PCF85134 depend on the number of active backplane outputs required. A selection of display configurations is shown in Table 4. All of these configurations can be implemented in the typical system shown in Figure 3. Table 4. Selection of display configurations Number of 7-segment alphanumeric 14-segment alphanumeric Dot matrix Backplanes Elements Digits Indicator symbols Characters Indicator symbols 4 240 30 30 16 16 240 (4 × 60) 3 180 22 26 12 12 180 (3 × 60) 2 120 15 15 8 8 120 (2 × 60) 1 60 7 11 4 4 60 (1 × 60) VDD R≤ tr 2Cb HOST MICROPROCESSOR/ MICROCONTROLLER VDD VLCD 60 segment drives SDA LCD PANEL SCL PCF85134 OSC A0 A1 A2 (up to 240 elements) SA0 VSS 013aaa206 VSS Fig 3. 4 backplanes Typical system configuration The host microprocessor or microcontroller maintains the 2-line I2C-bus communication channel with the PCF85134. Biasing voltages for the multiplexed LCD waveforms are generated internally, removing the need for an external bias generator. The internal oscillator is selected by connecting pin OSC to VSS. The only other connections required to complete the system are the power supplies (pins VDD, VSS and VLCD) and the LCD panel selected for the application. 7.1 Power-On Reset (POR) At power-on, the PCF85134 resets to the following default starting conditions: • • • • • All backplane outputs are set to VLCD All segment outputs are set to VLCD The selected drive mode is: 1:4 multiplex with 1⁄3 bias Blinking is switched off Input and output bank selectors are reset PCF85134_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 17 December 2009 6 of 40 PCF85134 NXP Semiconductors Universal LCD driver for low multiplex rates • The I2C-bus interface is initialized • The data pointer and the subaddress counter are cleared (set to logic 0) • The display is disabled Remark: Do not transfer data on the I2C-bus for at least 1 ms after a power-on to allow the reset action to complete. 7.2 LCD bias generator Fractional LCD biasing voltages are obtained from an internal voltage divider of three series resistors connected between pins VLCD and VSS. The center resistor is bypassed by switch if the 1⁄2 bias voltage level for the 1:2 multiplex drive mode configuration is selected. 7.3 LCD voltage selector The LCD voltage selector coordinates the multiplexing of the LCD in accordance with the selected LCD drive configuration. The operation of the voltage selector is controlled by the mode-set command (see Table 10) from the command decoder. The biasing configurations that apply to the preferred modes of operation, together with the biasing characteristics as functions of VLCD and the resulting discrimination ratios (D) are given in Table 5. Table 5. Biasing characteristics LCD drive mode Number of: LCD bias Backplanes Levels configuration V off ( RMS ) -------------------------V LCD V on ( RMS ) V on ( RMS ) ------------------------- D = -------------------------V off ( RMS ) V LCD static 1 2 static 0 1 ∞ 1:2 multiplex 2 3 1⁄ 2 0.354 0.791 2.236 4 1⁄ 3 0.333 0.745 2.236 0.333 0.638 1.915 0.333 0.577 1.732 1:2 multiplex 2 1:3 multiplex 3 4 1⁄ 3 1:4 multiplex 4 4 1⁄ 3 A practical value for VLCD is determined by equating Voff(RMS) with a defined LCD threshold voltage (Vth), typically when the LCD exhibits approximately 10 % contrast. In the static drive mode a suitable choice is VLCD > 3Vth. Multiplex drive modes of 1:3 and 1:4 with 1⁄2 bias are possible but the discrimination and hence the contrast ratios are smaller. 1 Bias is calculated by ------------- , where the values for a are 1+a a = 1 for 1⁄2 bias a = 2 for 1⁄3 bias The RMS on-state voltage (Von(RMS)) for the LCD is calculated with Equation 1: V on ( RMS ) = V LCD a 2 + 2a + n -----------------------------2n × (1 + a) PCF85134_1 Product data sheet (1) © NXP B.V. 2009. All rights reserved. Rev. 01 — 17 December 2009 7 of 40 PCF85134 NXP Semiconductors Universal LCD driver for low multiplex rates where the values for n are n = 1 for static drive mode n = 2 for 1:2 multiplex drive mode n = 3 for 1:3 multiplex drive mode n = 4 for 1:4 multiplex drive mode The RMS off-state voltage (Voff(RMS)) for the LCD is calculated with Equation 2: V off ( RMS ) = V LCD a 2 – 2a + n -----------------------------2n × (1 + a) (2) Discrimination is the ratio of Von(RMS) to Voff(RMS) and is determined from Equation 3: V on ( RMS ) D = ----------------------- = V off ( RMS ) 2 (a + 1) + (n – 1) ------------------------------------------2 (a – 1) + (n – 1) (3) Using Equation 3, the discrimination for an LCD drive mode of 1:3 multiplex with 1⁄ 2 bias is 1⁄ 2 bias 21 is ---------- = 1.528 . 3 3 = 1.732 and the discrimination for an LCD drive mode of 1:4 multiplex with The advantage of these LCD drive modes is a reduction of the LCD full scale voltage VLCD as follows: • 1:3 multiplex (1⁄2 bias):V LCD = 6 × V off ( RMS ) = 2.449V off ( RMS ) 4 × 3) • 1:4 multiplex (1⁄2 bias): V LCD = (--------------------- = 2.309V off ( RMS ) 3 These compare with V LCD = 3V off ( RMS ) when 1⁄3 bias is used. It should be noted that VLCD is sometimes referred as the LCD operating voltage. PCF85134_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 17 December 2009 8 of 40 PCF85134 NXP Semiconductors Universal LCD driver for low multiplex rates 7.4 LCD drive mode waveforms 7.4.1 Static drive mode The static LCD drive mode is used when a single backplane is provided in the LCD. Backplane and segment drive waveforms for this mode are shown in Figure 4. Tfr LCD segments VLCD BP0 VSS state 1 (on) VLCD state 2 (off) Sn VSS VLCD Sn+1 VSS (a) Waveforms at driver. VLCD state 1 0V −VLCD VLCD state 2 0V −VLCD (b) Resultant waveforms at LCD segment. 013aaa207 Vstate1(t) = VSn(t) − VBP0(t). Von(RMS) = VLCD. Vstate2(t) = V(Sn + 1)(t) − VBP0(t). Voff(RMS) = 0 V. Fig 4. Static drive mode waveforms PCF85134_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 17 December 2009 9 of 40 PCF85134 NXP Semiconductors Universal LCD driver for low multiplex rates 7.4.2 1:2 Multiplex drive mode When two backplanes are provided in the LCD, the 1:2 multiplex mode applies. The PCF85134 allows the use of 1⁄2 bias or 1⁄3 bias in this mode as shown in Figure 5 and Figure 6. Tfr VLCD BP0 LCD segments VLCD/2 VSS state 1 VLCD BP1 state 2 VLCD/2 VSS VLCD Sn VSS VLCD Sn+1 VSS (a) Waveforms at driver. VLCD VLCD/2 state 1 0V −VLCD/2 −VLCD VLCD VLCD/2 state 2 0V −VLCD/2 −VLCD (b) Resultant waveforms at LCD segment. 013aaa208 Vstate1(t) = VSn(t) − VBP0(t). Von(RMS) = 0.791VLCD. Vstate2(t) = VSn(t) − VBP1(t). Voff(RMS) = 0.354VLCD. Fig 5. Waveforms for the 1:2 multiplex drive mode with 1⁄2 bias PCF85134_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 17 December 2009 10 of 40 PCF85134 NXP Semiconductors Universal LCD driver for low multiplex rates Tfr BP0 BP1 Sn Sn+1 VLCD 2VLCD/3 LCD segments VLCD/3 VSS state 1 VLCD 2VLCD/3 state 2 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS (a) Waveforms at driver. VLCD 2VLCD/3 VLCD/3 state 1 0V −VLCD/3 −2VLCD/3 −VLCD VLCD 2VLCD/3 VLCD/3 state 2 0V −VLCD/3 −2VLCD/3 −VLCD (b) Resultant waveforms at LCD segment. 013aaa209 Vstate1(t) = VSn(t) − VBP0(t). Von(RMS) = 0.745VLCD. Vstate2(t) = VSn(t) − VBP1(t). Voff(RMS) = 0.333VLCD. Fig 6. Waveforms for the 1:2 multiplex drive mode with 1⁄3 bias PCF85134_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 17 December 2009 11 of 40 PCF85134 NXP Semiconductors Universal LCD driver for low multiplex rates 7.4.3 1:3 Multiplex drive mode When three backplanes are provided in the LCD, the 1:3 multiplex drive mode applies, as shown in Figure 7. Tfr BP0 BP1 BP2 Sn Sn+1 Sn+2 VLCD 2VLCD/3 LCD segments VLCD/3 VSS state 1 VLCD 2VLCD/3 state 2 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS (a) Waveforms at driver. VLCD 2VLCD/3 VLCD/3 state 1 0V −VLCD/3 −2VLCD/3 −VLCD VLCD 2VLCD/3 VLCD/3 state 2 0V −VLCD/3 −2VLCD/3 −VLCD (b) Resultant waveforms at LCD segment. 013aaa210 Vstate1(t) = VSn(t) − VBP0(t). Von(RMS) = 0.638VLCD. Vstate2(t) = VSn(t) − VBP1(t). Voff(RMS) = 0.333VLCD. Fig 7. Waveforms for the 1:3 multiplex drive mode with 1⁄3 bias PCF85134_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 17 December 2009 12 of 40 PCF85134 NXP Semiconductors Universal LCD driver for low multiplex rates 7.4.4 1:4 Multiplex drive mode When four backplanes are provided in the LCD, the 1:4 multiplex drive mode applies, as shown in Figure 8. Tfr BP0 VLCD 2VLCD/3 VLCD/3 VSS BP1 VLCD 2VLCD/3 VLCD/3 VSS BP2 VLCD 2VLCD/3 VLCD/3 VSS BP3 VLCD 2VLCD/3 VLCD/3 VSS Sn VLCD 2VLCD/3 VLCD/3 VSS Sn+1 VLCD 2VLCD/3 VLCD/3 VSS Sn+2 VLCD 2VLCD/3 VLCD/3 VSS Sn+3 VLCD 2VLCD/3 VLCD/3 VSS state 1 VLCD 2VLCD/3 VLCD/3 0V −VLCD/3 −2VLCD/3 −VLCD state 2 VLCD 2VLCD/3 VLCD/3 0V −VLCD/3 −2VLCD/3 −VLCD LCD segments state 1 state 2 (a) Waveforms at driver. (b) Resultant waveforms at LCD segment. 013aaa211 Vstate1(t) = VSn(t) − VBP0(t). Von(RMS) = 0.577VLCD. Vstate2(t) = VSn(t) − VBP1(t). Voff(RMS) = 0.333VLCD. Fig 8. Waveforms for the 1:4 multiplex drive mode with 1⁄3 bias PCF85134_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 17 December 2009 13 of 40 PCF85134 NXP Semiconductors Universal LCD driver for low multiplex rates 7.5 Oscillator The internal logic and the LCD drive signals of the PCF85134 are timed by the frequency fclk, which equals either the built-in oscillator frequency fosc or the external clock frequency fclk(ext). The clock frequency fclk determines the LCD frame frequency (ffr). 7.5.1 Internal clock The internal oscillator is enabled by connecting pin OSC to pin VSS. In this case, the output from pin CLK is the clock signal for any cascaded PCF85134 in the system. 7.5.2 External clock Connecting pin OSC to VDD enables an external clock source. Pin CLK becomes the external clock input. A clock signal must always be supplied to the device; removing the clock may freeze the LCD in a DC state, which is not suitable for the liquid crystal. 7.6 Timing and frame frequency The timing of the PCF85134 organizes the internal data flow of the device. This includes the transfer of display data from the display RAM to the display segment outputs. In cascaded applications, the synchronization signal (SYNC) maintains the correct timing relationship between all the PCF85134 in the system. The timing also generates the LCD frame frequency which is derived as an integer division of the clock frequency (see Table 6). The frame frequency is a fixed division of the internal clock or of the frequency applied to pad CLK when an external clock is used. Table 6. LCD frame frequencies Frame frequency Nominal frame frequency (Hz) f clk f fr = --------24 82 7.7 Display register The display register holds the display data while the corresponding multiplex signals are generated. There is a one-to-one relationship between the data in the display register, the LCD segment outputs, and one column of the display RAM. 7.8 Segment outputs The LCD drive section includes 60 segment outputs (S0 to S59) which must be connected directly to the LCD. The segment output signals are generated based on the multiplexed backplane signals and with data resident in the display register. When less than 60 segment outputs are required the unused segment outputs must be left open-circuit. PCF85134_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 17 December 2009 14 of 40 PCF85134 NXP Semiconductors Universal LCD driver for low multiplex rates 7.9 Backplane outputs The LCD drive section includes four backplane outputs: BP0 to BP3. The backplane output signals are generated based on the selected LCD drive mode. • In 1:4 multiplex drive mode: BP0 to BP3 must be connected directly to the LCD. If less than four backplane outputs are required the unused outputs can be left open-circuit. • In 1:3 multiplex drive mode: BP3 carries the same signal as BP1, therefore these two adjacent outputs can be tied together to give enhanced drive capabilities. • In 1:2 multiplex drive mode: BP0 and BP2, BP1 and BP3 respectively carry the same signals and can also be paired to increase the drive capabilities. • In static drive mode: The same signal is carried by all four backplane outputs; and they can be connected in parallel for very high drive requirements. 7.10 Display RAM The display RAM is a static 60 × 4 bit RAM which stores LCD data. A logic 1 in the RAM bit map indicates the on-state of the corresponding LCD element; similarly, a logic 0 indicates the off-state. There is a one-to-one correspondence between the RAM addresses and the segment outputs and between the individual bits of a RAM word and the backplane outputs. The display RAM bit map, Figure 9, shows rows 0 to 3 which correspond with the backplane outputs BP0 to BP3, and columns 0 to 59 which correspond with the segment outputs S0 to S59. In multiplexed LCD applications the segment data of the first, second, third, and fourth row of the display RAM are time-multiplexed with BP0, BP1, BP2, and BP3 respectively. columns display RAM addresses/segment outputs (S) 0 rows 1 2 3 4 55 56 57 58 59 0 display RAM rows/ backplane outputs 1 (BP) 2 3 013aaa212 The display RAM bit map shows the direct relationship between the display RAM addresses and the segment outputs and between the bits in a RAM word and the backplane outputs. Fig 9. Display RAM bit map When display data is transmitted to the PCF85134, the received display bytes are stored in the display RAM in accordance with the selected LCD drive mode. The data is stored as it arrives and does not wait for the acknowledge cycle as with the commands. Depending on the current multiplex drive mode, data is stored singularly, in pairs, triples, or quadruples. To illustrate the filling order, an example of a 7-segment display showing all drive modes is given in Figure 10; the RAM filling organization depicted applies equally to other LCD types. PCF85134_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 17 December 2009 15 of 40 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx LCD segments Sn+2 Sn+3 static display RAM filling order b f Sn+1 BP0 rows display RAM 0 rows/backplane 1 outputs (BP) 2 3 g e Sn+6 Sn Sn+7 c DP d n n+1 n+2 n+3 n+4 n+5 n+6 n+7 c x x x b x x x a x x x f x x x g x x x e x x x d x x x DP x x x Sn Sn+1 a b f g Sn+2 BP1 e Sn+3 c Sn+1 1:3 Sn+2 DP d b f Sn multiplex BP1 c b f BP0 g multiplex 16 of 40 © NXP B.V. 2009. All rights reserved. Sn+1 BP1 c d g e d DP n n+1 n+2 n+3 a b x x f g x x e c x x d DP x x MSB a b LSB f g e c d DP n rows display RAM 0 b rows/backplane 1 DP outputs (BP) 2 c 3 x n+1 n+2 a d g x f e x x MSB LSB b DP c a d g f e DP BP2 n rows display RAM 0 a rows/backplane 1 c BP3 outputs (BP) 2 b 3 DP n+1 f e g d MSB a c b DP f LSB e g d 001aaj646 x = data bit unchanged. Fig 10. Relationship between LCD layout, drive mode, display RAM storage order and display data transmitted over the I2C-bus PCF85134 e f columns display RAM address/segment outputs (s) byte1 byte2 byte3 byte4 byte5 a Sn 1:4 BP2 DP d c b a columns display RAM address/segment outputs (s) byte1 byte2 byte3 g e rows display RAM 0 rows/backplane 1 outputs (BP) 2 3 BP0 a LSB Universal LCD driver for low multiplex rates Rev. 01 — 17 December 2009 multiplex MSB columns display RAM address/segment outputs (s) byte1 byte2 BP0 1:2 transmitted display byte columns display RAM address/segment outputs (s) byte1 a Sn+4 Sn+5 LCD backplanes NXP Semiconductors PCF85134_1 Product data sheet drive mode PCF85134 NXP Semiconductors Universal LCD driver for low multiplex rates The following applies to Figure 10: • In static drive mode the eight transmitted data bits are placed into row 0 of eight successive 4-bit RAM words. • In 1:2 multiplex mode the eight transmitted data bits are placed in pairs into row 0 and 1 of four successive 4-bit RAM words. • In 1:3 multiplex mode the eight bits are placed in triples into row 0, 1, and 2 of three successive 4-bit RAM words, with bit 3 of the third address left unchanged. It is not recommended to use this bit in a display because of the difficult addressing. This last bit may, if necessary, be controlled by an additional transfer to this address, but care should be taken to avoid overwriting adjacent data because always full bytes are transmitted. • In the 1:4 multiplex mode the eight transmitted data bits are placed in quadruples into row 0, 1, 2, and 3 of two successive 4-bit RAM words. 7.11 Data pointer The addressing mechanism for the display RAM is realized using the data pointer. This allows the loading of an individual display data byte, or a series of display data bytes, into any location of the display RAM. The sequence commences with the initialization of the data pointer by the load-data-pointer command (see Table 9). Following this command, an arriving data byte is stored at the display RAM address indicated by the data pointer. The filling order is shown in Figure 10. After each byte is stored, the content of the data pointer is automatically incremented by a value dependent on the selected LCD drive mode: • • • • In static drive mode by eight. In 1:2 multiplex drive mode by four. In 1:3 multiplex drive mode by three. In 1:4 multiplex drive mode by two. If an I2C-bus data access terminates early, the state of the data pointer is unknown. Consequently, the data pointer must be rewritten prior to further RAM accesses. 7.12 Subaddress counter The storage of display data is conditioned by the content of the subaddress counter. Storage is allowed only when the content of the subaddress counter match with the hardware subaddress applied to A0, A1 and A2. The subaddress counter value is defined by the device-select command (see Table 12). If the content of the subaddress counter and the hardware subaddress do not match, then data storage is inhibited but the data pointer is incremented as if data storage had taken place. The subaddress counter is also incremented when the data pointer overflows. In cascaded applications each PCF85134 in the cascade must be addressed separately. Initially, the first PCF85134 is selected by sending the device-select command matching the first device's hardware subaddress. Then the data pointer is set to the preferred display RAM address by sending the load-data-pointer command. PCF85134_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 17 December 2009 17 of 40 PCF85134 NXP Semiconductors Universal LCD driver for low multiplex rates Once the display RAM of the first PCF85134 has been written, the second PCF85134 is selected by sending the device-select command again. This time however the command matches the second device's hardware subaddress. Next the load-data-pointer command is sent to select the preferred display RAM address of the second PCF85134. This last step is very important because during writing data to the first PCF85134, the data pointer of the second PCF85134 is incremented. In addition, the hardware subaddress should not be changed whilst the device is being accessed on the I2C-bus interface. 7.13 Output bank selector The output bank selector (see Table 13) selects one of the four rows per display RAM address for transfer to the display register. The actual row selected depends on the particular LCD drive mode in operation and on the instant in the multiplex sequence. • In 1:4 multiplex mode, all RAM addresses of row 0 are selected, these are followed by the contents of row 1, 2, and then 3 • In 1:3 multiplex mode, rows 0, 1, and 2 are selected sequentially • In 1:2 multiplex mode, rows 0 and 1 are selected • In static mode, row 0 is selected The SYNC signal resets these sequences to the following starting points: bit 3 for 1:4 multiplex, bit 2 for 1:3 multiplex, bit 1 for 1:2 multiplex, and bit 0 for static mode. The PCF85134 includes a RAM bank switching feature in the static and 1:2 multiplex drive modes. In the static drive mode, the bank-select command may request the contents of row 2 to be selected for display instead of the contents of row 0. In the 1:2 mode, the contents of rows 2 and 3 may be selected instead of rows 0 and 1. This gives the provision for preparing display information in an alternative bank and to be able to switch to it, once it is assembled. 7.14 Input bank selector The input bank selector loads display data into the display RAM in accordance with the selected LCD drive configuration. Display data can be loaded in row 2 in static drive mode or in rows 2 and 3 in 1:2 multiplex drive mode by using the bank-select command. The input bank selector functions independently to the output bank selector. 7.15 Blinker The display blink capabilities of the PCF85134 are very versatile. The whole display can blink at frequencies selected by the blink-select command (see Table 14). The blink frequencies are fractions of the clock frequency. The ratios between the clock and blink frequencies depend on the blink mode selected (see Table 7). PCF85134_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 17 December 2009 18 of 40 PCF85134 NXP Semiconductors Universal LCD driver for low multiplex rates Table 7. Blink frequencies Blink mode Operating mode ratio Blink frequency with respect to fclk (typical) Unit fclk = 1.970 kHz off - blinking off Hz 1 f clk --------768 2.5 Hz 2 f clk -----------1536 1.3 Hz 3 f clk -----------3072 0.6 Hz An additional feature is for an arbitrary selection of LCD segments to blink. This applies to the static and 1:2 multiplex drive modes and can be implemented without any communication overheads. By means of the output bank selector, the displayed RAM banks are exchanged with alternate RAM banks at the blink frequency. This mode can also be specified by the blink-select command. In the 1:3 and 1:4 multiplex modes, where no alternate RAM bank is available, groups of LCD segments can blink by selectively changing the display RAM data at fixed time intervals. The entire display can blink at a frequency other then the nominal blink frequency. This can be effectively performed by resetting and setting the display enable bit E at the required rate using the mode-set command (see Table 10). PCF85134_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 17 December 2009 19 of 40 PCF85134 NXP Semiconductors Universal LCD driver for low multiplex rates 8. Basic architecture 8.1 Characteristics of the I2C-bus The I2C-bus is for bidirectional, two-line communication between different ICs or modules. The two lines are a Serial Data line (SDA) and a Serial Clock Line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy. 8.1.1 Bit transfer One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as a control signal. Bit transfer is illustrated in Figure 11. SDA SCL data line stable; data valid change of data allowed mba607 Fig 11. Bit transfer 8.1.1.1 START and STOP conditions Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW change of the data line, while the clock is HIGH, is defined as the START condition (S). A LOW-to-HIGH change of the data line, while the clock is HIGH, is defined as the STOP condition (P). The START and STOP conditions are illustrated in Figure 12. SDA SDA SCL SCL S P START condition STOP condition mbc622 Fig 12. Definition of START and STOP conditions 8.1.2 System configuration A device generating a message is a transmitter, a device receiving a message is the receiver. The device that controls the message is the master; and the devices which are controlled by the master are the slaves. The system configuration is shown in Figure 13. PCF85134_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 17 December 2009 20 of 40 PCF85134 NXP Semiconductors Universal LCD driver for low multiplex rates MASTER TRANSMITTER/ RECEIVER SLAVE TRANSMITTER/ RECEIVER SLAVE RECEIVER MASTER TRANSMITTER/ RECEIVER MASTER TRANSMITTER SDA SCL mga807 Fig 13. System configuration 8.1.3 Acknowledge The number of data bytes transferred between the START and STOP conditions from transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge cycle. • A slave receiver, which is addressed, must generate an acknowledge after the reception of each byte. • A master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. • The device that acknowledges must pull-down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse (set-up and hold times must be taken into consideration). • A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a STOP condition. Acknowledgement on the I2C-bus is illustrated in Figure 14. data output by transmitter not acknowledge data output by receiver acknowledge SCL from master 1 2 8 9 S START condition clock pulse for acknowledgement mbc602 Fig 14. Acknowledgement of the I2C-bus PCF85134_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 17 December 2009 21 of 40 PCF85134 NXP Semiconductors Universal LCD driver for low multiplex rates 8.1.4 I2C-bus controller The PCF85134 acts as an I2C-bus slave receiver. It does not initiate I2C-bus transfers or transmit data to an I2C-bus master receiver. The only data output from the PCF85134 are the acknowledge signals of the selected devices. Device selection depends on the I2C-bus slave address, the transferred command data and the hardware subaddress. In single device applications, the hardware subaddress inputs A0, A1, and A2 are normally tied to VSS which defines the hardware subaddress 0. In multiple device applications A0, A1, and A2 are tied to VSS or VDD using a binary coding scheme, so that no two devices with a common I2C-bus slave address have the same hardware subaddress. 8.1.5 Input filters To enhance noise immunity in electrically adverse environments, RC low-pass filters are provided on the SDA and SCL lines. 8.2 I2C-bus protocol Two I2C-bus slave addresses (0111 000 and 0111 001) are reserved for the PCF85134. The least significant bit of the slave address is bit R/W. The PCF85134 is a write-only device. It will not respond to a read access, so this bit should always be logic 0. The second bit of the slave address is defined by the level tied at input SA0. Two displays controlled by PCF85134 can be recognized on the same I2C-bus which allows: • Up to 16 PCF85134s on the same I2C-bus for very large LCD applications • The use of two types of LCD multiplex drive mode on the same I2C-bus The I2C-bus protocol is shown in Figure 15. The sequence is initiated with a START condition (S) from the I2C-bus master which is followed by one of the available PCF85134 slave addresses. All PCF85134s with the same SA0 level acknowledge in parallel to the slave address. All PCF85134s with the alternative SA0 level ignore the whole I2C-bus transfer. PCF85134_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 17 December 2009 22 of 40 PCF85134 NXP Semiconductors Universal LCD driver for low multiplex rates R/W = 0 slave address control byte S C R S 0 1 1 1 0 0 A 0 A O S 0 RAM/command byte M A S B L S P B EXAMPLES a) transmit two bytes of RAM data S S 0 1 1 1 0 0 A 0 A 0 1 0 RAM DATA A RAM DATA A A COMMAND A 0 0 A COMMAND A P A COMMAND A 0 1 A RAM DATA A A P b) transmit two command bytes S S 0 1 1 1 0 0 A 0 A 1 0 0 c) transmit one command byte and two RAM date bytes S S 0 1 1 1 0 0 A 0 A 1 0 0 RAM DATA A P mgl752 Fig 15. I2C-bus protocol After acknowledgement, the control byte is sent defining if the next byte is a RAM or command information. The control byte also defines if the next byte is a control byte or further RAM or command data (see Figure 16 and Table 8). In this way it is possible to configure the device and then fill the display RAM with little overhead. MSB 7 6 5 CO RS 4 3 2 LSB 0 1 not relevant mgl753 Fig 16. Control byte format Table 8. Control byte description Bit Symbol 7 CO 6 Value continue bit 0 last control byte 1 control bytes continue RS register selection 0 1 5 to 0 - Description command register data register not relevant The command bytes and control bytes are also acknowledged by all addressed PCF85134s connected to the bus. The display bytes are stored in the display RAM at the address specified by the data pointer and the subaddress counter. Both data pointer and subaddress counter are automatically updated. PCF85134_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 17 December 2009 23 of 40 PCF85134 NXP Semiconductors Universal LCD driver for low multiplex rates The acknowledgement after each byte is made only by the (A0, A1, and A2) addressed PCF85134. After the last display byte, the I2C-bus master issues a STOP condition (P). Alternatively a START may be issued to RESTART I2C-bus access. 8.3 Command decoder The command decoder identifies command bytes that arrive on the I2C-bus. There are five commands: Table 9. Definition of commands Command Operation code Reference Bit 7 6 5 4 3 2 1 Mode-set 1 1 0 0 E B M[1:0] Load-data-pointer 0 P[6:0] Device-select 1 1 1 0 0 A[2:0] Bank-select 1 1 1 1 1 0 I Blink-select 1 1 1 1 0 A BF[1:0] Mode-set command bit description Bit Symbol Value Description 7 to 4 - 1100 fixed value 3 E [1] Table 12 O Table 13 Table 14 display status 0 disabled (blank)[1] 1 enable B 1 to 0 Table 10 Table 11 Table 10. 2 0 LCD bias configuration 0 1⁄ 3 bias 1 1⁄ 2 bias M[1:0] LCD drive mode selection 01 static; 1 backplane 10 1:2 multiplex; 2 backplanes 11 1:3 multiplex; 3 backplanes 00 1:4 multiplex; 4 backplanes The possibility to disable the display allows implementation of blinking under external control. Table 11. Load-data-pointer command bit description See Section 7.11. Bit Symbol Value Description 7 - 0 fixed value 6 to 0 P[6:0] 0000000 to 0111011 7-bit binary value of 0 to 59 Table 12. Device-select command bit description See Section 7.12. Bit Symbol Value Description 7 to 3 - 11100 fixed value 2 to 0 A[2:0] 000 to 111 3-bit binary value of 0 to 7 PCF85134_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 17 December 2009 24 of 40 PCF85134 NXP Semiconductors Universal LCD driver for low multiplex rates Table 13. Bank-select command bit description See Section 7.10, Section 7.11, Section 7.12, Section 7.13 and Section 7.14. Bit Symbol Value Description Static 7 to 2 - 1 I 111110 fixed value input bank selection: storage of arriving display data 0 1 0 [1] 1:2 multiplex[1] O RAM row 0 RAM rows 0 and 1 RAM row 2 RAM rows 2 and 3 output bank selection: retrieval of LCD display data 0 RAM row 0 RAM rows 0 and 1 1 RAM row 2 RAM rows 2 and 3 The bank-select command has no effect in 1:3 or 1:4 multiplex drive modes. Table 14. Blink-select command bit description See Section 7.15. Bit Symbol Value Description 7 to 3 - 11110 fixed value 2 A 1 to 0 blink mode selection 0 normal blinking[1] 1 blinking by alternating display RAM banks BF[1:0] blink frequency selection 00 off 01 1 10 2 11 3 [1] Normal blinking can only be selected in multiplex drive mode 1:3 or 1:4. [2] For the blink frequencies, see Table 7. 8.4 Display controller The display controller executes the commands identified by the command decoder. It contains the status registers of the PCF85134 and coordinates their effects. The controller also loads display data into the display RAM as required by the storage order. PCF85134_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 17 December 2009 25 of 40 PCF85134 NXP Semiconductors Universal LCD driver for low multiplex rates 9. Internal circuitry VDD VDD VSS VSS SA0 VDD CLK SCL VSS VDD VSS OSC VSS VDD SDA SYNC VSS VSS VDD A0, A1, A2 VLCD VSS VLCD VSS BP0, BP1, BP2, BP3 VSS VLCD S0 to S59 VSS 001aah615 Fig 17. Device protection diagram PCF85134_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 17 December 2009 26 of 40 PCF85134 NXP Semiconductors Universal LCD driver for low multiplex rates 10. Limiting values CAUTION Static voltages across the liquid crystal display can build up when the LCD supply voltage (VLCD) is on while the IC supply voltage (VDD) is off, or vice versa. This may cause unwanted display artifacts. To avoid such artifacts, VLCD and VDD must be applied or removed together. Table 15. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134).[1] Symbol Parameter VDD IDD Min Max supply voltage −0.5 +6.5 V supply current −50 +50 mA VLCD LCD supply voltage −0.5 +7.5 V IDD(LCD) LCD supply current −50 +50 mA ISS ground supply current −50 +50 mA VI input voltage [2] −0.5 +6.5 V input current [2] −10 +10 mA output voltage [2] −0.5 +6.5 V [3] −0.5 +7.5 V −10 +10 mA - 400 mW II VO Conditions IO output current Ptot total power dissipation P/out power dissipation per output VESD Ilu Tstg [2][3] - 100 mW HBM [4] - ±2500 V MM [5] - ±200 V latch-up current [6] - 200 mA storage temperature [7] −65 +150 °C electrostatic discharge voltage [1] Stresses above these values listed may cause permanent damage to the device. [2] Pins SDA, SCL, CLK, SYNC, SA0, OSC and A0 to A2. [3] Pins S0 to S59 and BP0 to BP3. [4] HBM: Human Body Model, according to Ref. 5 “JESD22-A114”. [5] MM: Machine Model, according to Ref. 6 “JESD22-A115”. [6] Pass level; latch-up testing according to Ref. 7 “JESD78” at maximum ambient temperature (Tamb(max) = +85 °C). [7] According to the NXP store and transport requirements (see Ref. 9 “NX3-00092”) the devices have to be stored at a temperature of +8 °C to +45 °C and a humidity of 25 % to 75 %. For long term storage products deviant conditions are described in that document. PCF85134_1 Product data sheet Unit © NXP B.V. 2009. All rights reserved. Rev. 01 — 17 December 2009 27 of 40 PCF85134 NXP Semiconductors Universal LCD driver for low multiplex rates 11. Static characteristics Table 16. Static characteristics VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 2.5 V to 6.5 V; Tamb = −40 °C to +85 °C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Supplies VDD supply voltage 1.8 - 5.5 V VLCD LCD supply voltage 2.5 - 6.5 V fclk(ext) = 1536 Hz [1] - 8 20 µA fclk(ext) = 1536 Hz [1] - 24 60 µA supply current IDD IDD(LCD) LCD supply current Logic VSS − 0.5 - VDD + 0.5 V on pins CLK, SYNC, OSC, A0 to A2 and SA0 VSS - 0.3VDD V on pins CLK, SYNC, OSC, A0 to A2 and SA0 0.7VDD - VDD V VI input voltage VIL LOW-level input voltage VIH HIGH-level input voltage VPOR power-on reset voltage 1.0 1.3 1.6 V IOL LOW-level output current output sink current; VOL = 0.4 V; VDD = 5 V; on pins CLK and SYNC 1 - - mA IOH HIGH-level output current output source current; VOH = 4.6 V; VDD = 5 V; on pin CLK 1 - - mA IL leakage current VI = VDD or VSS; on pins SA0, A0 to A2 and CLK −1 - +1 µA −1 - +1 µA - - 7 pF VSS − 0.5 - 5.5 V pin SCL VSS - 0.3VDD V pin SDA VI = VDD; on pin OSC [2] input capacitance CI I2C-bus; pins SDA and SCL VI input voltage VIL LOW-level input voltage VSS - 0.2VDD V VIH HIGH-level input voltage 0.7VDD - 5.5 V IOL LOW-level output current output sink current; VOL = 0.4 V; VDD = 5 V; on pin SDA 3 - - mA IL leakage current Ci input capacitance −1 - +1 µA [2] - - 7 pF VI = VDD or VSS LCD outputs Output pins BP0 to BP3 VBP voltage on pin BP Cbpl = 35 nF [3] −100 - +100 mV RBP resistance on pin BP VLCD = 5 V [4] - 1.5 10 kΩ Csgm = 35 nF [5] −100 - +100 mV VLCD = 5 V [4] - 6.0 13.5 kΩ Output pins S0 to S59 voltage on pin S VS resistance on pin S RS [1] LCD outputs are open-circuit; inputs at VSS or VDD; external clock with 50 % duty factor; I2C-bus inactive. [2] Not tested, design specification only. [3] Cbpl = backplane capacitance. [4] Measured on sample basis only. [5] Csgm = segment capacitance. PCF85134_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 17 December 2009 28 of 40 PCF85134 NXP Semiconductors Universal LCD driver for low multiplex rates 12. Dynamic characteristics Table 17. Dynamic characteristics VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 2.5 V to 6.5 V; Tamb = −40 °C to +85 °C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit 1440 1970 2640 Hz 800 - 3600 Hz Clock Internal: output pin CLK oscillator frequency fosc VDD = 5 V [1] External: input pin CLK fclk(ext) external clock frequency VDD = 5 V tclk(H) HIGH-level clock time 130 - - µs tclk(L) LOW-level clock time 130 - - µs Synchronization: input pin SYNC tPD(SYNC_N) SYNC propagation delay - 30 - ns tSYNC_NL SYNC LOW time 1 - - µs - - 30 µs Outputs: pins BP0 to BP3 and S0 to S59 tPD(drv) I2C-bus: driver propagation delay VLCD = 5 V timing[2] Pin SCL fSCL SCL frequency - - 400 kHz tLOW LOW period of the SCL clock 1.3 - - µs tHIGH HIGH period of the SCL clock 0.6 - - µs tSU;DAT data set-up time 100 - - ns tHD;DAT data hold time 0 - - ns Pin SDA Pins SCL and SDA tBUF bus free time between a STOP and START condition 1.3 - - µs tSU;STO set-up time for STOP condition 0.6 - - µs tHD;STA hold time (repeated) START condition 0.6 - - µs tSU;STA set-up time for a repeated START condition 0.6 - - µs tr rise time of both SDA and SCL signals - - 0.3 µs tf fall time of both SDA and SCL signals - - 0.3 µs Cb capacitive load for each bus line - - 400 pF tw(spike) spike pulse width - - 50 ns [1] Typical output (duty cycle δ = 50 %). [2] All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to VIL and VIH with an input voltage swing of VSS to VDD. PCF85134_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 17 December 2009 29 of 40 PCF85134 NXP Semiconductors Universal LCD driver for low multiplex rates 1 / fclk tclk(H) tclk(L) 0.7VDD CLK 0.3VDD 0.7VDD SYNC 0.3VDD tPD(SYNC_N) tPD(SYNC_N) tSYNC_NL 0.5 V BP0 to BP3, and S0 to S59 (VDD = 5 V) 0.5 V tPD(drv) 001aah618 Fig 18. Driver timing waveforms SDA tBUF tLOW tf SCL tHD;STA tr tHD;DAT tHIGH tSU;DAT SDA tSU;STA tSU;STO mga728 Fig 19. I2C-bus timing waveforms PCF85134_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 17 December 2009 30 of 40 PCF85134 NXP Semiconductors Universal LCD driver for low multiplex rates 13. Application information 13.1 Cascaded operation Large display configurations of up to 16 PCF85134 can be recognized on the same I2C-bus by using the 3-bit hardware subaddress (A0, A1, and A2) and the programmable I2C-bus slave address (SA0). Table 18. Addressing cascaded PCF85134 Cluster Bit SA0 Pin A2 Pin A1 Pin A0 Device 1 0 0 0 0 0 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 4 1 0 1 5 1 1 0 6 1 1 1 7 0 0 0 8 0 0 1 9 0 1 0 10 0 1 1 11 1 0 0 12 1 0 1 13 1 1 0 14 1 1 1 15 2 1 When cascaded PCF85134 are synchronized, they can share the backplane signals from one of the devices in the cascade. Such an arrangement is cost-effective in large LCD applications since the backplane outputs of only one device need to be through-plated to the backplane electrodes of the display. The other PCF85134 of the cascade contribute additional segment outputs, but their backplane outputs are left open-circuit (see Figure 20). PCF85134_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 17 December 2009 31 of 40 PCF85134 NXP Semiconductors Universal LCD driver for low multiplex rates VDD VLCD SDA 60 segment drives SCL PCF85134 SYNC CLK BP0 to BP3 (open-circuit) OSC A0 A1 A2 SA0 VSS LCD PANEL VLCD VDD R≤ HOST MICROPROCESSOR/ MICROCONTROLLER tr 2Cb VDD VLCD 60 segment drives SDA SCL SYNC PCF85134 BP0 to BP3 OSC VSS 4 backplanes CLK A0 A1 A2 SA0 VSS 013aaa213 Fig 20. Cascaded PCF85134 configuration The SYNC line is provided to maintain the correct synchronization between all cascaded PCF85134. Synchronization is guaranteed after a power-on reset. The only time that SYNC is likely to be needed is if synchronization is accidentally lost (e.g. by noise in adverse electrical environments or by defining a multiplex drive mode when PCF85134 with different SA0 levels are cascaded). SYNC is organized as an input/output pin. The output selection is realized as an open-drain driver with an internal pull-up resistor. A PCF85134 asserts the SYNC line at the onset of its last active backplane signal and monitors the SYNC line at all other times. If synchronization in the cascade is lost, it is restored by the first PCF85134 to assert SYNC. The timing relationship between the backplane waveforms and the SYNC signal for the various drive modes of the PCF85134 are shown in Figure 21. PCF85134_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 17 December 2009 32 of 40 PCF85134 NXP Semiconductors Universal LCD driver for low multiplex rates Tfr = 1 ffr BP0 SYNC (a) static drive mode. BP0 (1/2 bias) BP0 (1/3 bias) SYNC (b) 1:2 multiplex drive mode. BP0 (1/3 bias) SYNC (c) 1:3 multiplex drive mode. BP0 (1/3 bias) SYNC (d) 1:4 multiplex drive mode. mgl755 Fig 21. Synchronization of the cascade for various PCF85134 drive modes The contact resistance between the SYNC pins of cascaded devices must be controlled. If the resistance is too high, the device will not be able to synchronize properly. Table 19 shows the maximum contact resistance values. Table 19. SYNC contact resistance Number of devices Maximum contact resistance 2 6000 Ω 3 to 5 2200 Ω 6 to 10 1200 Ω 11 to 16 700 Ω PCF85134_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 17 December 2009 33 of 40 PCF85134 NXP Semiconductors Universal LCD driver for low multiplex rates 14. Package outline LQFP80: plastic low profile quad flat package; 80 leads; body 12 x 12 x 1.4 mm SOT315-1 c y X A 60 41 40 Z E 61 e E HE A A2 (A 3) A1 w M θ bp Lp L pin 1 index 80 21 1 detail X 20 ZD e v M A w M bp D B HD v M B 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e mm 1.6 0.16 0.04 1.5 1.3 0.25 0.27 0.13 0.18 0.12 12.1 11.9 12.1 11.9 0.5 HD HE 14.15 14.15 13.85 13.85 L Lp v w y 1 0.75 0.30 0.2 0.15 0.1 Z D (1) Z E (1) θ 1.45 1.05 7o o 0 1.45 1.05 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT315-1 136E15 MS-026 JEITA EUROPEAN PROJECTION ISSUE DATE 00-01-19 03-02-25 Fig 22. Package outline SOT315-1 (LQFP80) PCF85134_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 17 December 2009 34 of 40 PCF85134 NXP Semiconductors Universal LCD driver for low multiplex rates 15. Handling information All input and output pins are protected against ElectroStatic Discharge (ESD) under normal handling. When handling Metal-Oxide Semiconductor (MOS) devices ensure that all normal precautions are taken as described in JESD625-A, IEC 61340-5 or equivalent standards. 16. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 16.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 16.2 Wave and reflow soldering Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: • Through-hole components • Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are: • • • • • • Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering PCF85134_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 17 December 2009 35 of 40 PCF85134 NXP Semiconductors Universal LCD driver for low multiplex rates 16.3 Wave soldering Key characteristics in wave soldering are: • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities 16.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 23) than a SnPb process, thus reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 20 and 21 Table 20. SnPb eutectic process (from J-STD-020C) Package thickness (mm) Package reflow temperature (°C) Volume (mm3) < 350 ≥ 350 < 2.5 235 220 ≥ 2.5 220 220 Table 21. Lead-free process (from J-STD-020C) Package thickness (mm) Package reflow temperature (°C) Volume (mm3) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245 Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 23. PCF85134_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 17 December 2009 36 of 40 PCF85134 NXP Semiconductors Universal LCD driver for low multiplex rates maximum peak temperature = MSL limit, damage level temperature minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 23. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. 17. Abbreviations Table 22. Abbreviations Acronym Description CMOS Complementary Metal-Oxide Semiconductor ESD ElectroStatic Discharge HBM Human Body Model IC Integrated Circuit LCD Liquid Crystal Display MM Machine Model RAM Random Access Memory PCF85134_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 17 December 2009 37 of 40 PCF85134 NXP Semiconductors Universal LCD driver for low multiplex rates 18. References [1] AN10365 — Surface mount reflow soldering description [2] IEC 60134 — Rating systems for electronic tubes and valves and analogous semiconductor devices [3] IEC 61340-5 — Protection of electronic devices from electrostatic phenomena [4] IPC/JEDEC J-STD-020D — Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices [5] JESD22-A114 — Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM) [6] JESD22-A115 — Electrostatic Discharge (ESD) Sensitivity Testing Machine Model (MM) [7] JESD78 — IC Latch-Up Test [8] JESD625-A — Requirements for Handling Electrostatic-Discharge-Sensitive (ESDS) Devices [9] NX3-00092 — NXP store and transport requirements [10] SNV-FA-01-02 — Marking Formats Integrated Circuits [11] UM10204 — I2C-bus specification and user manual 19. Revision history Table 23. Revision history Document ID Release date Data sheet status Change notice Supersedes PCF85134_1 20091217 Product data sheet - - PCF85134_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 17 December 2009 38 of 40 PCF85134 NXP Semiconductors Universal LCD driver for low multiplex rates 20. Legal information 20.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 20.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 20.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 20.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus — logo is a trademark of NXP B.V. 21. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] PCF85134_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 17 December 2009 39 of 40 PCF85134 NXP Semiconductors Universal LCD driver for low multiplex rates 22. Contents 1 2 3 4 5 6 6.1 6.2 7 7.1 7.2 7.3 7.4 7.4.1 7.4.2 7.4.3 7.4.4 7.5 7.5.1 7.5.2 7.6 7.7 7.8 7.9 7.10 7.11 7.12 7.13 7.14 7.15 8 8.1 8.1.1 8.1.1.1 8.1.2 8.1.3 8.1.4 8.1.5 8.2 8.3 8.4 9 10 11 12 13 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 Functional description . . . . . . . . . . . . . . . . . . . 6 Power-On Reset (POR) . . . . . . . . . . . . . . . . . . 6 LCD bias generator. . . . . . . . . . . . . . . . . . . . . . 7 LCD voltage selector . . . . . . . . . . . . . . . . . . . . 7 LCD drive mode waveforms . . . . . . . . . . . . . . . 9 Static drive mode . . . . . . . . . . . . . . . . . . . . . . . 9 1:2 Multiplex drive mode . . . . . . . . . . . . . . . . . 10 1:3 Multiplex drive mode . . . . . . . . . . . . . . . . . 12 1:4 Multiplex drive mode . . . . . . . . . . . . . . . . . 13 Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Internal clock. . . . . . . . . . . . . . . . . . . . . . . . . . 14 External clock . . . . . . . . . . . . . . . . . . . . . . . . . 14 Timing and frame frequency . . . . . . . . . . . . . . 14 Display register . . . . . . . . . . . . . . . . . . . . . . . . 14 Segment outputs. . . . . . . . . . . . . . . . . . . . . . . 14 Backplane outputs . . . . . . . . . . . . . . . . . . . . . 15 Display RAM . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Data pointer . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Subaddress counter . . . . . . . . . . . . . . . . . . . . 17 Output bank selector. . . . . . . . . . . . . . . . . . . . 18 Input bank selector . . . . . . . . . . . . . . . . . . . . . 18 Blinker. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Basic architecture . . . . . . . . . . . . . . . . . . . . . . 20 Characteristics of the I2C-bus . . . . . . . . . . . . . 20 Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 START and STOP conditions . . . . . . . . . . . . . 20 System configuration . . . . . . . . . . . . . . . . . . . 20 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 21 I2C-bus controller . . . . . . . . . . . . . . . . . . . . . . 22 Input filters . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 I2C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 22 Command decoder . . . . . . . . . . . . . . . . . . . . . 24 Display controller . . . . . . . . . . . . . . . . . . . . . . 25 Internal circuitry. . . . . . . . . . . . . . . . . . . . . . . . 26 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 27 Static characteristics. . . . . . . . . . . . . . . . . . . . 28 Dynamic characteristics . . . . . . . . . . . . . . . . . 29 Application information. . . . . . . . . . . . . . . . . . 31 13.1 14 15 16 16.1 16.2 16.3 16.4 17 18 19 20 20.1 20.2 20.3 20.4 21 22 Cascaded operation . . . . . . . . . . . . . . . . . . . . Package outline . . . . . . . . . . . . . . . . . . . . . . . . Handling information . . . . . . . . . . . . . . . . . . . Soldering of SMD packages . . . . . . . . . . . . . . Introduction to soldering. . . . . . . . . . . . . . . . . Wave and reflow soldering . . . . . . . . . . . . . . . Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . Legal information . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 34 35 35 35 35 36 36 37 38 38 39 39 39 39 39 39 40 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2009. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 17 December 2009 Document identifier: PCF85134_1