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SLES010D – SEPTEMBER 2001 – REVISED MAY 2004 FEATURES D Multilevel DAC Including Lineout Amplifier D Analog Performance (VCC1, VCC2 = 2.4 V): D D − Dynamic Range: 98 dB Typ − THD+N at 0 dB: 0.007% Typ 1.6-V to 3.6-V Single Power Supply Low Power Dissipation: 6 mW at VCC1, VCC2 = 2.4 V System Clock: 128 fS, 192 fS, 256 fS, 384 fS D D Sampling Frequency: 5 kHz to 50 kHz D Software Control (PCM1772): − − − − D 16-, 20-, 24-Bit Word Available Left-, Right-Justified, and I2S Slave/Master Selectable Digital Attenuation: 0 dB to –62 dB, 1 dB/Step − 44.1-kHz Digital De-Emphasis − Zero Cross Attenuation − Digital Soft Mute − Monaural Analog-In With Mixing − Monaural Speaker Mode Hardware Control (PCM1773): − Left-Justified and I2S − 44.1-kHz Digital De-Emphasis − Monaural Analog-In With Mixing D Pop-Noise-Free Circuit D 3.3-V Tolerant D Packages: TSSOP-16 and VQFN-20, Lead Free APPLICATIONS D Portable Audio Player D Cellular Phone D PDA D Other Applications Requiring Low-Voltage Operation DESCRIPTION The PCM1772 and PCM1773 devices are CMOS, monolithic, integrated circuits which include stereo digital-to-analog converters, lineout circuitry, and support circuitry in small TSSOP-16 and VQFN-20 packages. The data converters use TI’s enhanced multilevel ∆-Σ architecture, which employs noise shaping and multilevel amplitude quantization to achieve excellent dynamic performance and improved tolerance to clock jitter. The PCM1772 and PCM1773 devices accept several industry standard audio data formats with 16- to 24-bit data, left-justified, I2S, etc., providing easy interfacing to audio DSP and decoder devices. Sampling rates up to 50 kHz are supported. A full set of user-programmable functions are accessible through a 3-wire serial control port, which supports register write functions. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. ! " #$%! " &$'(#! )!%* )$#!" # ! "&%##!" &% !+% !%" %," "!$%!" "!)) -!.* )$#! &#%""/ )%" ! %#%""(. #($)% !%"!/ (( &%!%"* Copyright 2004, Texas Instruments Incorporated www.ti.com SLES010D – SEPTEMBER 2001 – REVISED MAY 2004 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. PACKAGE/ORDERING INFORMATION PRODUCT PACKAGE PACKAGE PACKAGE CODE OPERATION TEMPERATURE RANGE PACKAGE MARKING PCM1772PW 16-lead TSSOP 16PW –25°C to 85°C PCM1772 PCM1772RGA 20-lead VQFN 20RGA –25°C to 85°C PCM1772 PCM1773PW 16-lead TSSOP 16PW –25°C to 85°C PCM1773 PCM1773RGA 20-lead VQFN 20RGA –25°C to 85°C PCM1773 ORDERING NUMBER TRANSPORT MEDIA PCM1772PW Tube PCM1772PWR Tape and reel PCM1772RGA Tray PCM1772RGAR Tape and reel PCM1773PW Tube PCM1773PWR Tape and reel PCM1773RGA Tray PCM1773RGAR Tape and reel ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted(1) PCM1772 PCM1773 Supply voltage: VCC1, VCC2 Supply voltage differences: VCC1, VCC2 Ground voltage differences Digital input voltage Input current (any terminals except supplies) 4V ±0.1 V ±0.1 V –0.3 V to 4 V ±10 mA Operating temperature –40°C to 125°C Storage temperature –55°C to 150°C Junction temperature Lead temperature (soldering) 150°C 260°C, 5 s Package temperature (IR reflow, peak) 260°C (1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2 www.ti.com SLES010D – SEPTEMBER 2001 – REVISED MAY 2004 ELECTRICAL CHARACTERISTICS all specifications at TA = 25°C, VCC1 = VCC2 = 2.4 V, fS = 44.1 kHz, system clock = 256 fS and 24-bit data, RL = 10 kΩ, unless otherwise noted PARAMETER TEST CONDITIONS PCM1772PW, PCM1773PW, PCM1772RGA, PCM1773RGA MIN Resolution TYP UNIT MAX 24 Bits OPERATING FREQUENCY Sampling frequency (fS) 5 System clock frequency DIGITAL INPUT/OUTPUT(1)(2) VIH VIL IIH IIL VOH VOL 50 kHz 128 fS, 192 fS, 256 fS, 384 fS 0.7 VCC1 Input logic level Input logic current VIN = VCC1 VIN = 0 V Output logic level(3) IOH = –2 mA IOL = 2 mA Vdc 0.3 VCC1 Vdc 10 µA –10 0.7 VCC1 µA Vdc 0.3 VCC1 Vdc DYNAMIC PERFORMANCE (LINE OUTPUT) Full scale output voltage 0 dB Dynamic range EIAJ, A-weighted 90 0.75 VCC2 Signal-to-noise ratio EIAJ, A-weighted 90 THD+N 0 dB 98 0.007% Channel separation 70 Load resistance 10 VP-P dB 98 dB 0.015% 80 dB kΩ DC ACCURACY Gain error ±2 ±8 % of FSR Gain mismatch, channel-to-channel ±2 ±8 % of FSR ±30 ±75 mV Bipolar zero error VOUT = 0.5 VCC1 at BPZ ANALOG LINE INPUT (MIXING CIRCUIT) Analog input voltage range 0.584 VCC2 Gain (analog input to line output) Analog input impedance THD+N VP-P 0.91 10 AIN = 0.56 VCC2 (peak-to-peak) kΩ 0.1% DIGITAL FILTER PERFORMANCE Pass band 0.454 fS Stop band 0.546 fS ±0.04 Pass-band ripple Stop-band attenuation –50 Group delay 44.1-kHz de-emphasis error dB dB 20/fS ±0.1 dB ±0.2 dB ANALOG FILTER PERFORMANCE Frequency response at 20 kHz (1) Digital inputs and outputs are CMOS compatible. (2) All logic inputs are 3.3-V tolerant and not terminated internally. (3) LRCK and BCK terminals 3 www.ti.com SLES010D – SEPTEMBER 2001 – REVISED MAY 2004 ELECTRICAL CHARACTERISTICS (continued) all specifications at TA = 25°C, VCC1 = VCC2 = 2.4 V, fS = 44.1 kHz, system clock = 256 fS and 24-bit data, RL = 10 kΩ, unless otherwise noted PARAMETER PCM1772PW, PCM1773PW, PCM1772RGA, PCM1773RGA TEST CONDITIONS UNIT MIN TYP MAX 1.6 POWER SUPPLY REQUIREMENTS Voltage range, VCC1, VCC2 ICC1 ICC2 ICC1 + ICC2 Supply current 2.4 3.6 BPZ input 1.5 2.5 BPZ input 1 2.5 Power down(4) 5 15 µA 6 12 mW 12 36 µW 85 °C BPZ input Power dissipation Power down(4) Vdc mA TEMPERATURE RANGE Operation temperature θJA –25 Thermal resistance PCM1772PW, −73PW: 16-terminal TSSOP 150 PCM1772RGA, −73RGA: 20-terminal VQFN 130 °C/W (4) All input signals are held static. PIN ASSIGNMENTS PCM1772 PW PACKAGE (TOP VIEW) 16 15 14 13 12 11 10 9 SCKI MS MC MD VCC1 VCC2 AIN VOUTL LRCK DATA BCK PD AGND1 AGND2 VCOM VOUTR 1 2 3 4 5 6 7 8 1 20 19 18 17 16 15 2 14 3 13 4 12 5 7 8 11 9 10 VCOM VOUTR NC VOUTL 6 NC – No internal connection 4 AIN DATA BCK PD AGND1 AGND2 SCKI FMT AMIX DEMP VCC1 VCC2 AIN VOUTL LRCK NC NC NC SCKI PCM1773 RGA PACKAGE (TOP VIEW) LRCK NC NC NC SCKI PCM1772 RGA PACKAGE (TOP VIEW) 16 15 14 13 12 11 10 9 MS MC MD VCC1 VCC2 DATA BCK PD AGND1 AGND2 1 20 19 18 17 16 15 2 14 AMIX 3 13 DEMP 4 12 VCC1 VCC2 5 6 7 8 11 9 10 AIN 1 2 3 4 5 6 7 8 VCOM VOUTR NC VOUTL LRCK DATA BCK PD AGND1 AGND2 VCOM VOUTR PCM1773 PW PACKAGE (TOP VIEW) FMT www.ti.com SLES010D – SEPTEMBER 2001 – REVISED MAY 2004 Terminal Functions PCM1772PW TERMINAL NAME AGND1 NO. I/O DESCRIPTIONS 5 — Analog ground. This is a return for VCC1. AGND2 6 — Analog ground. This is a return for VCC2. AIN 10 I BCK 3 I/O DATA 2 I LRCK 1 I/O MC 14 I Mode control port serial bit clock input. Clocks the individual bits of the control data input, MD. MD 13 I Mode control port serial data input. Controls the operation mode on the PCM1772 device. MS 15 I Mode control port select. The control port is active when this terminal is low. PD 4 I Reset input. When low, the PCM1772 device is powered down, and all mode control registers are reset to default settings. SCKI 16 I System clock input VCC1 VCC2 12 — Power supply for all analog circuits except the lineout amplifier. 11 — Analog power supply for the lineout amplifier circuits. The voltage level must be the same as VCC1. VCOM 7 — Decoupling capacitor connection. An external 10-µF capacitor connected from this terminal to analog ground is required for noise filtering. Voltage level of this terminal is 0.5 VCC2 nominal. VOUTL VOUTR 9 O L-channel analog signal output of the lineout amplifiers 8 O R-channel analog signal output of the lineout amplifiers Monaural analog signal mixer input. The signal can be mixed with the output of L- and R-channel DACs. Serial bit clock. Clocks the individual bits of the audio data input, DATA. In the slave interface mode, this clock is input from external device. In master interface mode, the PCM1772 device generates the BCK output to an external device. Serial audio data input Left and right clock. Determines which channel is being input on the audio data input, DATA. The frequency of LRCK must be the same as the audio sampling rate. In the slave interface mode, this clock is input from an external device. In the master interface mode, the PCM1772 device generates the LRCK output to an external device. PCM1772RGA TERMINAL NAME NO. I/O DESCRIPTIONS AGND1 4 — Analog ground. This is a return for VCC1. AGND2 5 — Analog ground. This is a return for VCC2. AIN 10 I BCK 2 I/O Monaural analog signal mixer input. The signal can be mixed with output of L- and R-channel DACs. Serial bit clock. Clocks the individual bits of the audio data input, DATA. In the slave interface mode, this clock is input from an external device. In the master interface mode, the PCM1772 device generates the BCK output to an external device. DATA 1 I LRCK 20 I/O Serial audio data input MC 14 I Mode control port serial bit clock input. Clocks the individual bits of the control data input, MD. MD 13 I Mode control port serial data input. Controls the operation mode on the PCM1772 device. MS 15 I Mode control port select. The control port is active when this terminal is low. NC 8, 17, 18, 19 — PD 3 I Reset input. When low, the PCM1772 device is powered down, and all mode control registers are reset to default settings. SCKI 16 I System clock input VCC1 VCC2 12 — Power supply for all analog circuits except lineout amplifier. 11 — Analog power supply for lineout amplifier circuits. The voltage level must be the same as VCC1. VCOM 6 — Decoupling capacitor connection. An external 10-µF capacitor connected from this terminal to analog ground is required for noise filtering. Voltage level of this terminal is 0.5 VCC2 nominal. VOUTR VOUTL 7 O R-channel analog signal output of lineout amplifiers. 9 O L-channel analog signal output of lineout amplifiers. Left and right clock. Determines which channel is being input on the audio data input, DATA. The frequency of LRCK must be the same as the audio sampling rate. In the slave interface mode, this clock is input from an external device. In the master interface mode, the PCM1772 device generates the LRCK output to an external device. No connect 5 www.ti.com SLES010D – SEPTEMBER 2001 – REVISED MAY 2004 Terminal Functions PCM1773PW TERMINAL NAME NO. I/O DESCRIPTIONS AGND1 5 — Analog ground. This is a return for VCC1. AGND2 6 — Analog ground. This is a return for VCC2. AIN 10 — Monaural analog signal mixer input. The signal can be mixed with the output of L- and R-channel DACs. AMIX 14 I Analog mixing control BCK 3 I Serial bit clock. Clocks the individual bits of the audio data input, DATA. DATA 2 I Serial audio data input DEMP 13 I De-emphasis control FMT 15 I Data format select LRCK 1 I Left and right clock. Determines which channel is being input on the audio data input, DATA. The frequency of LRCK must be the same as the audio sampling rate. PD 4 I Reset input. When low, the PCM1773 device is powered down, and all mode control registers are reset to default settings. SCKI 16 I System clock input VCC1 VCC2 12 — Power supply for all analog circuits except the lineout amplifier 11 — Analog power supply for the lineout amplifier circuits. The voltage level must be the same as VCC1. VCOM 7 — Decoupling capacitor connection. An external 10-µF capacitor connected from this terminal to analog ground is required for noise filtering. Voltage level of this terminal is 0.5 VCC2 nominal. VOUTL VOUTR 9 O L-channel analog signal output of the lineout amplifiers 8 O R-channel analog signal output of the lineout amplifiers PCM1773RGA TERMINAL NAME AGND1 NO. I/O DESCRIPTIONS 4 — Analog ground. This is a return for VCC1. AGND2 5 — Analog ground. This is a return for VCC2. AIN 10 — Monaural analog signal mixer input. The signal can be mixed with output of L- and R-channel DACs. AMIX 14 I Analog mixing control BCK 2 I Serial bit clock. Clocks the individual bits of the audio data input, DATA. DATA 1 I Serial audio data input DEMP 13 I De-emphasis control FMT 15 I Data format select LRCK 20 I Left and right clock. Determines which channel is being input on the audio data input, DATA. The frequency of LRCK must be the same as the audio sampling rate. NC 8, 17, 18, 19 — PD 3 I Reset input. When low, the PCM1773 device is powered down, and all mode control registers are reset to default settings. SCKI 16 I System clock input VCC1 VCC2 12 — Power supply for all analog circuits except the lineout amplifier 11 — Analog power supply for the lineout amplifier circuits. The voltage level must be the same as VCC1. VCOM 6 — Decoupling capacitor connection. An external 10-µF capacitor connected from this terminal to analog ground is required for noise filtering. Voltage level of this terminal is 0.5 VCC2 nominal. VOUTL VOUTR 9 O L-channel analog signal output of the lineout amplifiers 7 O R-channel analog signal output of the lineout amplifiers 6 No connect www.ti.com SLES010D – SEPTEMBER 2001 – REVISED MAY 2004 FUNCTIONAL BLOCK DIAGRAM AIN Digital Attenuator LRCK ×8 Digital Filter Audio Interface DATA Lineout Amplifier ∆Σ DAC VOUTR + BCK VCOM VCOM (FMT) MS ×8 Digital Filter SPI Port (AMIX) MC ∆Σ DAC + VOUTL (DEMP) MD Clock Manager Power Supply SCKI PD ( ) : PCM1773 AGND1 AGND2 VCC1 VCC2 TYPICAL PERFORMANCE CURVES DIGITAL FILTER Digital Filter (De-Emphasis Off) AMPLITUDE vs FREQUENCY AMPLITUDE vs FREQUENCY 0 0.05 0.04 −20 0.03 0.02 Amplitude – dB Amplitude – dB −40 −60 −80 0.01 0.00 −0.01 −0.02 −100 −0.03 −120 −0.04 −140 0 1 2 f – Frequency [ fS] Figure 1 3 4 −0.05 0.0 0.1 0.2 0.3 0.4 0.5 f – Frequency [ fS] Figure 2 All specifications at TA = 25°C, VCC1 = VCC2 = 2.4 V, fS = 44.1 kHz, system clock = 256 fS and 24-bit data, RL = 10 kΩ, unless otherwise noted. 7 www.ti.com SLES010D – SEPTEMBER 2001 – REVISED MAY 2004 De-Emphasis Curves DE-EMPHASIS ERROR vs FREQUENCY 0 0.5 −1 0.4 −2 0.3 De-Emphasis Error – dB De-Emphasis Level – dB DE-EMPHASIS LEVEL vs FREQUENCY −3 −4 −5 −6 −7 0.2 0.1 0.0 −0.0 −0.1 −0.2 −8 −0.3 −9 −0.4 −10 0.0 −0.5 0.1 0.2 0.3 0.4 0.5 0 0.6 2 4 6 f – Frequency – kHz 10 12 14 16 18 20 Figure 4 Figure 3 TOTAL HARMONIC DISTORTION + NOISE vs SUPPLY VOLTAGE DYNAMIC RANGE vs SUPPLY VOLTAGE 1.00 0.1 104 102 Dynamic Range – dB THD+N – Total Harmonic Distortion + Noise – % 8 f – Frequency – kHz 0.10 0.01 100 98 96 94 0.01 0.001 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 92 1.2 1.6 2.0 2.4 2.8 3.2 VCC – Supply Voltage – V VCC – Supply Voltage – V Figure 5 Figure 6 3.6 4.0 All specifications at TA = 25°C, VCC1 = VCC2 = 2.4 V, fS = 44.1 kHz, system clock = 256 fS and 24-bit data, RL = 10 kΩ, unless otherwise noted. 8 www.ti.com SLES010D – SEPTEMBER 2001 – REVISED MAY 2004 CHANNEL SEPARATION vs SUPPLY VOLTAGE SNR vs SUPPLY VOLTAGE 86 102 84 Channel Separation – dB 104 SNR – dB 100 98 96 1.6 2.0 2.4 2.8 3.2 3.6 78 74 1.2 4.0 1.6 2.0 2.4 2.8 3.2 VCC – Supply Voltage – V VCC – Supply Voltage – V Figure 7 Figure 8 TOTAL HARMONIC DISTORTION + NOISE vs FREE-AIR TEMPERATURE DYNAMIC RANGE vs FREE-AIR TEMPERATURE 1.00 0.1 3.6 4.0 80 100 102 101 100 Dynamic Range – dB THD+N – Total Harmonic Distortion + Noise – % 80 76 94 92 1.2 82 0.10 0.01 99 98 97 96 95 0.01 0.001 −40 −20 0 20 40 60 80 100 94 −40 −20 0 20 40 60 TA – Free-Air Temperature – °C TA – Free-Air Temperature – °C Figure 9 Figure 10 All specifications at TA = 25°C, VCC1 = VCC2 = 2.4 V, fS = 44.1 kHz, system clock = 256 fS and 24-bit data, RL = 10 kΩ, unless otherwise noted. 9 www.ti.com SLES010D – SEPTEMBER 2001 – REVISED MAY 2004 SNR vs FREE-AIR TEMPERATURE CHANNEL SEPARATION vs FREE-AIR TEMPERATURE 84 101 83 100 82 Channel Separation – dB 102 SNR – dB 99 98 97 96 95 94 −40 81 80 79 78 77 −20 0 20 40 60 80 76 −40 100 −20 0 20 40 60 TA – Free-Air Temperature – °C TA – Free-Air Temperature – °C Figure 11 Figure 12 80 100 5.0 20 4.5 18 4.0 16 3.5 14 Operational 3.0 12 2.5 10 2.0 8 1.5 6 Power Down 1.0 4 0.5 2 0.0 1.2 ICC – Supply Current, Power Down – µA ICC – Supply Current, Operational – mA SUPPLY CURRENT vs SUPPLY VOLTAGE 0 1.6 2.0 2.4 2.8 3.2 3.6 4.0 VCC – Supply Current – V Figure 13 All specifications at TA = 25°C, VCC1 = VCC2 = 2.4 V, fS = 44.1 kHz, system clock = 256 fS and 24-bit data, RL = 10 kΩ, unless otherwise noted. 10 www.ti.com SLES010D – SEPTEMBER 2001 – REVISED MAY 2004 5.0 20 4.5 18 4.0 16 3.5 14 3.0 12 Operational 2.5 10 2.0 8 Power Down 1.5 6 1.0 4 0.5 2 0.0 ICC – Supply Current, Power Down – µA ICC – Supply Current, Operational – mA SUPPLY CURRENT vs SAMPLING FREQUENCY 0 0 10 20 30 40 50 fS – Sampling Frequency – kHz Figure 14 DYNAMIC RANGE vs JITTER 100 Dynamic Range – dB 99 98 97 96 95 94 0 100 200 300 400 500 600 700 Jitter – ps Figure 15 All specifications at TA = 25°C, VCC1 = VCC2 = 2.4 V, fS = 44.1 kHz, system clock = 256 fS and 24-bit data, RL = 10 kΩ, unless otherwise noted. 11 www.ti.com SLES010D – SEPTEMBER 2001 – REVISED MAY 2004 OUTPUT SPECTRUM (–60 dB, N = 8192) 0 −20 −20 −40 −40 Amplitude – dB Amplitude – dB OUTPUT SPECTRUM (–60 dB, N = 8192) 0 −60 −80 −60 −80 −100 −100 −120 −120 −140 −140 0 5 10 15 20 0 20 40 60 80 f – Frequency – kHz f – Frequency – kHz Figure 16 Figure 17 100 120 All specifications at TA = 25°C, VCC1 = VCC2 = 2.4 V, fS = 44.1 kHz, system clock = 256 fS and 24-bit data, RL = 10 kΩ, unless otherwise noted. 12 www.ti.com SLES010D – SEPTEMBER 2001 – REVISED MAY 2004 DETAILED DESCRIPTION SYSTEM CLOCK, RESET, AND FUNCTIONS System Clock Input The PCM1772 and PCM1773 devices require a system clock for operating the digital interpolation filters and multilevel ∆-Σ modulators. The system clock is applied at terminal 16 (SCKI). Table 1 shows examples of system clock frequencies for common audio sampling rates. Figure 18 shows the timing requirements for the system clock input. For optimal performance, it is important to use a clock source with low-phase jitter and noise. Table 1. System Clock Frequency for Common Audio Sampling Frequencies SAMPLING FREQUENCY, LRCK SYSTEM CLOCK FREQUENCY, SCKI (MHz) 128 fS 192 fS 256 fS 384 fS 48 kHz 6.144 9.216 12.288 18.432 44.1 kHz 5.6448 8.4672 11.2896 16.9344 32 kHz 4.096 6.144 8.192 12.288 24 kHz 3.072 4.608 6.144 9.216 22.05 kHz 2.8224 4.2336 5.6448 8.4672 16 kHz 2.048 3.072 4.096 6.144 12 kHz 1.536 2.304 3.072 4.608 11.025 kHz 1.4112 2.1168 2.8224 4.2336 8 kHz 1.024 1.536 2.048 3.072 t(SCKH) 0.7 VCC1 SCKI 0.3 VCC1 t(SCKL) System Clock Pulse Cycle Time† † 1/(128 fS), 1/(192 fS), 1/(256 fS), and 1/(384 fS). PARAMETERS System clock pulse width high System clock pulse width low SYMBOL MIN UNIT t(SCKH) t(SCKL) 7 ns 7 ns Figure 18. System Clock Timing 13 www.ti.com SLES010D – SEPTEMBER 2001 – REVISED MAY 2004 POWER ON/OFF AND RESET The PCM1772/73 always must have the PD pin set from LOW to HIGH once after power-supply voltages VCC1 and VCC2 have reached the specified voltage range and stable clocks SCKI, BCK, and LRCK are being supplied for the power-on sequence. A minimum time of 1 ms after both the clock and power-supply requirements are met is required before the PD pin changes from LOW to HIGH, as shown in Figure 19. Subsequent to the PD LOW-to-HIGH transition, the internal logic state is held in reset for 1024 system clock cycles prior to the start of the power-on sequence. During the power-on sequence, VOUTL and VOUTR increase gradually from ground level, reaching an output level that corresponds to the input data after a period of 9334/fS. When powering off, the PD pin is set from HIGH to LOW first. Then VOUTL and VOUTR decrease gradually to ground level over a period of 9334/fS, as shown in Figure 20, after which power can be removed without creating pop noise. When powering on or off, adhering to the timing requirements of Figure 19 and Figure 20 ensures that pop noise does not occur. If the timing requirements are not met, pop noise might occur. VCC1, VCC2 0V 1 ms (Min) 1024 Internal System Clocks LRCK, BCK, SCKI 1 ms (Min) PD Internal Reset 9334/fS VOUTL, VOUTR 0V Figure 19. Power-On Sequence VCC1, VCC2 0V LRCK, BCK, SCKI 9334/fS PD VOUTL, VOUTR 0V Figure 20. Power-Off Sequence 14 www.ti.com SLES010D – SEPTEMBER 2001 – REVISED MAY 2004 POWER-UP/-DOWN SEQUENCE AND RESET The PCM1772 device has two kinds of power-up/-down methods: the PD terminal through hardware control and PWRD (register 4, B0) through software control. The PCM1773 device has only the PD terminal through hardware control for the power-up/-down sequence. The power-up or power-down sequence operates the same as the power-on or power-off sequence. When powering up or down using the PD terminal, all digital circuits are reset. When powering up or down using PWRD, all digital circuits are reset except for maintaining the logic states of the registers. Figure 21 shows the power-up/power-down sequence. 2.4 V VCC1, VCC2 9334/fS 9334/fS LRCK, BCK, SCKI PD VOUTL, VOUTR 0V Figure 21. Power-Down and Power-Up Sequences 15 www.ti.com SLES010D – SEPTEMBER 2001 – REVISED MAY 2004 AUDIO SERIAL INTERFACE The audio serial interface for the PCM1772 and PCM1773 devices is comprised of a 3-wire synchronous serial port. It includes terminals 1 (LRCK), 2 (DATA), and 3 (BCK). BCK is the serial audio bit clock, and it clocks the serial data present on DATA into the audio interface serial shift register. Serial data is clocked into the PCM1772 and PCM1773 devices on the rising edge of BCK. LRCK is the serial audio left/right word clock. It latches serial data into the serial audio interface internal registers. Both LRCK and BCK of the PCM1772 device support the slave and master modes which are set by FMT (register 3). LRCK and BCK are outputs during the master mode and inputs during the slave mode. In slave mode, BCK and LRCK are synchronous to the audio system clock, SCKI. Ideally, it is recommended that LRCK and BCK be derived from SCKI. LRCK is operated at the sampling frequency, fS. BCK can be operated at 32, 48, and 64 times the sampling frequency. In master mode, BCK and LRCK are derived from the system clock, and these terminals are outputs. The BCK and LRCK are synchronous to SCKI. LRCK is operated at the sampling frequency, fS. BCK can be operated at 64 times the sampling frequency. The PCM1772 and PCM1773 devices operate under LRCK synchronized with the system clock. The PCM1772 and PCM1773 devices do not need a specific phase relationship between LRCK and the system clock, but do require the synchronization of LRCK and the system clock. If the relationship between the system clock and LRCK changes more than ±3BCK during one sample period, internal operation of the PCM1772 and PCM1773 devices halt within 1/fS, and the analog output is kept in last data until resynchronization between system clock and LRCK is completed. AUDIO DATA FORMATS AND TIMING The PCM1772 device supports industry-standard audio data formats, including standard, I2S, and left justified. The PCM1773 device supports the I2S and left-justified data formats. Table 2 lists the main features of the audio data interface. Figure 22 shows the data formats. Data formats are selected using the format bits, FMT[2:0] of control register 3 in case of the PCM1772 device, and are selected using the FMT terminal in case of the PCM1773 device. The default data format is 24-bit, left-justified, slave mode. All formats require binary 2s complement, MSB-first audio data. Figure 23 shows a detailed timing diagram for the serial audio interface in slave mode. Figure 24 shows a detailed timing diagram for the serial audio interface in master mode. Table 2. Audio Data Interface AUDIO-DATA INTERFACE FEATURE Audio data interface format 16 (PCM1772) (PCM1773) CHARACTERISTIC Standard, I2S, left justified I2S, left justified Audio data bit length 16-, 20-, 24-bits selectable Audio data format MSB first, 2s complement www.ti.com SLES010D – SEPTEMBER 2001 – REVISED MAY 2004 (1) Standard Data Format; L-Channel = HIGH, R-Channel = LOW (Slave Mode) 1/fS LRCK R-Channel L-Channel BCK (= 32 fS, 48 fS or 64 fS) 16-Bit Right-Justified, BCK = 32 fS DATA 14 15 16 1 2 3 14 15 16 1 3 14 15 16 MSB LSB MSB 2 LSB 16-Bit Right-Justified, BCK = 48 fS or 64 fS DATA 14 15 16 1 2 3 1 14 15 16 MSB LSB 2 3 14 15 16 MSB LSB 20-Bit Right-Justified DATA 18 19 20 1 2 3 18 19 20 MSB 1 LSB 2 3 18 19 20 MSB LSB 24-Bit Right-Justified DATA 22 23 24 1 2 3 22 23 24 MSB 1 LSB 2 3 22 23 24 MSB LSB (2) I2S Data Format; L-Channel = LOW, R-Channel = HIGH (Slave Mode) 1/fS LRCK L-Channel R-Channel BCK (= 32 fS, 48 fS or 64 fS) DATA 1 2 3 N−2 N−1 MSB N 1 LSB 2 3 N−2 N−1 MSB N 1 2 LSB (3) Left-Justified Data Format; L-Channel = HIGH, R-Channel = LOW (Slave Mode) 1/fS LRCK L-Channel R-Channel BCK (= 32 fS, 48 fS or 64 fS) DATA 1 2 3 MSB N−2 N−1 N 1 LSB 2 3 N−2 N−1 MSB N 1 2 N 1 2 LSB (4) Left-Justified Data Format; L-Channel = HIGH, R-Channel = LOW (Master Mode) (The frequency of BCK is 64 fS and SCKI is 256 fS only) 1/fS LRCK L-Channel R-Channel BCK (= 64 fS) DATA 1 2 3 MSB N−2 N−1 LSB N 1 2 3 MSB N−2 N−1 LSB Figure 22. Audio Data Input Formats 17 www.ti.com SLES010D – SEPTEMBER 2001 – REVISED MAY 2004 50% of VCC1 LRCK (Input) t(BCL) t(BCH) t(LB) 50% of VCC1 BCK (Input) t(BCY) t(BL) 50% of VCC1 DATA t(DS) t(DH) PARAMETERS BCK pulse cycle time BCK high-level time BCK low-level time BCK rising edge to LRCK edge LRCK edge to BCK rising edge DATA setup time DATA hold time (1) fS is the sampling frequency. SYMBOL MIN t(BCY) t(BCH) 1/(64 fS)(1) 35 ns t(BCL) t(BL) 35 ns 10 ns t(LB) t(DS) t(DH) 10 ns 10 ns 10 ns Figure 23. Audio Interface Timing (Slave Mode) 18 MAX UNIT www.ti.com SLES010D – SEPTEMBER 2001 – REVISED MAY 2004 t(SCY) 50% of VCC1 SCKI t(DL) 50% of VCC1 LRCK (Output) t(BCL) t(BCH) t(DB) t(DB) 50% of VCC1 BCK (Output) t(BCY) 50% of VCC1 DATA t(DS) t(DH) PARAMETERS MAX UNIT 0 40 ns t(DB) t(BCY) t(BCH) 0 1/(64 fS)(1) 40 ns 146 ns t(BCL) t(DS) 146 ns DATA setup time 10 ns DATA hold time t(DH) 10 ns SCKI pulse cycle time LRCK edge from SCKI rising edge BCK edge from SCKI rising edge BCK pulse cycle time BCK high-level time BCK low-level time SYMBOL MIN t(SCY) t(DL) 1/(256 fS)(1) (1) fS is up to 48 kHz. fS is the sampling frequency. Figure 24. Audio Interface Timing (Master Mode) 19 www.ti.com SLES010D – SEPTEMBER 2001 – REVISED MAY 2004 HARDWARE CONTROL (PCM1773) The digital functions of the PCM1773 device are capable of hardware control. Table 3 shows selectable formats, Table 4 shows de-emphasis control, and Table 5 shows analog mixing control. Table 3. Data Format Select FMT DATA FORMAT Low 16- to 24-bit, left-justified format 16- to 24-bit, I2S format High Table 4. De-Emphasis Control DEMP DE-EMPHASIS FUNCTION Low 44.1-kHz de-emphasis OFF High 44.1-kHz de-emphasis ON Table 5. Analog Mixing Control AMIX ANALOG MIXING Low Analog mixing OFF High Analog mixing ON SOFTWARE CONTROL (PCM1772) The PCM1772 device has many programmable functions that can be controlled in the software control mode. The functions are controlled by programming the internal registers using MS, MC, and MD. The software control interface is a 3-wire serial port that operates asynchronously to the serial audio interface. The serial control interface is used to program the on-chip mode registers. MD is the serial data input, used to program the mode registers. MC is the serial bit clock, used to shift data into the control port. MS is the mode control port select signal. REGISTER WRITE OPERATION (PCM1772) All write operations for the serial control port use 16-bit data words. Figure 25 shows the control data word format. The most significant bit must be 0. Seven bits, labeled IDX[6:0], set the register index (or address) for the write operation. The eight least significant bits, D[7:0], contain the data to be written to the register specified by IDX[6:0]. Figure 26 shows the functional timing diagram for writing to the serial control port. To write data into the mode register, data is clocked into an internal shift register on the rising edge of the MC clock. Serial data can change on the falling edge of the MC clock and must be stable on the rising edge of the MC clock. The MS signal must be low during the write mode, and the rising edge of the MS signal must be aligned with the falling edge of the last MC clock pulse in the 16-bit frame. The MC clock can run continuously between transactions while the MS signal is low. LSB MSB 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 Register Index (or Address) IDX0 D7 D6 D5 D4 Register Data Figure 25. Control Data Word Format for MD 20 D3 D2 D1 D0 www.ti.com SLES010D – SEPTEMBER 2001 – REVISED MAY 2004 (1) Single Write Operation 16-Bits MS MC MD MSB LSB MSB (2) Continuous Write Operation 16-Bits x N Frames MS MC MD MSB LSB MSB LSB MSB LSB N Frames Figure 26. Register Write Operation CONTROL INTERFACE TIMING REQUIREMENTS (PCM1772) Figure 27 shows a detailed timing diagram for the serial control interface. These timing parameters are critical for proper control port operation. t(MHH) MS 50% of VCC1 t(MLS) t(MCL) t(MCH) t(MLH) MC 50% of VCC1 t(MCY) LSB MD 50% of VCC1 t(MDS) t(MDH) PARAMETERS MC pulse cycle time MC low-level time MC high-level time MS high-level time MS falling edge to MC rising edge MS hold time MD hold time SYMBOL t(MCY) t(MCL) t(MCH) t(MHH) t(MLS) t(MLH) t(MDH) MIN 100(1) TYP MAX UNITS ns 50 ns 50 ns (2) ns 20 ns 20 ns 15 ns MD setup time t(MDS) 20 (1) When MC runs continuously between transactions, MC pulse cycle time is specified as 3/(128 fS), where fS is sampling rate. (2) 3/(128fS) s (min), where fS is sampling rate ns Figure 27. Control Interface Timing 21 www.ti.com SLES010D – SEPTEMBER 2001 – REVISED MAY 2004 MODE CONTROL REGISTERS (PCM1772) User-Programmable Mode Controls The PCM1772 device has a number of user-programmable functions that can be accessed via mode control registers. The registers are programmed using the serial control interface, as discussed in the SOFTWARE CONTROL (PCM1772) section. Table 6 lists the available mode control functions, along with their reset default conditions and associated register index. Register Map Table 7 shows the mode control register map. Each register includes an index (or address) indicated by the IDX[6:0] bits. Table 6. User-Programmable Mode Controls FUNCTION RESET DEFAULT REGISTER NO. BIT(S) Disabled 01 MUTL, MUTR 0 dB 01, 02 ATL[5:0], ATR[5:0] OVER Soft mute control, L/R independently Digital attenuation level setting, 0 dB to –62 dB in 1-dB steps, L/R independently Oversampling rate control (128 fS, 192 fS, 256 fS, 384 fS) 128 fS oversampling 03 Polarity control for analog output for R-channel DAC Not inverted 03 RINV Analog mixing control for analog in, AIN (terminal 14) Disabled 03 AMIX 44.1-kHz de-emphasis control Disabled 03 DEM 24-bit, left-justified format 03 FMT[2:0] Zero cross attenuation Disabled 04 ZCAT Power down control Disabled 04 PWRD Audio data format select Table 7. Mode Control Register Map REGISTER IDX [6:0] (B14–B8) B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 Register 01 01h 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 MUTR MUTL ATL5 ATL4 ATL3 ATL2 ATL1 ATL0 Register 02 02h 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV RSV ATR5 ATR4 ATR3 ATR2 ATR1 ATR0 Register 03 03h 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 OVER RSV RINV AMIX DEM FMT2 FMT1 FMT0 Register 04 04h 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV RSV RSV ZCAT RSV RSV RSV PWRD NOTE: RSV: Reserved for test operation. It must be set to 0 during regular operation. Register Definitions Register 01 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 MUTR MUTL ATL5 ATL4 ATL3 ATL2 ATL1 ATL0 IDX[6:0]: 000 0001b MUTx: Soft Mute Control Where, x = L or R, corresponding to the line output VOUTL and VOUTR. Default Value: 0 MUTL, MUTR = 0 MUTL, MUTR = 1 Mute disabled (default) Mute enabled The mute bits, MUTL and MUTR, enable or disable the soft mute function for the corresponding line outputs, VOUTL and VOUTR. The soft mute function is incorporated into the digital attenuators. When mute is disabled (MUTx = 0), the attenuator and DAC operate normally. When mute is enabled by setting MUTx = 1, the digital attenuator for the corresponding output is decreased from the current setting to the infinite attenuation, one attenuator step (1 dB) at a time. This provides pop-free muting of the line output. By setting MUTx = 0, the attenuator is increased one step at a time to the previously programmed attenuation level. 22 www.ti.com SLES010D – SEPTEMBER 2001 – REVISED MAY 2004 ATL[5:0]: Digital Attenuation Level Setting for Line Output, VOUTL Default value: 11 1111b Line output, VOUTL includes a digital attenuation function. The attenuation level can be set from 0 dB to –62 dB, in 1-dB steps. Changes in attenuator levels are made by incrementing or decrementing by one step (1 dB) for every 8/fS time internal until the programmed attenuator setting is reached. Alternatively, the attenuation level may be set to infinite attenuation (or mute). The following table shows attenuation levels for various settings: ATL[5:0] ATTENUATION LEVEL SETTING 11 1111b 11 1110b 0 dB, no attenuation (default) –1 dB 11 1101b 00 0010b –2 dB –61 dB 00 0001b 00 0000b –62 dB Mute B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV RSV Register 02 B5 B4 B3 ATR5 ATR4 ATR3 B2 B1 ATR2 ATR1 B0 ATR0 IDX[6:0]: 000 0010b ATR[5:0]: Digital Attenuation Level Setting for Line Output, VOUTR Default Value: 11 1111b Line output, VOUTR includes a digital attenuation function. The attenuation level can be set from 0 dB to –62 dB, in 1-dB steps. Changes in attenuator levels are made by incrementing or decrementing by one step (1 dB) for every 8/fS time internal until the programmed attenuator setting in reached. Alternatively, the attenuation level can be set to infinite attenuation (or mute). To set the attenuation levels for ATR[5:0], see the table for ATL[5:0], register 01. Register 03 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 OVER RSV RINV AMIX DEM FMT2 FMT1 FMT0 IDX[6:0]: 000 0011b OVER: Oversampling Control Default Value: 0 OVER = 0 OVER = 1 128fS oversampling 192fS, 256fS, 384fS oversampling The OVER bit controls the oversampling rate of the ∆-Σ D/A converters. When it operates at a low sampling rate, less than 24 kHz, this function is recommended. RINV: Polarity Control for Line Output, VOUTR Default Value: 0 RINV = 0 RINV = 1 Not inverted Inverted output The RINV bits allow the user to control the polarity of the line output, VOUTR. This function can be used to connect the monaural speaker with BTL connection method. This bit is recommended to be 0 during the power-up/-down sequence for minimizing audible pop noise. 23 www.ti.com SLES010D – SEPTEMBER 2001 – REVISED MAY 2004 AMIX: Analog Mixing Control for External Analog Signal, AIN Default Value: 0 Disabled (not mixed) Enabled (mixing to the DAC output) AMIX = 0 AMIX = 1 AMIX bit allows the user to mix analog input (AIN) with line outputs (VOUTL/VOUTR) internally. DEM: 44.1-kHz De-Emphasis Control Default Value: 0 DEM = 0 DEM = 1 Disabled Enabled The DEM bit enables or disables the digital de-emphasis filter for 44.1-kHz sampling rate. FMT[2:0]: Audio Interface Data Format Default Value: 000 The FMT[2:0] bits select the data format for the serial audio interface. The following table shows the available format options. FMT[2:0] Audio Data Format Selection 000 001 010 011 100 101 110 111 16- to 24-bit, left-justified format (default) 16- to 24-bit, I2S format 24-bit right-justified data 20-bit right-justified data 16-bit right-justified data 16- to 24-bit, left-justified format, master mode Reserved Reserved Register 04 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV RSV RSV ZCAT RSV RSV RSV PWRD IDX[6:0]: 000 0100b ZCAT: Zero Cross Attenuation Default Value: 0 ZCAT = 0 ZCAT = 1 Normal attenuation (default) Zero cross attenuation This bit enables to change signal level on zero crossing during attenuation control or muting. If the signal does not cross BPZ beyond 512/fS (11.6 ms at 44.1-kHz sampling rate), the signal level is changed similar to normal attenuation control. This function is independently monitored for each channel; moreover, change of signal level is alternated between both channels. Figure 28 shows an example of zero cross attenuation. 24 www.ti.com SLES010D – SEPTEMBER 2001 – REVISED MAY 2004 ATT CTRL START L-Channel (1.5 kHz) R-Channel (1 kHz) Level Change Point Figure 28. Example of Zero Cross Attenuation PWRD: Power Down Control Default Value: 0 PWRD = 0 PWRD = 1 Normal operation (default) Power-down state This bit is used to enter into low-power mode. Note that PWRD has no reset function. When this bit is set to 1, the PCM1772 device enters low-power mode, and all digital circuits are reset except the register states which remain unchanged. ANALOG IN/OUT LINE OUTPUT (STEREO) The PCM1772 and PCM1773 devices have two independent lineout amplifiers, and each amplifier output is provided at the VOUTL and VOUTR terminals. The capability of line output is designed for driving a 10-kΩ minimum load. Monaural Output (BTL Mode/Monaural Speaker) When the user needs monaural output, the PCM1772 device can provide it. The PCM1772 device has RINV bit on control register 03. Because this bit allows the user to invert the polarity of the line output for the right channel, the user can create a monaural output by summing the line output for left and right channels through the external power amplifier or headphone amplifier. The RINV bit is recommended to be 0 during power-up/-down sequence for minimizing audible pop noise. Analog Input The PCM1772 and PCM1773 devices have an analog input, AIN (terminal 10). The AMIX bit (PCM1772) or the AMIX terminal (PCM1773) allows the user to mix AIN with the line outputs (VOUTL and VOUTR) internally. When in MIXING mode, an ac-coupling capacitor is needed for AIN. But if AIN is not used, AIN must be open and the AMIX bit (PCM1772) must be disabled or the AMIX terminal (PCM1773) must be low. Because AIN does not have an internal low-pass filter, it is recommended that the bandwidth of input signal into AIN is limited to less than 100 kHz. The source of signals connected to AIN must be connected by low impedance. Although the maximum input voltage on AIN is designed to be as large as 0.584VCC2 [peak-to-peak], the user must attenuate the input voltage on AIN and control digital input data so that each line output (VOUTL and VOUTR) does not exceed 0.75 VCC2 [peak-to-peak] during mixing mode. VCOM Output One unbuffered common-mode voltage output terminal, VCOM, is brought out for decoupling purposes. This terminal is nominally biased to a dc voltage level equal to 0.5 VCC2 and connected to a 10-µF capacitor. In the case of a capacitor smaller than 10 µF, pop noise can be generated during the power-on/-off or power-up/-down sequences. 25 www.ti.com SLES010D – SEPTEMBER 2001 – REVISED MAY 2004 APPLICATION INFORMATION CONNECTION DIAGRAMS Figure 29 shows the basic connection diagram with the necessary power supply bypassing and decoupling components. It is recommended that the component values shown in Figure 29 be used for all designs. The use of series resistors (22 Ω to 100 Ω) is recommended for the MCKI, LRCK, BCK, and DATA inputs. The series resistor combines with the stray PCB and device input capacitance to form a low-pass filter that reduces high-frequency noise emissions and helps to dampen glitches and ringing present on the clock and data lines. POWER SUPPLIES AND GROUNDING The PCM1772 and PCM1773 devices require a 2.4-V typical analog supply for VCC1 and VCC2. These 2.4-V supplies power the DAC, analog output filter, and other circuits. For best performance, these 2.4-V supplies must be derived from the analog supply using a linear regulator, as shown in Figure 29. Figure 29 shows the proper power supply bypassing. The 10-µF capacitors must be tantalum or aluminum electrolytic, while the 0.1-µF capacitors are ceramic (X7R type is recommended for surface-mount applications). 1.6 V to 3.6 V Audio DSP Controller 10 µF 1 LRCK SCKI 16 2 DATA MS 15 3 BCK MC 14 4 PD MD 13 VCC1 12 VCC2 11 AIN 10 5 AGND1 6 AGND2 7 VCOM 8 VOUTR PCM1772 VOUTL 10 µF 10 µF Analog In 9 10 µF 10 µF 10 µF Figure 29. Basic Connection Diagram 26 Post LPF Power Amplifier or Headphone Amplifier Post LPF Power Amplifier or Headphone Amplifier MPQF110 − SEPTEMBER 2001 RGA (S-PQFP-N20) PLASTIC QUAD FLATPACK 4,05 3,95 4,30 4,10 0,50 NOM/2 A “A” 4,30 4,10 B DETAIL “A” 4,05 3,95 0,50 NOM 20 1,00 NOM C0,70 Index “C” 0,25 0,09 S 1,00 0,95 MAX 0,50 1 0,50 NOM 1,00 NOM 0,75 0,45 0,05 0,00 S 0,05 S DETAIL “B” “B” 0,05 M S AB 0,27 0,17 0,21 0,09 0,05 0,00 0,35 ± 0,11 0,23 0,17 0,69 ± 0,11 0,25 0,09 0,27 0,17 DETAIL “C” 0,22 ± 0,05 4202802/B 08/01 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. These dimensions include package bend. Falls within EIAJ: EDR-7324. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. 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