PCM3010 SLES055 – NOVEMBER 2002 24-BIT STEREO AUDIO CODEC WITH 96-kHz ADC, 192-kHz DAC, AND SINGLE-ENDED ANALOG INPUT/OUTPUT D System Clock: 128 fS, 192 fS, 256 fS, 384 fS, FEATURES D 24-Bit Delta-Sigma ADC and DAC D Stereo ADC: D D D 512 fS, 768 fS D Dual Power Supplies: 5 V for Analog and 3.3 V – Single-Ended Voltage Input: 3 Vp-p – Antialiasing Filter Included – 1/128, 1/64 Decimation Filter: – Pass-Band Ripple: ±0.05 dB – Stop-Band Attenuation: –65 dB – On-Chip High-Pass Filter: 0.84 Hz at fS = 44.1 kHz – High Performance: – THD+N: –95 dB (Typical) – SNR: 100 dB (Typical) – Dynamic Range: 102 dB (Typical) Stereo DAC: – Single-Ended Voltage Output: 3 Vp-p – Analog Low-Pass Filter Included – ×8 Oversampling Digital Filter: – Pass-Band Ripple: ±0.03 dB – Stop-Band Attenuation: –50 dB – High Performance: – THD+N: –96 dB (Typical) – SNR: 104 dB (Typical) – Dynamic Range: 104 dB (Typical) Multiple Functions: – Digital De-Emphasis: 32 kHz, 44.1 kHz, 48 kHz – Power Down: ADC/DAC Simultaneous – 16-, 24-Bit Audio Data Formats Sampling Rate: 16–96 kHz (ADC), 16–192 kHz (DAC) D for Digital Package: 24-Pin SSOP, Lead-Free Product APPLICATIONS D DVD Recorders D CD Recorders D PC Audio D Sound Control System DESCRIPTION The PCM3010 is a low-cost single-chip 24-, 16-bit stereo audio codec (ADC and DAC) with single-ended analog voltage input and output. Both the analog-to-digital converters (ADCs) and digital-toanalog converters (DACs) employ delta-sigma modulation with 64-times oversampling. The ADCs include a digital decimation filter with a high-pass filter, and the DACs include an 8-times-oversampling digital interpolation filter. The DACs also include a digital de-emphasis function. The PCM3010 accepts four different audio data formats for the ADC and DAC. The PCM3010 provides a power-down mode, which works on the ADC and DAC simultaneously. The PCM3010 is suitable for a wide variety of cost-sensitive consumer applications where good performance is required. The PCM3010 is fabricated using a highly advanced CMOS process and is available in a small 24-pin SSOP package. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2002, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. www.ti.com 1 PCM3010 SLES055 – NOVEMBER 2002 DB PACKAGE (TOP VIEW) VINL VINR VREF1 VREF2 VCC1 AGND1 FMT0 FMT1 TEST LRCK BCK DIN 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VCOM VOUTL VOUTR VCC2 AGND2 DEMP0 DEMP1 PDWN SCKI VDD DGND DOUT PACKAGE/ORDERING INFORMATION 2 PRODUCT PACKAGE PACKAGE CODE PCM3010DB 24 lead SSOP 24-lead 24DB OPERATION TEMPERATURE RANGE PACKAGE MARKING –25°C 25°C to 85°C PCM3010 www.ti.com ORDERING NUMBER TRANSPORT MEDIA PCM3010DB Tube PCM3010DBR Tape and reel PCM3010 SLES055 – NOVEMBER 2002 block diagram VINL Single-End Differential Converter Fifth-Order Delta-Sigma Modulator DOUT VREF1 VREF2 × 1/128, 1/64 Decimation Filter with HPF Reference and Buffer Audio Data Interface BCK LRCK DIN VINR Single-End Differential Converter Fifth-Order Delta-Sigma Modulator Clock and Timing Generator, Timing and Power Control VOUTL Analog LPF and Buffer Amp SCKI PDWN Multilevel Delta-Sigma Modulator TEST ×8 Oversampling Interpolation Filter VCOM VOUTR Analog LPF and Buffer Amp Mode Control Interface FMT0 FMT1 DEMP0 DEMP1 Multilevel Delta-Sigma Modulator Power Supply AGND2 VCC2 AGND1 VCC1 DGND VDD Figure 1. PCM3010 Block Diagram www.ti.com 3 PCM3010 SLES055 – NOVEMBER 2002 analog front-end (right-channel) 1 µF + VINL 1 20 kΩ – – + (+) + (–) VREF1 3 + 0.1 µF Delta-Sigma Modulator 0.5 VCC1 10 µF VREF2 4 + 0.1 µF 10 µF 4 Reference www.ti.com PCM3010 SLES055 – NOVEMBER 2002 Terminal Functions TERMINAL NAME NO. I/O DESCRIPTIONS AGND1 6 – ADC analog ground AGND2 20 – DAC analog ground BCK 11 I Audio data bit clock input‡ DEMP1 18 I DEMP0 19 I De-emphasis select input, 1† De-emphasis select input, 0† DGND 14 – Digital ground DIN 12 I Audio data digital input‡ DOUT 13 O Audio data digital output FMT0 7 I FMT1 8 I Audio data format select input, 0† Audio data format select input, 1† LRCK 10 I Audio data latch enable input‡ PDWN 17 I SCKI 16 I ADC and DAC power-down control input, active LOW† System clock input‡ TEST 9 I Test control, must be open or connected to DGND† VCC1 VCC2 5 – ADC analog power supply, 5 V 21 – DAC analog power supply, 5 V VCOM VDD 24 – DAC common voltage decoupling (= 0.5 VCC2) 15 – Digital power supply, 3.3 V VINL VINR 1 I ADC analog input, L-channel 2 I ADC analog input, R-channel VOUTL VOUTR 23 O DAC analog output, L-channel 22 O DAC analog output, R-channel VREF1 3 – ADC reference voltage decoupling, 1 (= 0.5 VCC1) VREF2 4 – ADC reference voltage decoupling, 2 † Schimtt-trigger input with 50-kΩ typical internal pulldown resistor, 5-V tolerant. ‡ Schimtt-trigger input, 5-V tolerant. www.ti.com 5 PCM3010 SLES055 – NOVEMBER 2002 absolute maximum ratings over operating free-air temperature (unless otherwise noted)† Supply voltage: VCC1, VCC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5 V VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.0 V Supply voltage differences: VCC1, VCC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.1 V Ground voltage differences: AGND1, AGND2, DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.1 V Digital input voltage: PDWN, TEST, FMT0, FMT1, DEMP0, DEMP1, LRCK, BCK, DIN, SCKI . . . . –0.3 V to +6.5 V Digital input voltage: DOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to (VDD + 0.3 V) Analog input voltage, VINL, VINR, VREF1, VREF2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to (VCC1 + 0.3 V) Analog input voltage, VCOM, VOUTL, VOUTR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to (VCC2 + 0.3 V) Input current (any pins except supplies) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±10 mA Ambient temperature under bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 125°C Storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 150°C Junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C Lead temperature (soldering) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C, 5 s Package temperature (IR reflow, peak) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. electrical characteristics, all specifications at TA = 25°C, VCC1 = VCC2 = 5 V, VDD = 3.3 V, fS = 44.1 kHz, SCKI = 384 fS, 24-bit data (unless otherwise noted) PCM3010DB PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DIGITAL INPUT/OUTPUT DATA FORMAT Left-justified, I2S, right-justified Audio data interface format Audio data bit length 16, 24 Audio data format fS Bits MSB-first, 2s complement Sampling frequency, ADC 16 44.1 96 kHz Sampling frequency, DAC 16 44.1 192 kHz 4 50 MHz 2.0 5.5 VDC System clock frequency 128 fS, 192 fS, 256 fS, 384 fS, 512 fS, 768 fS INPUT LOGIC VIH VIL Input logic level (see Notes 1 and 2) IIH IIL Input logic current (see Note 2) VIN = VDD VIN = 0 V IIH IIL Input logic current (see Note 1) VIN = VDD VIN = 0 V 65 0.8 VDC ±10 µA ±10 µA 100 µA ±10 µA OUTPUT LOGIC VOH VOL Output logic level (see Note 3) IOUT = –4 mA IOUT = 4 mA 2.4 0.4 VDC ADC CHARACTERISTICS Resolution 24 Bits NOTES: 1. Pins 7, 8, 9, 17, 18, 19: PDWN , TEST, FMT0, FMT1, DEMP0, DEMP1 (Schmitt-trigger input with 50-kΩ typical internal pulldown resistor, 5-V tolerant). 2. Pins 10–12, 16: LRCK, BCK, DIN, SCKI (Schmitt-trigger input, 5-V tolerant). 3. Pin 13: DOUT. 6 www.ti.com PCM3010 SLES055 – NOVEMBER 2002 electrical characteristics, all specifications at TA = 25°C, VCC1 = VCC2 = 5 V, VDD = 3.3 V, fS = 44.1 kHz, SCKI = 384 fS, 24-bit data (unless otherwise noted) (continued) PCM3010DB PARAMETER TEST CONDITIONS MIN TYP UNIT MAX ACCURACY Gain mismatch, channel-to-channel 1 kHz, full-scale input ±1 ±6 % of FSR Gain error 1 kHz, full-scale input ±2 ±6 % of FSR fS = 44.1 kHz fS = 96 kHz fS = 44.1 kHz –95 –86 fS = 96 kHz fS = 44.1 kHz, A-weighted –40 DYNAMIC PERFORMANCE (see Note 4) THD N VIN = –0.5 THD+N 0 5 dB THD+N VIN = –60 60 dB Dynamic range S/N ratio Channel separation fS = 96 kHz, A-weighted fS = 44.1 kHz, A-weighted fS = 96 kHz, A-weighted fS = 44.1 kHz dB –92 –39 97 dB 102 dB 102 95 100 dB 102 93 fS = 96 kHz 98 dB 100 ANALOG INPUT Input voltage 60% of VCC1 Center voltage 50% of VCC1 Input impedance Anti-aliasing filter frequency response –3 dB Vp–p V 20 kΩ 300 kHz DIGITAL FILTER PERFORMANCE Pass band 0.454 fS Stop band Hz ±0.05 Pass-band ripple Stop-band attenuation dB –65 Delay time HPF frequency response Hz 0.583 fS –3 dB dB 17.4/fS 0.019 fS sec mHz 24 Bits DAC CHARACTERISTICS Resolution DC ACCURACY Gain mismatch, channel-to-channel ±1.0 ±4.0 % of FSR Gain error ±2.0 ±6.0 % of FSR Bipolar zero error ±1.0 % of FSR DYNAMIC PERFORMANCE (see Note 5) THD+N, VOUT = 0 dB fS = 44.1 kHz fS = 96 kHz –96 –88 –97 dB fS = 192 kHz –97 NOTES: 4. fIN = 1 kHz, using System Two audio measurement system, RMS mode with 20-kHz LPF, 400-Hz HPF in calculation. 5. fOUT = 1 kHz, using System Two audio measurement system, RMS mode with 20-kHz LPF, 400-Hz HPF. System Two is a trademark of Audio Precision, Inc. All other trademarks are the property of their respective owners. www.ti.com 7 PCM3010 SLES055 – NOVEMBER 2002 electrical characteristics, all specifications at TA = 25°C, VCC1 = VCC2 = 5 V, VDD = 3.3 V, fS = 44.1 kHz, SCKI = 384 fS, 24-bit data (unless otherwise noted) (continued) PCM3010DB PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DYNAMIC PERFORMANCE (see Note 5) (Continued) THD+N VOUT = –60 60 dB Dynamic range fS = 44.1 kHz fS = 96 kHz fS = 192 kHz fS = 44.1 kHz, EIAJ, A-weighted fS = 96 kHz, EIAJ, A-weighted fS = 192 kHz, EIAJ, A-weighted fS = 44.1 kHz, EIAJ, A-weighted S/N ratio separation Channel se aration –42 –43 98 104 105 dB 105 98 104 105 fS = 96 kHz, EIAJ, A-weighted fS = 192 kHz, EIAJ, A-weighted fS = 44.1 kHz fS = 96 kHz fS = 192 kHz dB –43 dB 105 95 102 102 dB 103 ANALOG OUTPUT Output voltage 60% of VCC2 Center voltage 50% of VCC2 Load impedance LPF frequency response AC coupling Vp-p V 5 kΩ f = 20 kHz –0.03 f = 44 kHz –0.20 dB DIGITAL FILTER PERFORMANCE Pass band ±0.03 dB Stop band 0.454 fS 0.546 fS Hz ±0.03 Pass-band ripple Stop-band attenuation 0.546 fS –50 Delay time dB dB 20/fS ±0.1 De-emphasis error Hz sec dB POWER SUPPLY REQUIREMENTS VCC1 VCC2 VDD ICC (ICC1 + ICC2) 4.5 5.0 5.5 3.0 3.3 3.6 fS = 44.1 kHz fS = 96 kHz 31 40 fS = 192 kHz fS = 44.1 kHz 9 Voltage range Supply current IDD Power dissi dissipation, ation, o operation eration 32 10 fS = 96 kHz fS = 192 kHz 20 fS = 44.1 kHz fS = 96 kHz fS = 192 kHz 190 VDC mA 15 mA 14 250 230 mW 90 Power dissipation, power down (see Note 6) 1 mW TEMPERATURE RANGE Operating temperature –25 θJA Thermal resistance 24-pin SSOP 100 NOTES: 5. fOUT = 1 kHz, using System Two audio measurement system, RMS mode with 20-kHz LPF, 400-Hz HPF. 6. Halt SCKI, BCK, LRCK. 8 www.ti.com 85 °C °C/W PCM3010 SLES055 – NOVEMBER 2002 TYPICAL PERFORMANCE CURVES OF INTERNAL FILTER (ADC PORTION) digital filter AMPLITUDE vs FREQUENCY AMPLITUDE vs FREQUENCY 0 0 –10 –20 –30 Amplitude – dB Amplitude – dB –50 –100 –40 –50 –60 –70 –150 –80 –90 –100 0.0 –200 0 8 16 24 32 0.2 0.4 0.6 0.8 1.0 Frequency [× fS] Frequency [× fS] Figure 2. Overall Characteristics Figure 3. Stop-Band Attenuation Characteristics AMPLITUDE vs FREQUENCY AMPLITUDE vs FREQUENCY 0.2 0 –1 –2 –3 –0.2 Amplitude – dB Amplitude – dB –0.0 0.0 –0.4 –0.6 –4.13 dB @ 0.5 fS –4 –5 –6 –7 –8 –0.8 –9 –1.0 0.0 0.1 0.2 0.3 0.4 0.5 –10 0.45 0.46 0.47 0.48 0.49 0.50 0.51 0.52 0.53 0.54 0.55 Frequency [× fS] Frequency [× fS] Figure 4. Pass-Band Ripple Characteristics Figure 5. Transient Band Characteristics All specifications at TA = 25°C, VCC1 = VCC2 = 5 V, VDD = 3.3 V, fS = 44.1 kHz, SCKI = 384 fS, 24-bit data, unless otherwise noted. www.ti.com 9 PCM3010 SLES055 – NOVEMBER 2002 digital filter (continued) AMPLITUDE vs FREQUENCY AMPLITUDE vs FREQUENCY 0 0.2 –10 –0.0 0.0 –20 Amplitude – dB Amplitude – dB –30 –40 –50 –60 –70 –80 –0.2 –0.4 –0.6 –0.8 –90 –100 0.0 –1.0 0.1 0.2 0.3 0.4 0 0.5 1 Frequency [× fS/1000] 2 3 4 Frequency [× fS/1000] Figure 6. Low-Cut HPF Stop-Band Characteristics Figure 7. Low-Cut HPF Pass-Band Characteristics analog filter AMPLITUDE vs FREQUENCY 0 0.0 –0.0 –10 –0.2 Amplitude – dB Amplitude – dB AMPLITUDE vs FREQUENCY –20 –30 –40 –50 10 –0.4 –0.6 –0.8 100 1k 10k 100k 1M 10M f – Frequency – Hz –1.0 10 100 1k 10k 100k 1M f – Frequency – Hz Figure 8. Antialiasing Filter Stop-Band Characteristics Figure 9. Antialiasing Filter Pass-Band Characteristics All specifications at TA = 25°C, VCC1 = VCC2 = 5 V, VDD = 3.3 V, fS = 44.1 kHz, SCKI = 384 fS, 24-bit data, unless otherwise noted. 10 www.ti.com 10M PCM3010 SLES055 – NOVEMBER 2002 TYPICAL PERFORMANCE CURVES OF INTERNAL FILTER (DAC PORTION) digital filter AMPLITUDE vs FREQUENCY AMPLITUDE vs FREQUENCY 0 0.05 0.04 –20 0.03 0.02 Amplitude – dB Amplitude – dB –40 –60 –80 0.01 0.00 –0.01 –0.02 –100 –0.03 –120 –0.04 –140 0 1 2 3 –0.05 0.0 4 0.1 0.2 Frequency [× fS] Figure 10. Frequency Response (Sharp Rolloff) –1 0.4 –2 0.3 –3 0.2 –4 0.1 Error – dB Level – dB 0.5 –5 –6 –0.0 0.0 –0.1 –7 –0.2 –8 –0.3 –9 –0.4 4.0 6.0 8.0 10.0 0.5 ERROR vs FREQUENCY 0 2.0 0.4 Figure 11. Frequency Response, Pass-Band (Sharp Rolloff) LEVEL vs FREQUENCY –10 0.0 0.3 Frequency [× fS] 12.0 14.0 f – Frequency – kHz –0.5 0.0 2.0 4.0 6.0 8.0 10.0 12.0 14.0 f – Frequency – kHz Figure 12. De-Emphasis (fS = 32 kHz) Figure 13. De-Emphasis Error (fS = 32 kHz) All specifications at TA = 25°C, VCC1 = VCC2 = 5 V, VDD = 3.3 V, fS = 44.1 kHz, SCKI = 384 fS, 24-bit data, unless otherwise noted. www.ti.com 11 PCM3010 SLES055 – NOVEMBER 2002 digital filter (continued) ERROR vs FREQUENCY 0 0.5 –1 0.4 –2 0.3 –3 0.2 –4 0.1 Error – dB Level – dB LEVEL vs FREQUENCY –5 –6 –0.0 0.0 –0.1 –7 –0.2 –8 –0.3 –9 –0.4 –10 –0.5 0 2 4 6 8 10 12 14 16 18 20 0 2 4 6 f – Frequency – kHz Figure 14. De-Emphasis (fS = 44.1 kHz) 10 12 14 16 18 ERROR vs FREQUENCY 0.5 –1 0.4 –2 0.3 –3 0.2 –4 0.1 Error – dB 0 –5 –6 –0.0 0.0 –0.1 –7 –0.2 –8 –0.3 –9 –0.4 –10 –0.5 0 2 4 6 8 10 12 14 16 18 20 22 f – Frequency – kHz 0 2 4 6 8 10 12 14 16 18 20 22 f – Frequency – kHz Figure 16. De-Emphasis (fS = 48 kHz) Figure 17. De-Emphasis Error (fS = 48 kHz) All specifications at TA = 25°C, VCC1 = VCC2 = 5 V, VDD = 3.3 V, fS = 44.1 kHz, SCKI = 384 fS, 24-bit data, unless otherwise noted. 12 20 Figure 15. De-Emphasis Error (fS = 44.1 kHz) LEVEL vs FREQUENCY Level – dB 8 f – Frequency – kHz www.ti.com PCM3010 SLES055 – NOVEMBER 2002 analog filter AMPLITUDE vs FREQUENCY 0 –0.0 0.0 –10 –0.2 Amplitude – dB Amplitude – dB AMPLITUDE vs FREQUENCY –20 –30 –40 –0.4 –0.6 –0.8 –50 10 100 1k 10k 100k 1M –1.0 10 10M 100 1k 10k 100k 1M 10M f – Frequency – Hz f – Frequency – Hz Figure 18. Analog Filter Stop-Band Performance (10 Hz–10 MHz) Figure 19. Analog Filter Pass-Band Performance (10 Hz–10 MHz) –30 –90 –0.5 dB –35 –95 –60 dB –100 –105 –50 –40 –45 –25 0 25 50 75 TA – Free-Air Temperature – °C 100 Figure 20 DYNAMIC RANGE and SNR vs FREE-AIR TEMPERATURE 110 Dynamic Range and SNR – dB TOTAL HARMONIC DISTORTION + NOISE vs FREE-AIR TEMPERATURE THD+N – Total Harmonic Distortion + Noise at –60 dB – dB THD+N – Total Harmonic Distortion + Noise at –0.5 dB – dB TYPICAL PERFORMANCE CURVES (ADC PORTION) 105 Dynamic Range 100 SNR 95 –50 –25 0 25 50 75 100 TA – Free-Air Temperature – °C Figure 21 All specifications at TA = 25°C, VCC1 = VCC2 = 5 V, VDD = 3.3 V, fS = 44.1 kHz, SCKI = 384 fS, 24-bit data, unless otherwise noted. www.ti.com 13 PCM3010 –30 –90 –0.5 dB –35 –95 –60 dB –100 –40 –105 4.25 4.50 4.75 5.00 5.25 5.50 –45 5.75 DYNAMIC RANGE and SNR vs SUPPLY VOLTAGE 110 Dynamic Range and SNR – dB TOTAL HARMONIC DISTORTION + NOISE vs SUPPLY VOLTAGE THD+N – Total Harmonic Distortion + Noise at –60 dB – dB THD+N – Total Harmonic Distortion + Noise at –0.5 dB – dB SLES055 – NOVEMBER 2002 105 Dynamic Range 100 SNR 95 4.25 4.50 VCC – Supply Voltage – V –0.5 dB –35 –95 –60 dB –100 –40 –105 –45 48 64 5.25 5.50 80 96 fS – Sampling Frequency – kHz 112 Figure 24 110 105 Dynamic Range 100 SNR 95 16 32 48 64 80 96 fS – Sampling Frequency – kHz Figure 25 All specifications at TA = 25°C, VCC1 = VCC2 = 5 V, VDD = 3.3 V, fS = 44.1 kHz, SCKI = 384 fS, 24-bit data, unless otherwise noted. 14 5.75 DYNAMIC RANGE and SNR vs SAMPLING FREQUENCY Dynamic Range and SNR – dB –30 –90 THD+N – Total Harmonic Distortion + Noise at –60 dB – dB THD+N – Total Harmonic Distortion + Noise at –0.5 dB – dB TOTAL HARMONIC DISTORTION + NOISE vs SAMPLING FREQUENCY 32 5.00 Figure 23 Figure 22 16 4.75 VCC – Supply Voltage – V www.ti.com 112 PCM3010 SLES055 – NOVEMBER 2002 –30 –90 –35 –95 0 dB –100 –40 –60 dB –105 –50 –45 –25 0 25 50 75 100 DYNAMIC RANGE and SNR vs FREE-AIR TEMPERATURE 110 Dynamic Range and SNR – dB TOTAL HARMONIC DISTORTION + NOISE vs FREE-AIR TEMPERATURE THD+N – Total Harmonic Distortion + Noise at –60 dB – dB THD+N – Total Harmonic Distortion + Noise at 0 dB – dB TYPICAL PERFORMANCE CURVES (DAC PORTION) Dynamic Range 100 95 –50 TA – Free-Air Temperature – °C SNR 105 –25 0 –95 –35 0 dB –100 –40 –60 dB 5.00 100 5.25 5.50 –45 5.75 VCC – Supply Voltage – V DYNAMIC RANGE and SNR vs SUPPLY VOLTAGE 110 Dynamic Range and SNR – dB –30 THD+N – Total Harmonic Distortion + Noise at –60 dB – dB THD+N – Total Harmonic Distortion + Noise at 0 dB – dB –90 4.75 75 Figure 27 TOTAL HARMONIC DISTORTION + NOISE vs SUPPLY VOLTAGE 4.50 50 TA – Free-Air Temperature – °C Figure 26 –105 4.25 25 SNR 105 Dynamic Range 100 95 4.25 4.50 4.75 5.00 5.25 5.50 5.75 VCC – Supply Voltage – V Figure 28 Figure 29 All specifications at TA = 25°C, VCC1 = VCC2 = 5 V, VDD = 3.3 V, fS = 44.1 kHz, SCKI = 384 fS, 24-bit data, unless otherwise noted. www.ti.com 15 PCM3010 TOTAL HARMONIC DISTORTION + NOISE vs SAMPLING FREQUENCY –90 –30 –95 –35 0 dB –100 –40 –60 dB –105 –45 16 32 48 64 80 96 112 fS – Sampling Frequency – kHz THD+N – Total Harmonic Distortion + Noise at –60 dB – dB THD+N – Total Harmonic Distortion + Noise at 0 dB – dB SLES055 – NOVEMBER 2002 Figure 30 DYNAMIC RANGE and SNR vs SAMPLING FREQUENCY Dynamic Range and SNR – dB 110 SNR 105 Dynamic Range 100 95 16 32 48 64 80 96 112 fS – Sampling Frequency – kHz Figure 31 All specifications at TA = 25°C, VCC1 = VCC2 = 5 V, VDD = 3.3 V, fS = 44.1 kHz, SCKI = 384 fS, 24-bit data, unless otherwise noted. 16 www.ti.com PCM3010 SLES055 – NOVEMBER 2002 TYPICAL PERFORMANCE CURVES ADC output spectrum AMPLITUDE vs FREQUENCY AMPLITUDE vs FREQUENCY 0 0 –20 –20 –40 Amplitude – dB Amplitude – dB –40 –60 –80 –60 –80 –100 –100 –120 –120 –140 –140 0 5 10 15 0 20 5 10 15 20 f – Frequency – kHz f – Frequency – kHz Figure 32. Output Spectrum (–0.5 dB, N = 8192) Figure 33. Output Spectrum (–60 dB, N = 8192) DAC output spectrum AMPLITUDE vs FREQUENCY 0 0 –20 –20 –40 –40 Amplitude – dB Amplitude – dB AMPLITUDE vs FREQUENCY –60 –80 –60 –80 –100 –100 –120 –120 –140 –140 0 5 10 15 20 0 f – Frequency – kHz 5 10 15 20 f – Frequency – kHz Figure 34. Output Spectrum (0 dB, N = 8192) Figure 35. Output Spectrum (–60 dB, N = 8192) All specifications at TA = 25°C, VCC1 = VCC2 = 5 V, VDD = 3.3 V, fS = 44.1 kHz, SCKI = 384 fS, 24-bit data, unless otherwise noted. www.ti.com 17 PCM3010 SLES055 – NOVEMBER 2002 supply current SUPPLY CURRENT vs FREE-AIR TEMPERATURE SUPPLY CURRENT vs SAMPLING FREQUENCY 35 35 ICC1 + ICC2 ICC1 + ICC2 30 ICC – Supply Current – mA ICC – Supply Current – mA 30 25 20 15 IDD 10 25 20 15 IDD 10 5 0 –50 5 0 –25 0 25 50 75 100 16 TA – Free-Air Temperature – °C 32 48 64 80 96 112 fS – Sampling Frequency – kHz Figure 36 Figure 37. Supply Current vs Sampling Frequency, ADC and DAC Operating SUPPLY CURRENT vs VCC1, VCC2 SUPPLY VOLTAGE SUPPLY CURRENT vs VDD SUPPLY VOLTAGE 35 35 ICC1 + ICC2 30 ICC – Supply Current – mA ICC – Supply Current – mA 30 25 20 15 10 5 0 4.25 25 20 15 IDD 10 5 4.50 4.75 5.00 5.25 5.50 5.75 VCC1, VCC2 – Supply Voltage – V 0 2.7 3.0 3.3 3.6 VDD – Supply Voltage – V Figure 38 Figure 39 All specifications at TA = 25°C, VCC1 = VCC2 = 5 V, VDD = 3.3 V, fS = 44.1 kHz, SCKI = 384 fS, 24-bit data, unless otherwise noted. 18 www.ti.com 3.9 PCM3010 SLES055 – NOVEMBER 2002 THEORY OF OPERATION ADC portion The ADC block consists of a reference circuit, two single-ended to differential converter channels, a fifth-order delta-sigma modulator with full-differential architecture, a decimation filter with low-cut filter, and a serial interface circuit which is also used as a serial interface for the DAC input signal as shown in the block diagram, Figure 1. The analog front-end diagram illustrates the architecture of the single-ended to differential converter and antialiasing filter. Figure 40 illustrates the block diagram of the fifth-order delta-sigma modulator and transfer function. An on-chip reference circuit with two external capacitors provides all the reference voltages which are needed in the ADC portion, and defines the full-scale voltage range of both channels. An on-chip single-ended to differential signal converter saves the design, space, and extra parts cost of an external signal converter. Full-differential architecture provides a wide dynamic range and excellent power supply rejection performance. The input signal is sampled at a ×64 oversampling rate, and an on-chip antialiasing filter eliminates the external sample-hold amplifier. A fifth-order delta-sigma noise shaper, which consists of five integrators using a switched capacitor technique followed by a comparator, shapes the quantization noise generated by the comparator and 1-bit DAC outside the audio signal band. The high order delta-sigma modulation randomizes the modulator outputs and reduces the idle tone level. The 64-fS, 1-bit stream from the delta-sigma modulator is converted to a 1-fS, 24-bit or 16-bit digital signal by removing the high-frequency noise components with a decimation filter. The dc component of the signal is removed by the HPF, and the HPF output is converted to a time-multiplexed serial signal through the serial interface, which provides flexible serial formats. Analog In X(z) + – 1st SW-CAP Integrator + – 2nd SW-CAP Integrator + 3rd SW-CAP Integrator + + + + – 4th SW-CAP Integrator + 5th SW-CAP Integrator + H(z) + Qn(z) Digital Out Y(z) + Comparator 1-Bit DAC Y(z) = STF(z) * X(z) + NTF(z) * Qn(z) Signal Transfer Function STF(z) = H(z) / [1 + H(z)] Noise Transfer Function NTF(z) = 1 / [1 + H(z)] Figure 40. Block Diagram of Fifth-Order Delta-Sigma Modulator www.ti.com 19 PCM3010 SLES055 – NOVEMBER 2002 DAC portion The DAC portion is based on the delta-sigma modulator, which consists of an 8-level amplitude quantizer and a 4th-order noise shaper. This section converts the oversampled input data to the 8-level delta-sigma format. A block diagram of the 8-level delta-sigma modulator is shown in Figure 41. This 8-level delta-sigma modulator has the advantage of improved stability and clock jitter over the typical one-bit (2-level) delta-sigma modulator. The combined oversampling rate of the delta-sigma modulator and the internal 8× interpolation filter is 64 fS for all system clocks. The theoretical quantization noise performance of the 8-level delta-sigma modulator is shown in Figure 42. IN 8 fS + + – Z–1 + + + Z–1 + Z–1 – + + + + 8-Level Quantizer OUT 64 fS Figure 41. 8-Level Delta-Sigma Modulator Block Diagram 20 www.ti.com + + Z–1 PCM3010 SLES055 – NOVEMBER 2002 DYNAMIC RANGE vs JITTER AMPLITUDE vs FREQUENCY 125 0 –20 120 Dynamic Range – dB Amplitude – dB –40 –60 –80 –100 –120 115 110 105 100 –140 95 –160 90 –180 0 1 2 3 4 Frequency [ 5 6 7 0 8 100 200 300 400 500 600 Jitter – ps fS] Figure 42. Quantization Noise Spectrum ( 64 Oversampling) Figure 43. Jitter Dependence ( 64 Oversampling) system clock The system clock for the PCM3010 must be 128 fS, 192 fS, 256 fS, 384 fS, 512 fS or 768 fS, where fS is the audio sampling rate, 16 kHz to 192 kHz. The PCM3010 detects 128 fS, 192 fS, 256 fS, 384 fS, 512 fS or 768 fS automatically with the built-in circuit. Operation at the 192-kHz sampling rate is available on the DAC only, and when a system clock of 128 fS or 192 fS is detected, the ADC is disabled (DOUT = LOW). Table 1 lists the typical system clock frequency, and Figure 44 illustrates the system clock timing. Table 1. Typical System Clock SAMPLING RATE FREQUENCY (fS) – LRCK 128 fS 192 fS 256 fS 32 kHz – – 8.192 384 fS 12.288 512 fS 16.384 768 fS 24.576 44.1 kHz – – 11.2896 16.9344 22.5792 33.8688 48 kHz – – 12.288 18.432 24.576 36.864 96 kHz – 24.576† – 36.864† 24.576 36.864 49.152 – – – – – 192 kHz SYSTEM CLOCK FREQUENCY – MHz † DAC only. www.ti.com 21 PCM3010 SLES055 – NOVEMBER 2002 system clock (continued) tSCKH 2.0 V System Clock 0.8 V tSCKL 1/128 fS or 1/192 fS 1/256 fS or 1/384 fS 1/512 fS or 1/768 fS PARAMETER tSCKH tSCKL MIN MAX UNIT System clock pulse duration HIGH 8 ns System clock pulse duration LOW 8 ns Figure 44. System Clock Timing power supply on, external reset, and power down The PCM3010 has both an internal power-on reset circuit and an external reset circuit. The sequences for both resets are explained as follows. Figure 45 is the timing diagram for the internal power-on reset. Two power-on reset circuits are implemented for VCC1 and VDD, respectively. Initialization (reset) occurs automatically when VCC1 and VDD exceed 4.0 V and 2.2 V, typically. Internal reset is released 1024 SCKI clock cycles following the release from power-on reset, and the PCM3010 begins normal operation. VOUTL and VOUTR from the DAC are forced to the VCOM (= 0.5 VCC2) level as VCC2 rises. When synchronization between SCKI, BCK and LRCK is obtained while VOUTL and VOUTR go into the fade sequence and provide outputs corresponding to DIN after tDACDLY1 = 2100/fS following release from power-on reset. On the other hand, DOUT from the ADC provides an output corresponding to VINL and VINR after tADCDLY1 = 4500/fS following release from power-on reset. If the synchronization is not held, the internal reset is not released and device operation remains in the power-down mode. After resynchronization, the DAC performs the fade-in sequence and the ADC resumes normal operation following internal initialization. Figure 46 is the external-reset timing diagram. External forced reset, driving the PDWN pin LOW, puts the PCM3010 in the power-down mode, which is its lowest power-dissipation state. When PDWN transitions from HIGH to LOW while synchronization is maintained between SCKI, BCK, and LRCK, then VOUTL and VOUTR are faded out and forced to the VCOM (= 0.5 VCC2) level after tDACDLY1 = 2100/fS. At the same time as the internal reset becomes LOW, DOUT becomes ZERO, the PCM3010 enters into power-down mode. To enter into normal operation mode again, change PDWN to HIGH again. The reset sequence shown in Figure 45 occurs. Notes: 1. A large popping noise may be generated on VOUTL and VOUTR when the power supply is turned off during normal operation. 2. To switch PDWN during fade in or fade out causes an immediate change between fade in and fade out. 3. To switch the control pins on the fly during normal operation can degrade analog performance. It is recommended that changing control pins, changing clocks, stopping clocks, turning power supplies off, etc., be done in the power-down mode. 22 www.ti.com PCM3010 SLES055 – NOVEMBER 2002 power supply on, external reset and power down (continued) VCC1, VDD 0V (VCC1 = 5 V, VDD = 3.3 V, Typ) (VCC1 = 4 V, VDD = 2.2 V, Typ) LRCK, BCK, SCKI Synchronous Clocks PDWN 1024 SCKI Internal Reset Normal Operation Power Down tDACDLY1 2100/fS VOUTL, VOUTR VCOM (0.5 VCC2) tADCDLY1 4500/fS DOUT Zero Figure 45. DAC Output and ADC Output for Power-On Reset VCC1, VDD LRCK, BCK, SCKI (VCC1 = 5 V, VDD = 3.3 V, Typ) 0V Synchronous Clocks Synchronous Clocks PDWN 1024 SCKI Internal Reset Normal Operation Power Down tDACDLY1 2100/fS Normal Operation tDACDLY1 2100/fS VCOM (0.5 VCC2) VOUTL, VOUTR tADCDLY1 4500/fS DOUT Zero Figure 46. DAC Output and ADC Output for External Reset (PDWN Pin) www.ti.com 23 PCM3010 SLES055 – NOVEMBER 2002 PCM audio interface Digital audio data is interfaced to the PCM3010 on LRCK (pin 10), BCK (pin 11), DIN (pin 12), and DOUT (pin 13). The PCM3010 can accept the following 16-bit and 24-bit formats. These formats are selected through FMT0 (pin 7) and FMT1 (pin 8), as shown in Table 2. Table 2. Audio Data Format Select FMT1 FMT0 DAC DATA FORMAT ADC DATA FORMAT LOW LOW 24-bit, MSB-first, right-justified 24-bit, MSB-first, left-justified LOW HIGH 16-bit, MSB-first, right-justified 24-bit, MSB-first, left-justified HIGH LOW HIGH HIGH 24-bit, MSB-first, left-justified 24-bit, MSB-first, I2S 24-bit, MSB-first, left-justified 24-bit, MSB-first, I2S The PCM3010 accepts two combinations of BCK and LRCK, 64 or 48 clocks of BCK in one clock of LRCK. The following figures illustrate audio data input/output format and timing. FORMAT 0: FMT[1:0] = 00 DAC: 24-Bit, MSB-First, Right-Justified Left Channel LRCK Right Channel BCK DIN 24 1 2 3 22 23 24 MSB 1 2 3 22 23 24 MSB LSB LSB ADC: 24-Bit, MSB-First, Left-Justified Left Channel LRCK Right Channel BCK DOUT 1 2 3 22 23 24 1 LSB MSB 2 3 22 23 24 1 LSB MSB FORMAT 1: FMT[1:0] = 01 DAC: 16-Bit, MSB-First, Right-Justified Left Channel LRCK Right Channel BCK DIN 16 1 2 3 14 15 16 MSB 1 2 3 14 15 16 MSB LSB LSB ADC: 24-Bit, MSB-First, Left-Justified Left Channel LRCK Right Channel BCK DOUT 1 2 MSB 3 22 23 24 LSB 1 2 3 MSB Figure 47. Audio Data Input/Output Format 24 www.ti.com 22 23 24 LSB 1 PCM3010 SLES055 – NOVEMBER 2002 PCM audio interface (continued) FORMAT 2: FMT[1:0] = 10 DAC: 24-Bit, MSB-First, Left-Justified Left Channel LRCK Right Channel BCK DIN 1 2 3 22 23 24 MSB LSB 1 2 3 22 23 24 MSB 1 LSB ADC: 24-Bit, MSB-First, Left-Justified Left Channel LRCK Right Channel BCK DOUT 1 2 3 22 23 24 LSB MSB 1 2 3 22 23 24 1 LSB MSB FORMAT 3: FMT[1:0] = 11 DAC: 24-Bit, MSB-First, I2S Left Channel LRCK Right Channel BCK DIN 1 2 3 22 23 24 MSB LSB 1 2 3 22 23 24 MSB LSB ADC: 24-Bit, MSB-First, I2S Left Channel LRCK Right Channel BCK DOUT 1 2 MSB 3 22 23 24 LSB 1 2 3 MSB 22 23 24 LSB Figure 48. Audio Data Input/Output Format (Continued) www.ti.com 25 PCM3010 SLES055 – NOVEMBER 2002 PCM audio interface (continued) tLRP 1.4 V LRCK tBCL tBCH tLB tBL 1.4 V BCK tBCY tDIS tDIH 1.4 V DIN tCKDO tLRDO 0.5 VDD DOUT PARAMETER MIN MAX UNIT tBCY tBCH BCK pulse cycle time 80 ns BCK pulse duration, HIGH 35 ns tBCL tBL BCK pulse duration, LOW 35 ns BCK rising edge to LRCK edge 10 ns tLB tLRP LRCK edge to BCK rising edge 10 ns LRCK pulse duration 2.1 µs tDIS tDIH DIN setup time 10 ns DIN hold time 10 ns tCKDO tLRDO DOUT delay time from BCK falling edge 20 ns DOUT delay time from LRCK edge 20 ns tR tF Rising time of all signals 10 ns Falling time of all signals 10 ns Figure 49. Audio Data Input/Output Timing synchronization with digital audio system The PCM3010 operates with LRCK and BCK synchronized to the system clock. The PCM3010 does not need a specific phase relationship between LRCK, BCK and the system clock, but does require the synchronization of LRCK, BCK, and the system clock. If the relationship between system clock and LRCK changes more than ±6 BCKs during one sample period due to LRCK jitter, etc., internal operation of DAC halts within 6/fS, and the analog output is forced to 0.5 VCC2 until resynchronization between the system clock, LRCK, and BCK is completed and then tDACDLY2 elapses. Internal operation of the ADC also halts within 6/fS, and the digital output is forced to a ZERO code until resynchronization between the system clock, LRCK, and BCK is completed, and then tADCDLY2 elapses. In the case of changes less than ±5 BCKs, resynchronization does not occur and the previously described discontinuity in analog/digital output control does not occur. 26 www.ti.com PCM3010 SLES055 – NOVEMBER 2002 synchronization with digital audio system (continued) Figure 50 illustrates the DAC analog output and ADC digital output for loss of synchronization. During undefined data, some noise may be generated in the audio signal. Also, the transition from normal to undefined data and from undefined or zero data to normal creates a data discontinuity on the analog and digital outputs, which may generate some noise in the audio signal. State of Synchronization SYNCHRONOUS ASYNCHRONOUS SYNCHRONOUS Within 6/fS DAC VOUT NORMAL DATA tDACDLY2 32/fS UNDEFINED DATA VCOM (0.5 VCC2) NORMAL DATA tADCDLY2 32/fS ADC DOUT NORMAL DATA UNDEFINED DATA NORMAL DATA ZERO DATA Figure 50. DAC Output and ADC Output for Lost of Synchronization de-emphasis control DEMP1, DEMP0: De-emphasis control pins select the de-emphasis mode of the DACs as shown below. DEMP1 DEMP0 LOW LOW De-emphasis 44.1 kHz ON DESCRIPTION LOW HIGH De-emphasis OFF HIGH LOW De-emphasis 48 kHz ON HIGH HIGH De-emphasis 32 kHz ON test control TEST: The TEST pin is used for device testing; it must be connected to DGND for normal operation. www.ti.com 27 PCM3010 SLES055 – NOVEMBER 2002 typical circuit connection The following figure illustrates typical circuit connection. 5V 3.3 V 0V (See Note C) L-Ch IN (See Note C) R-Ch IN (See Note B) Control + + + (See Note B) + (See Note A) + 1 VINL VCOM 24 2 VINR VOUTL 23 3 VREF1 4 VREF2 22 (See Note B) + (See Note D) + (See Note D) + (See Note A) Post LPF Post LPF VCC2 21 5 VCC1 AGND2 20 6 AGND1 DEMP0 19 De-emphasis 0 Format 0 7 FMT0 DEMP1 18 De-emphasis 1 Format 1 8 FMT1 PDWN 17 Power Down 9 TEST SCKI 16 System Clock Clock L/R Clock 10 LRCK VDD 15 Bit Clock 11 BCK DGND 14 12 DIN DOUT 13 Data OUT Data Clock Data VOUTR + Data IN + Control (See Note A) NOTES: A. 0.1 µF ceramic and 10 µF electrolytic capacitors typical, depending on power supply quality and pattern layout. B. 0.1 µF ceramic and 10 µF electrolytic capacitors are recommended. C. 1 µF electrolytic capacitor typical, gives 8-Hz cutoff frequency of input HPF in normal operation and gives settling time with 20 ms (1 µF × 20 kΩ) time constant in power ON and power down OFF period. D. 10 µF electrolytic capacitor typical, gives 2-Hz cutoff frequency for 10-kΩ post-LPF input resistance in normal operation and gives settling time with 100 ms (10 µF × 10 kΩ) time constant in power ON and power down OFF period. design and layout considerations in application power supply pins (VCC1, VCC2, VDD) The digital and analog power supply lines to the PCM3010 should be bypassed to the corresponding ground pins, with 0.1-µF ceramic and 10-µF electrolytic capacitors as close to the pins as possible to maximize the dynamic performance of the ADC and the DAC. Although the PCM3010 has three power lines to maximize the potential of dynamic performance, using one common 5-V power supply for VCC1 and VCC2 and a 3.3-V power supply, which is generated from the 5-V VCC1 and VCC2 power supply, for VDD. This power supply arrangement is recommended to avoid unexpected power supply trouble, like latch-up or power supply sequencing problems. grounding (AGND1, AGND2, DGND) To maximize the dynamic performance of the PCM3010, the analog and digital grounds are not connected internally. These points should have very low impedance to avoid digital noise feeding back into the analog ground. They should be connected directly to each other under the connected parts to reduce the potential for noise problems. 28 www.ti.com PCM3010 SLES055 – NOVEMBER 2002 VIN pins A 1-µF electrolytic capacitor is recommended as an ac-coupling capacitor, which gives an 8-Hz cutoff frequency. If a higher full-scale input voltage is required, it can be adjusted by adding only one series resistor to each VIN pin. VREF1, VREF2 pins A 0.1-µF ceramic capacitor and a 10-µF electrolytic capacitor are recommended between VREF1, VREF2, and AGND1 to ensure low source impedance of the ADC references. These capacitors should be located as close as possible to the VREF1 and VREF2 pins and the AGND1 pin to reduce dynamic errors on the ADC references. VCOM pin A 0.1-µF ceramic capacitor and a 10-µF electrolytic capacitor are recommended between VCOM and AGND2 to ensure low source impedance of the DAC common voltage. These capacitors should be located as close as possible to the VCOM pin to reduce dynamic errors on the DAC common voltage. system clock The quality of SCKI may influence dynamic performance, as the PCM3010 (both DAC and ADC) operates based on SCKI. Therefore, it may be necessary to consider the jitter, duty cycle, rise and fall time, etc., of the system clock. reset control If large capacitors (more than 22 µF) are used on VREF1, VREF2, and VCOM, external reset control by PDWN = LOW is required after the VREF1, VREF2, and VCOM transient response settles. external mute control To eliminate the clicking noise which is generated by DAC output dc level change during power-down ON/OFF control, external mute control is generally required. The recommended control sequence is: external mute ON, codec power down ON, SCKI stop and restart if necessary, codec power down OFF, and external mute OFF. www.ti.com 29 PCM3010 SLES055 – NOVEMBER 2002 MECHANICAL DATA DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. 30 All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-150 www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third–party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Mailing Address: Texas Instruments Post Office Box 655303 Dallas, Texas 75265 Copyright 2002, Texas Instruments Incorporated