PCS2P5T9050A November 2006 rev 0.2 2.5V Single Data Rate1:5 Clock Buffer Terabuffer Features The PCS2P5T9050A 2.5V single data rate (SDR) clock • Optimized for 2.5V LVTTL buffer is a single-ended input to five single-ended outputs • Guaranteed Low Skew < 25pS (max) buffer built on advanced metal CMOS technology. The • Very low duty cycle distortion< 300pS (max) SDR • High speed propagation delay < 1.8nS. (max) single-ended outputs reduces the loading on the preceding • Up to 200MHz operation driver and provides an efficient clock distribution network. • Very low CMOS power levels Multiple power and grounds reduce noise. • Hot Insert able and over-voltage tolerant inputs • 1:5 fan-out buffer • 2.5V Supply Voltage • Available in TSSOP Package clock buffer fan-out from a single input to five Applications: PCS2P5T9050A is targeted towards Clock and signal distribution applications. Functional Description Block Diagram GL G OUTPUT CONTROL Q1 OUTPUT CONTROL Q2 OUTPUT CONTROL Q3 OUTPUT CONTROL Q4 OUTPUT CONTROL Q5 A PulseCore Semiconductor Corporation 1715 S. Bascom Ave Suite 200, Campbell, CA 95008 • Tel: 408-879-9077 • Fax: 408-879-9018 www.pulsecoresemi.com Notice: The information in this document is subject to change without notice. PCS2P5T9050A November 2006 rev 0.2 Pin Configuration- Top View – TSSOP Package GL 1 28 GND VDD 2 27 VDD GND 3 26 GND G 4 25 GND VDD 5 24 VDD Q1 6 23 Q2 22 GND PCS2P5T9050A GND 7 A 8 21 Q3 Q5 9 20 Q4 VDD 10 19 VDD GND 11 18 GND VDD 12 17 GND VDD 13 16 VDD NC 14 15 NC Pin Description Symbol I/O Type A I LVTTL G I LVTTL GL I LVTTL Qn O LVTTL Description Clock input Gate control for Qn outputs. When G is LOW, these outputs are enabled. When G is HIGH, these outputs are asynchronously disabled to the level designated by GL1. Specifies output disable level. If HIGH, the outputs disable HIGH. If LOW, the outputs disable LOW. Clock outputs VDD PWR Power supply for the device core, inputs, and outputs GND PWR Power supply return for power NOTE: 1. Because the gate controls are asynchronous, runt pulses are possible. It is the user's responsibility to either time the gate control signals to minimize the possibility of runt pulses or be able to tolerate them in down stream circuitry. 2.5V Single Data Rate1:5 Clock Buffer Terabuffer Notice: The information in this document is subject to change without notice. 2 of 10 PCS2P5T9050A November 2006 rev 0.2 Absolute Maximum Ratings Symbol Max Unit Power Supply Voltage -0.5 to +3.6 V VI Input Voltage -0.5 to +3.6 V VO Output Voltage -0.5 to VDD +0.5 V VDD Description TSTG Storage Temperature -65 to +165 °C TJ Junction Temperature 150 °C Note: 1. These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect device reliability. Capacitance1 (TA = +25°C, F = 1.0MHz) Symbol Parameter Min CIN Input Capacitance Typ Max Unit 6 pF NOTE: 1. This parameter is measured at characterization but not tested. Recommended Operating Range Symbol Description Min Typ Max Unit TA Ambient Operating Temperature -40 +25 +85 °C VDD Internal Power Supply Voltage 2.3 2.5 2.7 V 2.5V Single Data Rate1:5 Clock Buffer Terabuffer Notice: The information in this document is subject to change without notice. 3 of 10 PCS2P5T9050A November 2006 rev 0.2 DC Electrical Characteristics Over Operating Range1 Symbol Parameter IIH Input HIGH Current VDD= 2.7V IIL Input LOW Current VDD= 2.7V VIK Clamp Diode Voltage VIN DC Input Voltage -0.3 VIH DC Input HIGH2 1.7 VIL DC Input LOW3 VOH Output HIGH Voltage VOL Test Conditions Min Typ4 Max Unit VI = VDD/GND ±5 µA VI = GND/VDD ±5 VDD= 2.3V, IIN= -18mA -0.7 - 1.2 V +3.6 V V 0.7 Output LOW Voltage V IOH= -12mA VDD- 0.4 V IOH= -100µA VDD- 0.1 V IOL= 12mA 0.4 V IOL= 100µA 0.1 V NOTES: 1. See RECOMMENDED OPERATING RANGE table. 2. Voltage required to maintain a logic HIGH. 3. Voltage required to maintain a logic LOW. 4. Typical values are at VDD = 2.5V, +25°C ambient. Power Supply Characteristics Symbol IDDQ IDDD Test Conditions1 Parameter Quiescent VDD Power Supply VDD= Max., Reference Clock = LOW Current Outputs enabled, All outputs unloaded Dynamic VDD Power Supply VDD= Max., CL= 0pF Current per Output Typ Max Unit 1 1.5 mA 100 150 µA/MHz 50 65 VDD= 2.5V., FREFERENCE CLOCK = 100MHz, ITOT Total Power VDD Supply Current CL= 15pF VDD= 2.5V., FREFERENCE CLOCK = 200MHz, CL= 15pF mA 75 100 NOTE: 1. The termination resistors are excluded from these measurements. 2.5V Single Data Rate1:5 Clock Buffer Terabuffer Notice: The information in this document is subject to change without notice. 4 of 10 PCS2P5T9050A November 2006 rev 0.2 Input AC Test Conditions Symbol Parameter Value Units VIH Input HIGH Voltage VDD V VIL Input LOW Voltage 0 V VTH Input Timing Measurement Reference Level1 VDD/2 V tR, tF Input Signal Edge Rate2 2 V/nS NOTES: 1. A nominal 1.25V timing measurement reference level is specified to allow constant, repeatable results in an automatic test equipment (ATE) environment. 2. The input signal edge rate of 2V/nS or greater is to be maintained in the 10% to 90% range of the input waveform. AC Electrical Characteristics Over Operating Range4 Symbol Skew Parameters Parameter Min Typ Max Unit tSK(O) Same Device Output Pin-to-Pin Skew1 25 pS tSK(P) Pulse Skew2 300 pS tSK(PP) Part-to-Part Skew3 300 pS 1.8 nS Propagation Delay tPLH tPHL Propagation Delay A to Qn tR Output Rise Time (20% to 80%) 350 850 pS tF Output Fall Time (20% to 80%) 350 850 pS fO Frequency Range 200 MHz 3.5 nS 3 nS Output Gate Enable/Disable Delay tPGE Output Gate Enable to Qn tPGD Output Gate Enable to Qn Driven to GL Designated Level NOTES: 1. Skew measured between all outputs under identical input and output transitions and load conditions on any one device. 2. Skew measured is the difference between propagation delay times tPHL and tPLH of any output under identical input and output transitions and load conditions on any one device. 3. Skew measured is the magnitude of the difference in propagation times between any outputs of two devices, given identical transitions and load conditions at identical VDD levels and temperature. 4. Guaranteed by design. 2.5V Single Data Rate1:5 Clock Buffer Terabuffer Notice: The information in this document is subject to change without notice. 5 of 10 PCS2P5T9050A November 2006 rev 0.2 AC Timing Waveforms Propagation and Skew Waveforms NOTE: Pulse Skew is calculated using the following expression: tSK(P) = | tPHL - tPLH | where tPHL and tPLH are measured on the controlled edges of any one output from rising and falling edges of a single pulse. Please note that the tPHL and tPLH shown are not valid measurements for this calculation because they are not taken from the same pulse. Gate Disable/Enable Showing Runt Pulse Generation NOTE: As shown, it is possible to generate runt pulses on gate disable and enable of the outputs. It is the user's responsibility to time their G signal to avoid this problem. 2.5V Single Data Rate1:5 Clock Buffer Terabuffer Notice: The information in this document is subject to change without notice. 6 of 10 PCS2P5T9050A November 2006 rev 0.2 Test Circuit and Conditions Test Circuit for Input/Output Input/Output Test Conditions Symbol VDD= 2.5V ± 0.2V VTH VDD/ 2 V R1 100 Ω R2 100 Ω CL 15 pF 2.5V Single Data Rate1:5 Clock Buffer Terabuffer Notice: The information in this document is subject to change without notice. Unit 7 of 10 PCS2P5T9050A November 2006 rev 0.2 Package Diagram 28L TSSOP (173 mil) Dimensions Symbol Inches Min Max Millimeters Min Max A …. 0.043 … 1.2 A1 0.0020 0.0059 0.05 0.15 A2 0.031 0.041 0.80 1.05 D 0.3779 0.3858 9.60 9.80 L 0.020 0.030 0.50 0.75 E 0.252 BSC 6.40 BSC E1 0.169 0.177 4.30 4.50 R 0.004 …. 0.09 ….. R1 0.004 …. 0.09 ….. b 0.007 0.012 0.19 0.30 b1 0.007 0.010 0.19 0.25 c 0.004 0.008 0.09 0.20 c1 0.004 0.006 0.09 0.16 L1 e θ1 θ2 θ3 0.039 REF 1.0 REF 0.026 BSC 0° 0.65 BSC 8° 0° 8° 12° REF 12° REF 12° REF 12° REF 2.5V Single Data Rate1:5 Clock Buffer Terabuffer Notice: The information in this document is subject to change without notice. 8 of 10 PCS2P5T9050A November 2006 rev 0.2 Ordering Information Part Number Marking Package Type Operating Range PCS2P5T9050AF-28TT 2P5T9050AF 28 Pin TSSOP, Tube, Pb Free Commercial PCS2P5T9050AF-28TR 2P5T9050AF 28 Pin TSSOP, Tape and Reel, Pb Free Commercial PCS2I5T9050AF-28TT 2I5T9050AF 28 Pin TSSOP, TUBE, Pb Free PCS2I5T9050AF-28TR 2I5T9050AF 28 Pin TSSOP, Tape and Reel, Pb Free PCS2P5T9050AG-28TT 2P5T9050AG 28 Pin TSSOP, Tube, Green Commercial PCS2P5T9050AG-28TR 2P5T9050AG 28 Pin TSSOP, Tape and Reel, Green Commercial Industrial Industrial PCS2I5T9050AG-28TT 2I5T9050AG 28 Pin TSSOP, TUBE, Green Industrial PCS2I5T9050AG-28TR 2I5T9050AG 28 Pin TSSOP, Tape and Reel, Green Industrial Ordering Information P C S 2 P 5 T 9 0 5 0 A F - 2 8 T R OR – TSOT23 -6,T/R TT – TSSOP, TUBE TR – TSSOP, T/R VT – TVSOP, TUBE VR – TVSOP, T/R ST – SOIC, TUBE AR – SSOP, T/R AT – SSOP, TUBE SR QR QT BT BR UR DR DT – SOIC, T/R – QFN, T/R – QFN, TRAY – BGA, TRAY – BGA, T/R – SOT-23, T/R – QSOP, T/R – QSOP, TUBE PIN COUNT LEAD FREE PART F = LEAD FREE AND RoHS COMPLIANT PART G = GREEN PACKAGE, LEAD FREE, and RoHS X = Automotive (-40C to +125C) I = Industrial P or n/c = Commercial (-40C to +85C) (0C to +70C) 1 – reserved 2 – Non PLL based 3 – EMI Reduction 4 – DDR support products 5 – STD Zero Delay Buffer 6 – power management 7 – power management 8 – power management 9 – Hi performance 0 - reserved PulseCore Semiconductor Mixed Signal Product Licensed under US patent #5,488,627, #6,646,463 and #5,631,920. 2.5V Single Data Rate1:5 Clock Buffer Terabuffer Notice: The information in this document is subject to change without notice. 9 of 10 PCS2P5T9050A November 2006 rev 0.2 PulseCore Semiconductor Corporation 1715 S. Bascom Ave Suite 200 Campbell, CA 95008 Tel: 408-879-9077 Fax: 408-879-9018 www.pulsecoresemi.com Copyright © PulseCore Semiconductor All Rights Reserved Preliminary Information Part Number: PCS2P5T9050 Document Version: 0.2 Note: This product utilizes US Patent # 6,646,463 Impedance Emulator Patent issued to PulseCore Semiconductor, dated 11-11-2003 © Copyright 2006 PulseCore Semiconductor Corporation. All rights reserved. Our logo and name are trademarks or registered trademarks of PulseCore Semiconductor. All other brand and product names may be the trademarks of their respective companies. PulseCore reserves the right to make changes to this document and its products at any time without notice. PulseCore assumes no responsibility for any errors that may appear in this document. The data contained herein represents PulseCore’s best data and/or estimates at the time of issuance. PulseCore reserves the right to change or correct this data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. PulseCore does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of PulseCore products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in PulseCore’s Terms and Conditions of Sale (which are available from PulseCore). All sales of PulseCore products are made exclusively according to PulseCore’s Terms and Conditions of Sale. The purchase of products from PulseCore does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of PulseCore or third parties. PulseCore does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of PulseCore products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify PulseCore against all claims arising from such use.. 2.5V Single Data Rate1:5 Clock Buffer Terabuffer Notice: The information in this document is subject to change without notice. 10 of 10