(Preliminary) PL611s-06 Low-Power Programmable Quick Turn Clock T M FEATURES DESCRIPTION • Advanced low-power, space saving programmable PLL design • Very low Jitter and Phase Noise (30-70ps Pk-Pk typical) • Up to 2 programmable clock outputs • CMOS output frequency up to 35MHz. • Accepts Crystal or Ref Clock input o Fundamental Crystal: 10MHz to 30MHz o Reference Input: 1MHz to 100MHz • Accepts >0.1V reference signal input voltage • Single 1.8V, 2.5V, or 3.3V ± 10% power supply • Operating temperature range from -40°C to 85°C • Available in 6-pin DFN, SC70, and SOT23, GREEN /RoHS compliant packages The PL611s-06 is a low-power general purpose frequency synthesizer and a member of PhaseLink’s Programmable ‘Quick Turn Clock (QTC)’ family. PhaseLink’s PL611s-06 can generate two system clock frequencies of up to 35MHz from a 10MHz to 30MHz fundamental crystal or a 1MHz to 100MHz Reference clock source. The PL611s-06 offers the best phase noise and jitter performance, and power consumption of its rivals. Cascading of the ICs to produce additional clock frequencies is also supported. PACKAGE PIN CONFIGURATION 6 5 4 XOUT VDD OE, CLK1 CLK0 XIN, FIN 2 3 6 CLK0 5 VDD 4 XOUT OE, CLK1 1 GND 2 XIN, FIN 3 PL611s-06 1 2 3 PL611s-06 XIN, FIN OE, CLK1 GND 1 PL611s-06 GND 6 CLK0 5 VDD 4 XOUT DFNDFN-6L SC70 SC7070-6L SOT23 SOT2323-6L (2.0mmx1 mmx1.3mmx0 mmx0.6mm) mm) (2.3mmx2 mmx2.25mmx 25mmx1 mmx1.0mm) mm) (3.0mmx3 mmx3.0mmx1 mmx1.35mm 35mm) mm) BLOCK DIAGRAM XIN/FIN XOUT XTAL OSC Programmable CLoad FREF R-Counter (8-bit) Phase Detector M-Counter (11-bit) F VCO = F REF * (2 * M/R) FOUT = F VCO / (2 * P) Programmable Function P-Counter (5-bit) Programming Logic Charge Pump Loop Filter VCO CLK OE, CLK1 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 12/12/06 Page 1 (Preliminary) PL611s-06 Low-Power Programmable Quick Turn Clock T M KEY PROGRAMMING PARAMETERS CLK Output Frequency Programmable Input/Output Output Drive Strength FOUT = FREF * M / (R * P) Where M = 11 bit R = 8 bit P = 5 bit CLK0 = FOUT, FREF or FREF / (2*P) CLK1 = FREF, FREF/2, CLK0 or CLK0/2 Three optional drive strengths to choose from: One output pin can be configured as: • Low: 4mA • Std: 8mA (default) • High: 16mA • OE - input • CLK1 – output PACKAGE PIN ASSIGNMENT Name Pin Assignment SOT23 SC70 DFN Pin # Pin# Pin# Type Description OE, CLK1 1 2 2 B This programmable I/O pin can be configured as an Output Enable (OE) input, or CLK1 output. This pin has an internal 60KΩ pull up resistor (OE Function Only). GND 2 1 3 P GND connection XIN, FIN 3 3 1 I Crystal or Reference input pin XOUT 4 4 6 O Crystal Output pin Do Not Connect (DNC ) when FIN is present VDD 5 5 5 P VDD connection CLK0 6 6 4 O Programmable Clock Output 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 12/12/06 Page 2 (Preliminary) PL611s-06 Low-Power Programmable Quick Turn Clock T M FUNCTIONAL DESCRIPTION PL611s-06 is a highly featured, very flexible, advanced programmable PLL design for high performance, lowpower, small form-factor applications. The PL611s-06 accepts a fundamental crystal input of 10MHz to 30MHz or reference clock input of 1MHz to 100MHz and is capable of producing two outputs up to 35MHz. This flexible design allows the PL611s-06 to deliver any PLL generated frequency, F REF (Crystal or Ref Clk) frequency or F REF /2 to CLK0 and/or CLK1. Some of the design features of the PL611s-06 are mentioned below: PLL Programming Clock Output (CLK1) The PLL in the PL611s-06 is fully programmable. The PLL is equipped with an 8-bit input frequency divider (R-Counter), and an 11-bit VCO frequency feedback loop divider (M-Counter). The output of the PLL is transferred to a 5-bit post VCO divider (PCounter). The output frequency is determined by the following formula [F OUT = F REF * M / (R * P) ]. The CLK1 feature allows the PL611s-06 to have an additional clock output. This output can be programmed to one of the following: F REF - Reference ( Crystal or Ref Clk ) Frequency F REF / 2 CLK0 CLK0 / 2 Clock Output (CLK0) CLK0 is the main clock output. The output of CLK0 can be configured as the PLL output (F VCO /(2*P)), F REF (Crystal or Ref Clk Frequency) output, or F REF /2 output. The output drive level can be programmed to Low Drive (4mA), Standard Drive (8mA) or High Drive (16mA). The maximum output frequency is 35MHz. Output Enable (OE) The Output Enable feature allows the user to enable and disable the clock output(s) by toggling the OE pin. The OE pin incorporates a 60kΩ pull up resistor giving a default condition of logic “1”. 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 12/12/06 Page 3 (Preliminary) PL611s-06 Low-Power Programmable Quick Turn Clock T M ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS PARAMETERS SYMBOL MIN. MAX. UNITS Supply Voltage Range V DD 7 V Input Voltage Range Output Voltage Range Soldering Temperature (Green package) VI VO - 0.5 - 0.5 - 0.5 V DD + 0.5 V DD + 0.5 260 V V °C Year 10 Data Retention @ 85°C Storage Temperature Ambient Operating Temperature* TS -65 -40 150 85 °C °C Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. *Operating temperature is guaranteed by design. Parts are tested to commercial grade only. AC SPECIFICATIONS PARAMETERS Crystal Input Frequency (XIN) Input (FIN) Frequency Input (FIN) Signal Amplitude Input (FIN) Signal Amplitude Output Frequency Settling Time Output Enable Time VDD Sensitivity Output Rise Time Output Fall Time CONDITIONS MIN. TYP. MAX. UNITS Fundamental Crystal @ VDD =3.3V @ VDD =2.5V @ VDD =1.8V 10 30 MHz 1 100 MHz Internally AC coupled (High Frequency) Internally AC coupled (Low Frequency) 3.3V <50MHz, 2.5V <40MHz, 1.8V <15MHz @ VDD =3.3V @ VDD =2.5V @ VDD =1.8V 0.9 VDD Vpp 0.1 VDD V pp 35 MHz MHz MHz 1.2 1.2 2 10 2 2 1.7 1.7 ms ns ms ppm ns ns 50 55 % At power-up (after VDD increases over 1.62V) OE Function; Ta=25º C, 15pF Load PDB Function; Ta=25º C, 15pF Load Frequency vs. VDD +/-10% 15pF Load, 10/90% VDD, High Drive, 3.3V 15pF Load, 90/10% VDD, High Drive, 3.3V Duty Cycle PLL Enabled, @ VDD /2 Period Jitter,Pk-to-Pk* With capacitive decoupling between VDD and (measured from 10,000 samples) GND. * Note: Jitter performance depends on the programming parameters. -2 45 70 ps 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 12/12/06 Page 4 (Preliminary) PL611s-06 Low-Power Programmable Quick Turn Clock T M DC SPECIFICATIONS PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS Supply Current, Dynamic, with Loaded CMOS Outputs I DD @ VDD =3.3V, 27MHz, load=15pF 5.5 mA Supply Current, Dynamic, with Loaded CMOS Outputs I DD @ VDD =2.5V, 27MHz, load=15pF 3.5 mA Supply Current, Dynamic with Loaded CMOS Outputs I DD @Vdd=1.8V,27MHz, load=5pF 1.8 mA Supply Current, Dynamic, with Loaded CMOS Outputs I DD When PDB=0 Operating Voltage V DD Output Low Voltage V OL I OL = +4mA Standard Drive Output High Voltage V OH I OH = -4mA Standard Drive Output Current, Low Drive I OSD Output Current, Standard Drive Output Current, High Drive 1.62 <10 µA 3.63 V 0.4 V V DD – 0.4 V V OL = 0.4V, V OH = 2.4V 4 mA I OSD V OL = 0.4V, V OH = 2.4V 8 mA I OHD V OL = 0.4V, V OH = 2.4V 16 mA * Note: Please contact PhaseLink, if super low-power is required. CRYSTAL SPECIFICATIONS PARAMETERS Fundamental Crystal Resonator Frequency Crystal Loading Rating (The IC can be programmed for any value in this range.) SYMBOL MIN. F XIN C L (xtal) TYP. MAX. UNITS 10 30 MHz 8 12 pF 100 µW Maximum Sustainable Drive Level Operating Drive Level Metal Can Crystal 30 Shunt Capacitance ESR Max Small SMD Crystal Shunt Capacitance ESR Max µW C0 5.5 pF ESR 50 Ω C0 2.5 pF ESR 80 Ω 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 12/12/06 Page 5 (Preliminary) PL611s-06 Low-Power Programmable Quick Turn Clock T M LAYOUT RECOMMENDATIONS The following guidelines are to assist you with a performance optimized PCB design: - Keep all the PCB traces to the PL611s-06 as short as possible, as well as keeping all other traces as far away from it as possible. - Place a 0.01µF~0.1µF decoupling capacitor between VDD and GND, on the component side of the PCB, close to the VDD pin. It is not recommended to place this component on the backside of the PCB. Going through vias will reduce the signal integrity, causing additional jitter and phase noise. - It is highly recommended to keep the VDD and GND traces as short as possible. - When connecting long traces (> 1 inch) to a CMOS output, it is important to design the traces as a transmission line or ‘stripline’, to avoid reflections or ringing. In this case, the CMOS output needs to be matched to the trace impedance. Usually ‘striplines’ are designed for 50Ω impedance and CMOS outputs usually have lower than 50 Ω impedance so matching can be achieved by adding a resistor in series with the CMOS output pin to the ‘stripline’ trace. - Please contact PhaseLink for additional information on how to design outputs driving long traces or for the Gerber files for the PL611s-06 eval board shown. DFN-6L Evaluation Board 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 12/12/06 Page 6 (Preliminary) PL611s-06 Low-Power Programmable Quick Turn Clock T M PACKAGE DRAWINGS (GREEN PACKAGE COMPLIANT) SOT23-6L Symbol A A1 A2 b c D E H L e Dimension in MM Min. Max. 1.05 1.35 0.05 0.15 1.00 1.20 0.30 0.50 0.08 0.20 2.80 3.00 1.50 1.70 2.60 3.0 0.35 0.55 0.95 BSC Pin1 Dot E H D A2 A A1 C b e L SC70-6L Symbol A A1 A2 b c D E H L e Dimension in MM Min. Max. 0.80 1.00 0.00 0.09 0.80 0.91 0.15 0.30 0.08 0.25 1.85 2.25 1.15 1.35 2.00 2.30 0.21 0.41 0.65BSC Pin1 Dot E H D A2 A A1 C b e L DFN-6L D1 Symbol A A1 A3 b e D E D1 E1 L Dimension in MM Min. Max. 0.50 0.60 0.00 0.05 0.152 0.152 0.15 0.25 0.40BSC 1.25 1.35 1.95 2.05 0.75 0.85 0.95 1.05 0.20 0.30 b e D Pin 6 ID Chamfer E E1 L Pin1 Dot A A1 A3 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 12/12/06 Page 7 (Preliminary) PL611s-06 Low-Power Programmable Quick Turn Clock T M ORDERING INFORMATION (GREEN PACKAGE COMPLIANT) For part ordering, please contact our Sales Department: 47745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991 PART NUMBER The order number for this device is a combination of the following: Part number, Package type and Operating temperature range PL611s-06-XXX X X X PART NUMBER 3 DIGIT ID Code * (will be assigned at programming time) PACKAGE TYPE G=DFN-6L U=SC70-6L T=SOT-6L Part Number/Order Number PL611s-06-XXXGC-R PL611s-06-XXXUC-R PL611s-06-XXXTC-R † NONE= TUBE R=TAPE and REEL TEMPERATURE C=COMMERCIAL I=INDUSTRIAL Marking† XXX XXX 06XXX Package Option 6-Pin DFN (Tape and Reel) 6-Pin SC70 (Tape and Reel) 6-Pin SOT23 (Tape and Reel) Note: ‘XXX’ designates marking identifier that could be independent of the part number. PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of PhaseLink Corporation. Solder reflow profile available at www.phaselink.com/QA/solderingGreen.pdf 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 12/12/06 Page 8